2026-01-29 01:32:03.098 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.128.20:5700'
2026-01-29 01:32:03.099 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.128.20:5802)
2026-01-29 01:32:03.099 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.128.20:5801)
2026-01-29 01:32:03.099 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.128.22:6700'
2026-01-29 01:32:03.099 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.128.22:6802)
2026-01-29 01:32:03.099 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.128.22:6801)
2026-01-29 01:32:03.099 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.128.20:5700/1'
2026-01-29 01:32:03.099 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.128.20:5804)
2026-01-29 01:32:03.099 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.128.20:5803)
2026-01-29 01:32:03.099 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.128.20:5700/2'
2026-01-29 01:32:03.099 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.128.20:5806)
2026-01-29 01:32:03.099 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.128.20:5805)
2026-01-29 01:32:03.099 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.128.20:5700/3'
2026-01-29 01:32:03.099 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.128.20:5808)
2026-01-29 01:32:03.099 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.128.20:5807)
2026-01-29 01:32:03.099 [INFO] fake_trx.py:429 Init complete
2026-01-29 01:32:03.099 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-01-29 01:32:03.651 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:03.652 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:03.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:03.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:03.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:03.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:07.657 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:07.659 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:07.659 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.659 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:07.659 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 0 -> 1
2026-01-29 01:32:07.664 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:07.664 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:07.665 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:07.665 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:07.666 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.667 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:07.667 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 0 -> 1
2026-01-29 01:32:07.671 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:07.672 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:07.672 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:07.672 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.673 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:07.673 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.673 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:07.673 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 0 -> 1
2026-01-29 01:32:07.678 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:07.678 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:07.679 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:07.679 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:07.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:07.680 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.680 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:07.680 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 0 -> 1
2026-01-29 01:32:07.683 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:07.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:07.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:07.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:07.683 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:07.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:07.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.684 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:07.684 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:32:07.684 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:32:07.684 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:07.685 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:07.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:07.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:07.689 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:08.167 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:08.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.227 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:08.229 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:08.231 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:08.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:08.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:08.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:08.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:08.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:08.256 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:08.256 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:08.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:08.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:08.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.640 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:32:08.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:08.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:08.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:08.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:08.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:08.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:08.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:08.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:08.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:08.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:08.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:08.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:08.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:08.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:08.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:08.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:08.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:08.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.111 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:32:09.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:09.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:09.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:09.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:09.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:09.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:09.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:09.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:09.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:09.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:09.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:09.581 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:32:09.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:09.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:09.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:09.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:09.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:09.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:09.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:10.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:10.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:10.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:10.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:10.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:10.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:10.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:10.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:10.039 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:10.039 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:10.052 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:32:10.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:10.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:10.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:10.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:10.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:10.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:10.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:10.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:10.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:10.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:10.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:10.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:10.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:10.523 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:32:10.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:10.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:10.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:10.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:10.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:10.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:10.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:10.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:10.994 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:32:11.467 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:32:11.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:11.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:11.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:11.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:11.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:11.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:11.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:11.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:11.547 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:11.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:11.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:11.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:11.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:11.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:11.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:11.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:11.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:11.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:11.940 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:32:12.413 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:32:12.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:12.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:12.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:12.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:12.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:12.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:12.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:12.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:12.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:12.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:12.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:12.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:12.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:12.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:12.886 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:32:13.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:13.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:13.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:13.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:13.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:13.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:13.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:13.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:13.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:13.114 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:13.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:13.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:13.358 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:32:13.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:13.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:13.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:13.830 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:32:14.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:14.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:14.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:14.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:14.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:14.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:14.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:14.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:14.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:14.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:14.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:14.303 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:32:14.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:14.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:14.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:14.776 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:32:15.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:15.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:15.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:15.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:15.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:15.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:15.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.166 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:15.166 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:15.166 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:15.167 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:15.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:15.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:15.248 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:32:15.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:15.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:15.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:15.719 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:32:16.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:16.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:16.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:16.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:16.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:16.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:16.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:16.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:16.062 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:16.062 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:16.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:16.193 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:32:16.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:16.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:16.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:16.665 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:32:17.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:17.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:17.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:17.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:17.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:17.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.138 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:32:17.173 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:17.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:17.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:17.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:17.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:17.610 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:32:17.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:17.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:17.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:17.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:17.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.776 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:17.776 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:17.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:17.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:17.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:17.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:17.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.083 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:32:18.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:18.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:18.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:18.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.271 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.271 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:18.271 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:18.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.555 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:32:18.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:18.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:18.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:18.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:18.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.775 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:18.775 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:18.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:18.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:18.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:18.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:18.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.026 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:32:19.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:19.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:19.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:19.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:19.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:19.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:19.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:19.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:19.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:19.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:19.497 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:32:19.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:19.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:19.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:19.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:19.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:19.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:19.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:19.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:19.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:19.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:19.968 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:32:19.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:20.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:20.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:20.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:20.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:20.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:20.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:20.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:20.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:20.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:20.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:20.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:20.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:20.441 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:32:20.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:20.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:20.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:20.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:20.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:20.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:20.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:20.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:20.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:20.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:20.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:20.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:20.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:20.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:20.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:20.910 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:20.910 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:20.910 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:20.910 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.910 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.910 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.910 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.910 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:20.910 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:32:25.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:25.911 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:25.911 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:25.911 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:25.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:25.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:25.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:25.918 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:25.918 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:25.919 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:25.923 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:25.923 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:25.923 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:25.923 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:25.924 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.925 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:25.925 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:25.927 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:25.927 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:25.928 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:25.928 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:25.928 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.928 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:25.928 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:25.931 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:25.931 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:25.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:25.931 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:25.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:25.931 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:25.931 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.935 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:32:25.935 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:32:25.935 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:25.936 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:25.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:25.940 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:26.418 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:26.466 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:26.469 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:26.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.471 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:26.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:26.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:26.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:26.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.882 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:32:26.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:26.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:26.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:26.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:27.008 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:27.008 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:27.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:32.015 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:32.015 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:32.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:32.015 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:32.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:32.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:32.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:32.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:32.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:32.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:32.027 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:32.032 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:32.033 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:32.033 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:32.034 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:32.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:32.034 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:32.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:32.035 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:32.038 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:32.038 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:32.039 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:32.039 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:32.039 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:32.039 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:32.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:32.040 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:32.042 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:32.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:32.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:32.043 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:32.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:32.043 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:32.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:32.044 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:32:32.048 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:32:32.048 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:32.048 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:32.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:32.053 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:32.531 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:32.575 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:32.577 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:32.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:32.580 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:32.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:32.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:32.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:32.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:32.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:32.621 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:32.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:32.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:32.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:32.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:32.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:32.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:32.623 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:32.623 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:32.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:32.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:37.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:37.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:37.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:37.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:37.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:37.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:37.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:37.637 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:37.637 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:37.638 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:37.641 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:37.641 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:37.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:37.641 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:37.642 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.642 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:37.642 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:37.645 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:37.645 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:37.645 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:37.645 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:37.646 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.646 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:37.646 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:37.649 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:37.649 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:37.649 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:37.649 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:37.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:37.649 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.649 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:37.649 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:37.653 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:37.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.654 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:32:37.654 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:32:37.654 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:37.654 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:37.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:37.659 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:38.138 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:38.187 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:38.189 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:38.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:38.191 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:38.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:38.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:38.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:38.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:38.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:38.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:38.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:38.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:38.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:38.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:38.230 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:38.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:38.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:38.230 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:43.234 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:43.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:43.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:43.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:43.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:43.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:43.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:43.245 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:43.245 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:43.245 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:43.245 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:43.250 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:43.250 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:43.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:43.251 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:43.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:43.252 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:43.252 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:43.252 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:43.254 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:43.255 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:43.255 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:43.255 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:43.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:43.256 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:43.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:43.256 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:43.258 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:43.258 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:43.258 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:43.258 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:43.258 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:43.259 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:43.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:43.259 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:43.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:43.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:43.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:43.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:32:43.262 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:32:43.262 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:43.262 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:43.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:43.267 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:43.746 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:43.789 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:43.791 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:43.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:43.794 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:43.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:43.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:43.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:43.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:43.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:43.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:43.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:43.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:43.914 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:43.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:43.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:43.914 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:43.914 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:43.914 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:32:48.920 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:32:48.920 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:32:48.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:48.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:48.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:48.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:48.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:32:48.937 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:48.937 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.938 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:32:48.938 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:32:48.942 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:32:48.942 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:32:48.943 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:48.943 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:32:48.943 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.943 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:32:48.943 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:32:48.947 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:32:48.948 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:32:48.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:48.948 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:32:48.948 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:32:48.948 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:32:48.952 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:32:48.952 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:32:48.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:48.953 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:32:48.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:32:48.953 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:32:48.953 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:32:48.958 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:32:48.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:32:48.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.959 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:32:48.959 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:32:48.959 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:32:48.960 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:32:48.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:32:48.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:32:48.964 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:32:49.442 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:32:49.489 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:32:49.492 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:32:49.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:49.496 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:32:49.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:49.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:49.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:49.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:49.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:49.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:49.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:49.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:49.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:49.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:49.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:49.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:49.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:49.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:49.915 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:32:49.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:49.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:49.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:49.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:50.386 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:32:50.859 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:32:50.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:50.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:50.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:50.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:51.332 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:32:51.804 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:32:51.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:51.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:51.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:51.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:52.275 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:32:52.748 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:32:52.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:52.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:52.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:52.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:53.221 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:32:53.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:53.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:53.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:53.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:53.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:53.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:53.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:53.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:53.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:53.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:53.693 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:32:53.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:53.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:53.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:53.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:53.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:53.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:32:53.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:32:53.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:32:53.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:32:54.164 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:32:54.637 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:32:55.110 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:32:55.582 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:32:56.053 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:32:56.526 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:32:56.999 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:32:57.471 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:32:57.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:57.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:57.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:57.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:32:57.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:32:57.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:32:57.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:57.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:57.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:32:57.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:32:57.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:57.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:32:57.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:32:57.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:32:57.941 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:32:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:32:58.412 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:32:58.885 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:32:59.358 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:32:59.830 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:33:00.301 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:33:00.774 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:33:01.247 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:33:01.719 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:33:02.190 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:33:02.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:02.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:02.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:02.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:02.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:02.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:02.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:02.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:02.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:02.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:02.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:02.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:02.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:02.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:02.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:02.662 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:33:03.136 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:33:03.608 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:33:04.081 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:33:04.554 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:33:05.026 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:33:05.500 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:33:05.971 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:33:06.443 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:33:06.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:06.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:06.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:06.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:06.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:06.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:06.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:06.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:06.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:06.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:06.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:06.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:06.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:06.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:06.914 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:33:07.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:07.385 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:33:07.859 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:33:08.331 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:33:08.804 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:33:09.275 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:33:09.748 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:33:10.221 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:33:10.693 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:33:11.166 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:33:11.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:11.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:11.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:11.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:11.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:11.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:11.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:11.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:11.275 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:11.275 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:11.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:11.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:11.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:11.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:11.639 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:33:12.112 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:33:12.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:12.584 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:33:13.057 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:33:13.529 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:33:14.002 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:33:14.476 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:33:14.948 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:33:15.421 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:33:15.894 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:33:16.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:16.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:16.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:16.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:16.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:16.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:16.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:16.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:16.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:16.150 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:16.150 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:16.150 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:16.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:16.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:16.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:16.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:16.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:16.366 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:33:16.837 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:33:17.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:17.308 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:33:17.779 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:33:18.253 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:33:18.725 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:33:19.197 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:33:19.669 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:33:20.142 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:33:20.615 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:33:21.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:21.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:21.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:21.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:21.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:21.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:21.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:21.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:21.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:21.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:21.039 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:21.039 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:21.087 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:33:21.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:33:21.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:21.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:21.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:21.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:21.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:21.558 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:33:21.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:22.029 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:33:22.502 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:33:22.975 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:33:23.443 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:33:23.916 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:33:24.388 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:33:24.861 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:33:25.334 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:33:25.807 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:33:25.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:25.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:25.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:25.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:25.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:25.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:25.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:25.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:25.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:25.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:25.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:25.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:25.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:25.954 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:25.954 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:25.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:25.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:26.279 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:33:26.750 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:33:26.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:27.224 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:33:27.696 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:33:28.168 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:33:28.642 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:33:29.114 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:33:29.586 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:33:30.057 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:33:30.528 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:33:30.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:30.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:30.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:30.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:30.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:30.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:30.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:30.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:30.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:30.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:30.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:30.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:30.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:33:30.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:30.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:30.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:30.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:30.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:30.999 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:33:31.472 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:33:31.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:31.944 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:33:32.417 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:33:32.888 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:33:33.361 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:33:33.834 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:33:34.306 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:33:34.780 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:33:35.253 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:33:35.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:35.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:35.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:35.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:35.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:35.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:35.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:35.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:35.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:35.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:35.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:35.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:35.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:35.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:35.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:35.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:35.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:35.726 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:33:36.198 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:33:36.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:36.671 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:33:37.142 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:33:37.615 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:33:38.088 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:33:38.559 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:33:39.033 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:33:39.505 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:33:39.976 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:33:40.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:40.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:40.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:40.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:40.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:40.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:40.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:40.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:40.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:40.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:40.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:40.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:40.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:40.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:40.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:40.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:40.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:40.448 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:33:40.921 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:33:41.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:41.393 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:33:41.864 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:33:42.335 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:33:42.806 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:33:43.277 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:33:43.747 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:33:44.218 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:33:44.689 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:33:45.160 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:33:45.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:45.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:45.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:45.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:45.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:45.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:45.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:45.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:45.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:45.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:45.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:45.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:45.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:45.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:45.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:45.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:45.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:45.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:45.630 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:33:46.104 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:33:46.576 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:33:47.048 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:33:47.519 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:33:47.993 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:33:48.465 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:33:48.937 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:33:49.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:49.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:49.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:49.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:49.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:49.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:49.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:49.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:49.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:49.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:49.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:49.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:49.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:49.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:49.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:49.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:49.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:49.408 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:33:49.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:49.879 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:33:50.352 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:33:50.824 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:33:51.296 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:33:51.767 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:33:52.241 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:33:52.713 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:33:53.185 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:33:53.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:53.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:53.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:53.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:53.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:53.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:53.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:53.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:53.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:53.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:53.596 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:53.596 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:53.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:53.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:53.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:53.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:53.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:53.656 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 01:33:53.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:54.127 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 01:33:54.601 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 01:33:55.073 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 01:33:55.545 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 01:33:56.016 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 01:33:56.490 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 01:33:56.961 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 01:33:57.433 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 01:33:57.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:57.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:57.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:57.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:57.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:33:57.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:33:57.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:33:57.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:57.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:57.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:57.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:33:57.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:33:57.904 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 01:33:57.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:57.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:33:57.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:33:57.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:57.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:33:58.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:33:58.375 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 01:33:58.849 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 01:33:59.321 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 01:33:59.793 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 01:34:00.267 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 01:34:00.739 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 01:34:01.211 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 01:34:01.682 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 01:34:02.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:02.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:02.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:02.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:02.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:02.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:02.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:02.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:02.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:02.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:02.139 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:02.139 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:02.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:02.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:02.150 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:02.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:02.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:02.155 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 01:34:02.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:02.628 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 01:34:03.100 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 01:34:03.571 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 01:34:04.044 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 01:34:04.517 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 01:34:04.989 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 01:34:05.460 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 01:34:05.933 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 01:34:06.405 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 01:34:06.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:06.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:06.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:06.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:06.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:06.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:06.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:06.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:06.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:06.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:06.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:06.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:06.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:06.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:06.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:06.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:06.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:06.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:06.877 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 01:34:07.348 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 01:34:07.821 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 01:34:08.294 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 01:34:08.766 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 01:34:09.237 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 01:34:09.710 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 01:34:10.183 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 01:34:10.655 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 01:34:10.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:10.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:10.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:10.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:10.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:10.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:10.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:10.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:10.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:10.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:10.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:10.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:10.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:10.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:10.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:10.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:10.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:11.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:11.125 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 01:34:11.596 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 01:34:12.069 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 01:34:12.542 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 01:34:13.014 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 01:34:13.485 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 01:34:13.958 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 01:34:14.430 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 01:34:14.902 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 01:34:15.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:15.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:15.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:15.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:15.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:15.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:15.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:15.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:15.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:15.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:15.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:15.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:15.145 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:15.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:15.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:15.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:15.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:15.373 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 01:34:15.844 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 01:34:16.318 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 01:34:16.790 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 01:34:17.262 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 01:34:17.733 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 01:34:18.207 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 01:34:18.679 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 01:34:19.151 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 01:34:19.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:19.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:19.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:19.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:19.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:19.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:19.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:19.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:19.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:19.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:19.362 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:19.362 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:34:19.362 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:34:19.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:19.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:24.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:24.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:34:24.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:24.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:24.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:24.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:24.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:24.382 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:24.382 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:24.382 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:24.383 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:34:24.386 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:34:24.387 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:34:24.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:24.387 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:24.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:24.387 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:34:24.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:24.387 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:34:24.391 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:34:24.391 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:34:24.391 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:24.391 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:24.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:24.392 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:34:24.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:24.392 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:34:24.395 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:34:24.395 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:34:24.395 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:24.395 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:24.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:24.396 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:34:24.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:24.396 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:24.401 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:34:24.401 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:34:24.402 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:34:24.402 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:34:24.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:24.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:24.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:24.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:24.405 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:24.405 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:34:24.405 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:34:24.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:24.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:29.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:34:29.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:29.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:29.412 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:29.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:29.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:29.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:29.424 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:29.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:29.425 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:34:29.431 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:34:29.431 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:34:29.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:29.432 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:29.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:29.433 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:34:29.433 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:29.433 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:34:29.436 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:34:29.436 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:34:29.436 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:29.436 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:29.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:29.437 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:34:29.437 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:29.437 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:34:29.440 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:34:29.440 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:34:29.440 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:29.440 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:29.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:29.441 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:34:29.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:29.441 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.445 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:34:29.445 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:34:29.445 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:34:29.445 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:29.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:29.450 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:34:29.927 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:34:29.975 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:34:29.977 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:34:29.979 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:34:29.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:30.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:30.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:30.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:30.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:30.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:30.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:30.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.154 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:30.154 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:30.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.399 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:34:30.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:30.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:30.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:30.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:30.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:30.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:30.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:30.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.642 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:30.642 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:30.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:30.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:30.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:30.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:30.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:30.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:30.870 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:34:30.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:30.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:30.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:30.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:30.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:31.341 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:34:31.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:31.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:31.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:31.348 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:31.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:31.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:31.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:31.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:31.812 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:34:31.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:31.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:31.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:31.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:31.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:31.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:31.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:31.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:31.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:31.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:31.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.285 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:34:32.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:32.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:32.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:32.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:32.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:32.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:32.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.407 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:32.407 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:32.407 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:32.407 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:32.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:32.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:32.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:32.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:32.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:32.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:32.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:32.758 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:34:32.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:32.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:32.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:32.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:32.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:32.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:32.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:32.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:32.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:32.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:32.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:32.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:32.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:33.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:33.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:33.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.230 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:34:33.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:33.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:33.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:33.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:33.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:33.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:33.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:33.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:33.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:33.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:33.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:33.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:33.495 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:33.495 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:33.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:33.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:33.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:33.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:33.701 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:34:34.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:34.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:34.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:34.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:34.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:34.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.174 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:34:34.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:34.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:34.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:34.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:34.647 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:34:34.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:34.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:34.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:34.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:34.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:34.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:34.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:34.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:34.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:34.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:34.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.119 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:34:35.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:35.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:35.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:35.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:35.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:35.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:35.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:35.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:35.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:35.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:35.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:35.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.590 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:34:35.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:35.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:35.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:35.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:35.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:35.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:35.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:35.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:35.963 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:35.963 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:36.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.061 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:34:36.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:36.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:36.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:36.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:36.238 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:36.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.534 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:34:36.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:36.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:36.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:36.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:36.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.728 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:36.728 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:36.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:36.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:36.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:36.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:36.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.006 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:34:37.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:37.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:37.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:37.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.218 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:37.218 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:37.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.478 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:34:37.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:37.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:37.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:37.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:37.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:37.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:37.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:37.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:37.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:37.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:37.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:37.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:37.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:37.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:37.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:37.949 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:34:38.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:38.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:38.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:38.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:38.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:38.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:38.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:38.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:38.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:38.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:38.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:38.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:38.420 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:34:38.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:38.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:38.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:38.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:38.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:38.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:38.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:38.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:38.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:38.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:38.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:38.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:38.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:38.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:38.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:38.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:38.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:38.893 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:34:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:38.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:38.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:38.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:38.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:39.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:39.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:39.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:39.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:39.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:39.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:39.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:39.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:39.352 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:39.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:39.352 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:39.352 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:34:39.352 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:34:39.352 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:39.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:39.352 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:39.352 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:39.352 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:39.352 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:39.352 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:39.352 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:39.353 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:39.353 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2142 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:34:44.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:34:44.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:34:44.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:44.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:44.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:44.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:44.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:34:44.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:44.364 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:44.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:34:44.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:34:44.365 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:34:44.365 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:34:44.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:44.365 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:44.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:34:44.365 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:34:44.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:34:44.365 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:34:44.366 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:34:44.366 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:34:44.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:44.366 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:44.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:34:44.366 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:34:44.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:34:44.366 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:34:44.367 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:34:44.367 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:34:44.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:44.367 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:34:44.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:34:44.367 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:34:44.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:34:44.367 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:34:44.369 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:34:44.370 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:34:44.370 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:34:44.370 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:44.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:34:44.374 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:34:44.853 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:34:44.895 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:34:44.897 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:34:44.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:44.899 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:34:44.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:44.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:44.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:44.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:44.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:44.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:44.928 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:44.928 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:44.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:44.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:44.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:44.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:44.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:45.325 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:34:45.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:45.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:45.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:45.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:45.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:45.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:45.797 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:34:45.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:46.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:46.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:46.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:46.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:46.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:46.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:46.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:46.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:46.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:46.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:46.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:46.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:46.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:46.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:46.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:46.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:46.270 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:34:46.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:46.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:46.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:46.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:46.742 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:34:46.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:46.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:47.214 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:34:47.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:47.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:47.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:47.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:47.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:47.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:47.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:47.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:47.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:47.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:47.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:47.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:47.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:47.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:47.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:47.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:47.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:47.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:47.685 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:34:48.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.156 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:34:48.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:48.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:48.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:48.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:48.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:48.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:48.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:48.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:48.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:48.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:48.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:48.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:48.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:48.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:48.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:48.627 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:34:48.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:48.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:48.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:48.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:48.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:49.098 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:34:49.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:34:49.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:34:49.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:34:49.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:34:49.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:49.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:49.571 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:34:50.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:50.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:50.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:50.043 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:34:50.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:50.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:50.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:50.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:50.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:50.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:50.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:50.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:50.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:50.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:50.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:50.516 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:34:50.987 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:34:51.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.460 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:34:51.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:51.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:51.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:51.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:51.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:51.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:51.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:51.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:51.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:51.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:51.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:51.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:51.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:51.933 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:34:52.405 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:34:52.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:52.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:52.876 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:34:53.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:53.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:53.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:53.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:53.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:53.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:53.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:53.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:53.113 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:53.113 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:53.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:53.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:53.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:53.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:53.349 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:34:53.822 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:34:54.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.295 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:34:54.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:54.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:54.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:54.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:54.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:54.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:54.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:54.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:54.620 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:54.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:54.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:54.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:54.765 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:34:55.236 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:34:55.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:55.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:55.710 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:34:56.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:56.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:56.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:56.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:56.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:56.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:56.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:56.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:56.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:56.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:56.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:56.182 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:34:56.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:56.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:56.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:56.654 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:34:57.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:57.125 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:34:57.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:57.596 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:34:57.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:57.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:57.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:57.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:57.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:57.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:57.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:57.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:57.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:57.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:57.626 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:57.626 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:57.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:34:57.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:57.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:57.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:57.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:57.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:58.066 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:34:58.540 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:34:58.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:58.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:59.012 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:34:59.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:59.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:59.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:59.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:59.484 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:34:59.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:34:59.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:34:59.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:34:59.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:59.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:59.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:59.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:34:59.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:34:59.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:34:59.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:34:59.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:34:59.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:59.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:34:59.955 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:35:00.426 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:35:00.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:00.897 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:35:00.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:00.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:00.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:00.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:00.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:00.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:00.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:00.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:00.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:00.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:00.930 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:00.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:00.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:00.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:00.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:00.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:00.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:01.370 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:35:01.843 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:35:01.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:01.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:02.315 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:35:02.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:02.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:02.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:02.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:02.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:02.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:02.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:02.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:02.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:02.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:02.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:02.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:02.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:02.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:02.786 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:35:03.259 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:35:03.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:03.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:03.732 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:35:03.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:03.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:03.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:03.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:03.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:03.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:03.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:03.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:03.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:03.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:03.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:03.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:03.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:03.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:03.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:03.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:03.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:04.204 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:35:04.675 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:35:04.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:04.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:05.148 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:35:05.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:05.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:05.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:05.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:05.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:05.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:05.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:05.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:05.340 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:05.340 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:05.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:05.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:05.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:05.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:05.621 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:35:06.092 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:35:06.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:06.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:06.564 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:35:06.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:06.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:06.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:06.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:06.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:06.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:06.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:06.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:06.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:06.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:06.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:06.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:06.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:06.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:06.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:06.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:06.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:07.037 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:35:07.510 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:35:07.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:07.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:07.981 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:35:08.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:08.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:08.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:08.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:08.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:08.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:08.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:08.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:08.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:08.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:08.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:08.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:08.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:08.453 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:35:08.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:08.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:08.926 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:35:09.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:09.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:09.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:09.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:09.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:09.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:09.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:09.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:09.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:09.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:09.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:09.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:09.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:09.398 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:35:09.399 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:09.399 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:09.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:09.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:09.870 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:35:10.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:10.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:10.341 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:35:10.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:10.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:10.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:10.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:10.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:10.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:10.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:10.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:10.765 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:10.765 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:10.765 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:10.765 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:10.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:10.814 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:35:10.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:10.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:10.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:10.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:11.287 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:35:11.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:11.759 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:35:12.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:12.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:12.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:12.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:12.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:12.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:12.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:12.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:12.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:12.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:12.205 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:12.205 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:12.230 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:35:12.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:12.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:12.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:12.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:12.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:12.701 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:35:13.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:13.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:13.172 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:35:13.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:13.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:13.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:13.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:13.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:13.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:13.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:13.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:13.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:35:13.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:35:13.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:35:13.628 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:35:13.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:35:13.628 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:35:13.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:35:18.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:35:18.635 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:35:18.635 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:35:18.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:35:18.635 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:35:18.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:35:18.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:35:18.644 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:35:18.644 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:18.645 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:35:18.645 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:35:18.651 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:35:18.652 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:35:18.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:35:18.652 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:18.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:35:18.653 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:35:18.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:35:18.653 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:35:18.657 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:35:18.657 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:35:18.657 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:35:18.657 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:18.657 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:35:18.658 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:35:18.658 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:35:18.658 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:35:18.661 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:35:18.661 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:35:18.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:35:18.661 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:35:18.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:35:18.662 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:35:18.662 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:35:18.662 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:35:18.666 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:35:18.666 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:35:18.666 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:35:18.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:35:18.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:35:18.671 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:35:19.150 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:35:19.193 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:35:19.195 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:35:19.197 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:35:19.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:19.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:19.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:19.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:19.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:19.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:19.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:19.224 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:19.224 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:19.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:19.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:19.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:19.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:19.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:19.621 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:35:19.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:19.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:19.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:19.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:20.093 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:35:20.566 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:35:20.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:20.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:20.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:20.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:21.039 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:35:21.511 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:35:21.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:21.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:21.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:21.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:21.982 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:35:22.455 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:35:22.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:22.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:22.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:22.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:22.928 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:35:23.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:23.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:23.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:23.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:23.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:23.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:23.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:23.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:23.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:23.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:23.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:23.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:23.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:23.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:23.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:23.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:23.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:23.399 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:35:23.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:35:23.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:35:23.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:35:23.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:35:23.871 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:35:24.344 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:35:24.817 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:35:25.288 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:35:25.760 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:35:26.230 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:35:26.701 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:35:27.174 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:35:27.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:27.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:27.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:27.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:27.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:27.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:27.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:27.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:27.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:27.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:27.415 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:27.415 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:27.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:27.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:27.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:27.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:27.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:27.646 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:35:28.118 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:35:28.589 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:35:29.060 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:35:29.533 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:35:30.006 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:35:30.478 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:35:30.949 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:35:31.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:31.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:31.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:31.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:31.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:31.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:31.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:31.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:31.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:31.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:31.406 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:31.406 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:31.422 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:35:31.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:31.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:31.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:31.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:31.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:31.895 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:35:32.367 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:35:32.838 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:35:33.309 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:35:33.782 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:35:34.255 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:35:34.727 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:35:35.198 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:35:35.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:35.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:35.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:35.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:35.671 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:35:35.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:35.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:35.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:35.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:35.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:35.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:35.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:35.674 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:35.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:35.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:35.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:35.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:35.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:36.144 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:35:36.616 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:35:37.089 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:35:37.562 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:35:38.034 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:35:38.505 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:35:38.979 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:35:39.451 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:35:39.924 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:35:40.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:40.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:40.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:40.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:40.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:40.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:40.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:40.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:40.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:40.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:40.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:40.348 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:40.394 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:35:40.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:40.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:40.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:40.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:40.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:40.865 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:35:41.339 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:35:41.811 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:35:42.284 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:35:42.757 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:35:43.230 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:35:43.702 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:35:44.176 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:35:44.648 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:35:44.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:44.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:44.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:44.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:44.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:44.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:44.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:44.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:44.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:44.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:44.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:44.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:44.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:44.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:44.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:44.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:44.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:45.121 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:35:45.594 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:35:46.067 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:35:46.540 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:35:47.013 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:35:47.486 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:35:47.958 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:35:48.432 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:35:48.904 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:35:49.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:49.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:49.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:49.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:49.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:49.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:49.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:49.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:49.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:49.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:49.147 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:49.147 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:49.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:49.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:49.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:49.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:49.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:49.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:49.376 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:35:49.848 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:35:50.321 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:35:50.794 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:35:51.266 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:35:51.737 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:35:52.208 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:35:52.678 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:35:53.149 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:35:53.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:53.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:53.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:53.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:53.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:53.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:53.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:53.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:53.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:53.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:53.533 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:53.533 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:53.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:53.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:53.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:53.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:53.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:53.622 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:35:54.095 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:35:54.567 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:35:55.038 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:35:55.509 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:35:55.980 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:35:56.453 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:35:56.925 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:35:57.398 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:35:57.871 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:35:57.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:57.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:57.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:57.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:57.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:35:57.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:35:57.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:35:57.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:57.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:57.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:57.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:35:57.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:35:57.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:35:57.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:35:57.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:35:57.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:35:57.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:57.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:35:58.344 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:35:58.816 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:35:59.290 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:35:59.762 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:36:00.235 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:36:00.708 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:36:01.181 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:36:01.653 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:36:02.127 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:36:02.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:02.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:02.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:02.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:02.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:02.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:02.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:02.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:02.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:02.202 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:02.202 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:02.202 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:02.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:02.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:02.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:02.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:02.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:02.599 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:36:03.071 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:36:03.542 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:36:04.013 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:36:04.484 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:36:04.954 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:36:05.425 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:36:05.898 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:36:06.371 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:36:06.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:06.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:06.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:06.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:06.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:06.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:06.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:06.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:06.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:06.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:06.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:06.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:06.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:06.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:06.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:06.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:06.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:06.843 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:36:07.314 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:36:07.785 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:36:08.259 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:36:08.731 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:36:09.202 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:36:09.676 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:36:10.148 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:36:10.620 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:36:10.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:10.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:10.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:10.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:10.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:10.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:10.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:10.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:10.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:10.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:10.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:10.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:10.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:10.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:10.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:10.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:10.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:11.093 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:36:11.566 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:36:12.038 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:36:12.511 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:36:12.984 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:36:13.455 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:36:13.927 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:36:14.400 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:36:14.872 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:36:15.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:15.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:15.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:15.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:15.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:15.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:15.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:15.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:15.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:15.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:15.050 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:15.050 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:15.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:15.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:15.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:15.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:15.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:15.343 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:36:15.815 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:36:16.288 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:36:16.760 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:36:17.232 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:36:17.703 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:36:18.177 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:36:18.649 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:36:19.121 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:36:19.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:19.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:19.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:19.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:19.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:19.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:19.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:19.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:19.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:19.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:19.310 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:19.310 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:19.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:19.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:19.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:19.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:19.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:19.592 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:36:20.063 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:36:20.536 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:36:21.009 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:36:21.481 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:36:21.952 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:36:22.425 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:36:22.897 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:36:23.369 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 01:36:23.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:23.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:23.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:23.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:23.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:23.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:23.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:23.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:23.586 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:23.586 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:23.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:23.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:23.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:23.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:23.840 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 01:36:24.314 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 01:36:24.786 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 01:36:25.258 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 01:36:25.729 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 01:36:26.203 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 01:36:26.675 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 01:36:27.147 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 01:36:27.621 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 01:36:27.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:27.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:27.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:27.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:27.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:27.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:27.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:27.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:27.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:27.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:27.851 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:27.851 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:27.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:27.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:27.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:27.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:27.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:28.092 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 01:36:28.564 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 01:36:29.035 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 01:36:29.507 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 01:36:29.980 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 01:36:30.453 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 01:36:30.925 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 01:36:31.396 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 01:36:31.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:31.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:31.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:31.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:31.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:31.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:31.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:31.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:31.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:31.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:31.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:31.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:31.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:31.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:31.869 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 01:36:32.341 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 01:36:32.813 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 01:36:33.285 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 01:36:33.758 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 01:36:34.230 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 01:36:34.702 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 01:36:35.173 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 01:36:35.644 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 01:36:36.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:36.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:36.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:36.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:36.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:36.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:36.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:36.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:36.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:36.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:36.075 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:36.075 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:36.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:36.117 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 01:36:36.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:36.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:36.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:36.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:36.590 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 01:36:37.062 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 01:36:37.533 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 01:36:38.004 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 01:36:38.477 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 01:36:38.949 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 01:36:39.421 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 01:36:39.892 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 01:36:40.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:40.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:40.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:40.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:40.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:40.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:40.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:40.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:40.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:40.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:40.365 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 01:36:40.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:40.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:40.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:40.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:40.838 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 01:36:41.310 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 01:36:41.781 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 01:36:42.254 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 01:36:42.726 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 01:36:43.199 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 01:36:43.670 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 01:36:44.140 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 01:36:44.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:44.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:44.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:44.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:44.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:44.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:44.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:44.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:44.604 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:44.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:44.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:44.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:44.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:44.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:36:44.605 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:44.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=18565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:36:49.608 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:49.608 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:36:49.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:49.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:49.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:49.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:49.616 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:49.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:49.618 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:49.618 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:36:49.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:36:49.626 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:36:49.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:49.626 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:49.626 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:49.626 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:36:49.629 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:36:49.630 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:36:49.630 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:49.630 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:49.630 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.630 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:49.630 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:36:49.633 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:36:49.633 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:36:49.633 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:49.633 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:49.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:49.634 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:49.634 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:36:49.637 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:36:49.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:36:49.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:36:49.638 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:36:49.638 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:36:49.638 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:49.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:36:49.640 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:49.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.648 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:36:54.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:36:54.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:54.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:54.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:54.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:54.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:36:54.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:54.657 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:36:54.657 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:36:54.659 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:36:54.659 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:36:54.660 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:54.660 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:36:54.660 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.661 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:36:54.661 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:36:54.662 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:36:54.662 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:36:54.662 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:54.662 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:36:54.662 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.662 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:36:54.662 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:36:54.664 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:36:54.664 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:36:54.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:54.664 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:36:54.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:36:54.664 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:36:54.664 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:36:54.667 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:36:54.667 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:36:54.667 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:36:54.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:36:54.672 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:36:55.148 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:36:55.195 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:36:55.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:55.198 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:36:55.201 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:36:55.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:55.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:55.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:55.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:55.228 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:55.228 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:55.228 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:55.228 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:55.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:55.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:55.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:55.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:55.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:55.620 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:36:55.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:55.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:55.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:55.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:56.092 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:36:56.565 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:36:56.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:56.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:56.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:56.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:57.037 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:36:57.509 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:36:57.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:57.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:57.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:57.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:57.980 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:36:58.454 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:36:58.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:58.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:58.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:58.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:58.926 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:36:59.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:59.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:59.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:59.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:36:59.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:36:59.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:36:59.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:59.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:59.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:36:59.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:36:59.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:36:59.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:36:59.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:36:59.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:36:59.398 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:36:59.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:36:59.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:36:59.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:36:59.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:36:59.869 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:37:00.343 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:37:00.815 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:37:01.287 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:37:01.758 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:37:02.231 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:37:02.704 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:37:03.175 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:37:03.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:03.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:03.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:03.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:03.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:03.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:03.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:03.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:03.584 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:03.584 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:03.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:03.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:03.633 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:03.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:03.646 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:37:04.117 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:37:04.588 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:37:05.061 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:37:05.534 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:37:06.006 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:37:06.477 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:37:06.948 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:37:07.421 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:37:07.894 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:37:08.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:08.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:08.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:08.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:08.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:08.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:08.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:08.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:08.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:08.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:08.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:08.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:08.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:08.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:08.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:08.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:08.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:08.366 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:37:08.837 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:37:09.311 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:37:09.783 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:37:10.255 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:37:10.725 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:37:11.197 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:37:11.670 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:37:12.143 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:37:12.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:12.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:12.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:12.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:12.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:12.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:12.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:12.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:12.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:12.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:12.312 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:12.312 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:12.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:12.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:12.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:12.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:12.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:12.615 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:37:13.086 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:37:13.557 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:37:14.030 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:37:14.503 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:37:14.975 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:37:15.449 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:37:15.921 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:37:16.394 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:37:16.865 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:37:16.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:16.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:16.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:16.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:16.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:16.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:16.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:16.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:16.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:16.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:16.937 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:16.937 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:16.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:16.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:16.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:16.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:16.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:17.336 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:37:17.809 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:37:18.282 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:37:18.754 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:37:19.225 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:37:19.698 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:37:20.171 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:37:20.644 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:37:21.117 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:37:21.590 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:37:21.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:21.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:21.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:21.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:21.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:21.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:21.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:21.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:21.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:21.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:21.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:21.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:21.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:21.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:21.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:21.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:21.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:22.062 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:37:22.533 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:37:23.006 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:37:23.479 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:37:23.952 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:37:24.422 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:37:24.893 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:37:25.366 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:37:25.839 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:37:26.312 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:37:26.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:26.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:26.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:26.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:26.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:26.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:26.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:26.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:26.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:26.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:26.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:26.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:26.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:37:26.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:26.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:26.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:26.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:26.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:26.785 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:37:27.258 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:37:27.730 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:37:28.201 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:37:28.672 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:37:29.142 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:37:29.616 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:37:30.089 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:37:30.561 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:37:31.032 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:37:31.505 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:37:31.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:31.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:31.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:31.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:31.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:31.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:31.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:31.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:31.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:31.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:31.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:31.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:31.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:31.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:31.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:31.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:31.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:31.978 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:37:32.450 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:37:32.921 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:37:33.394 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:37:33.867 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:37:34.339 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:37:34.813 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:37:35.285 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:37:35.758 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:37:36.229 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:37:36.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:36.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:36.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:36.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:36.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:36.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:36.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:36.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:36.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:36.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:36.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:36.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:36.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:37:36.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:36.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:36.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:36.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:36.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:36.699 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:37:37.172 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:37:37.645 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:37:38.117 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:37:38.588 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:37:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:37:39.535 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:37:40.007 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:37:40.478 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:37:40.951 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:37:41.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:41.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:41.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:41.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:41.180 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=10048 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:37:41.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:41.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:41.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:41.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:41.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:41.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:41.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:41.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:41.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:41.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:41.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:41.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:41.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:41.424 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:37:41.896 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:37:42.367 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:37:42.841 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:37:43.313 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:37:43.785 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:37:44.258 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:37:44.731 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:37:45.203 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:37:45.674 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:37:45.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:45.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:45.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:45.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:46.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:46.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:46.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:46.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:46.009 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:46.009 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:46.009 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:46.009 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:46.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:46.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:46.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:46.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:46.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:46.145 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:37:46.616 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:37:47.089 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:37:47.561 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:37:48.033 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:37:48.505 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:37:48.975 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:37:49.446 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:37:49.917 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:37:50.390 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:37:50.863 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:37:50.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:50.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:50.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:50.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:50.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:50.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:50.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:50.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:50.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:50.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:50.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:50.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:50.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:50.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:50.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:50.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:50.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:51.335 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:37:51.806 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:37:52.279 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:37:52.751 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:37:53.224 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:37:53.697 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:37:54.170 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:37:54.642 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:37:54.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:54.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:54.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:54.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:54.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:54.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:54.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:54.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:54.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:54.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:54.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:54.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:55.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:55.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:55.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:55.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:55.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:55.114 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:37:55.587 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:37:56.059 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:37:56.533 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:37:57.005 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:37:57.477 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:37:57.948 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:37:58.419 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:37:58.893 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:37:59.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:59.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:59.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:59.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:59.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:37:59.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:37:59.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:37:59.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:59.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:59.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:59.253 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:37:59.253 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:37:59.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:37:59.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:37:59.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:37:59.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:59.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:37:59.363 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 01:37:59.831 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 01:38:00.305 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 01:38:00.777 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 01:38:01.249 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 01:38:01.723 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 01:38:02.195 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 01:38:02.667 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 01:38:03.138 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 01:38:03.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:03.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:03.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:03.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:03.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:03.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:03.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:03.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:03.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:03.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:03.516 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:03.516 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:03.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:03.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:03.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:03.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:03.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:03.611 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 01:38:04.084 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 01:38:04.556 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 01:38:05.027 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 01:38:05.500 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 01:38:05.972 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 01:38:06.444 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 01:38:06.915 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 01:38:07.389 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 01:38:07.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:07.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:07.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:07.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:07.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:07.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:07.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:07.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:07.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:07.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:07.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:07.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:07.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:07.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:07.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:07.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:07.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:07.861 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 01:38:08.333 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 01:38:08.804 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 01:38:09.277 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 01:38:09.750 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 01:38:10.222 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 01:38:10.693 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 01:38:11.166 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 01:38:11.639 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 01:38:12.110 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 01:38:12.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:12.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:12.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:12.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:12.199 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=16749 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:12.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:12.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:12.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:12.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:12.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:12.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:12.217 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:12.217 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:12.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:12.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:12.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:12.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:12.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:12.582 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 01:38:13.055 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 01:38:13.528 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 01:38:13.999 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 01:38:14.471 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 01:38:14.944 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 01:38:15.416 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 01:38:15.888 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 01:38:16.359 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 01:38:16.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:16.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:16.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:16.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:16.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:16.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:16.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:16.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:16.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:16.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:16.479 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:16.479 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:16.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:16.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:16.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:16.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:16.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:16.833 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 01:38:17.305 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 01:38:17.777 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 01:38:18.248 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 01:38:18.721 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 01:38:19.194 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 01:38:19.666 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 01:38:20.137 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 01:38:20.608 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 01:38:20.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:20.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:20.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:20.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:20.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:20.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:20.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:20.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:20.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:20.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:20.754 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:20.754 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:20.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:20.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:20.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:20.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:20.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:21.081 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 01:38:21.553 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 01:38:22.025 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 01:38:22.496 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 01:38:22.970 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 01:38:23.442 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 01:38:23.914 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 01:38:24.385 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 01:38:24.859 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 01:38:25.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:25.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:25.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:25.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:25.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:25.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:25.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:25.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:25.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:25.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:25.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:25.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:25.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:25.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:38:25.019 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:38:25.019 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19519 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:25.019 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19519 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:25.019 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19519 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:25.019 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19519 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:38:30.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:30.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:38:30.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:30.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:30.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:30.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:30.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:30.031 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:30.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:30.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:30.032 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:38:30.034 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:38:30.034 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:38:30.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:30.035 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:30.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:30.035 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:38:30.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:30.036 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:38:30.037 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:38:30.037 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:38:30.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:30.037 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:30.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:30.037 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:38:30.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:30.037 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:38:30.039 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:38:30.039 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:38:30.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:30.039 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:30.039 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:30.039 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:38:30.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:30.039 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:38:30.042 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:38:30.042 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:38:30.042 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:30.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:30.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:38:30.043 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:38:30.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:30.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.051 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:38:35.051 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:38:35.051 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:35.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:35.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:35.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:35.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:38:35.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:35.059 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:35.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:38:35.060 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:38:35.062 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:38:35.062 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:38:35.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:35.063 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:35.063 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:38:35.063 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:38:35.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:38:35.064 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:38:35.065 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:38:35.065 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:38:35.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:35.065 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:35.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:38:35.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:38:35.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:38:35.066 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:38:35.067 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:38:35.067 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:38:35.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:35.067 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:38:35.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:38:35.067 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:38:35.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:38:35.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.070 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:38:35.070 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:38:35.070 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:38:35.070 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:38:35.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:38:35.075 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:38:35.553 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:38:35.596 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:38:35.598 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:38:35.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:35.600 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:38:35.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:35.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:35.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:35.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:35.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:35.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:35.629 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:35.629 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:35.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:35.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:35.651 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:35.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:35.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.025 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:38:36.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:36.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:36.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:36.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:36.497 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:38:36.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:36.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:36.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:36.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:36.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:36.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:36.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:36.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:36.716 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:36.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:36.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:36.765 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:36.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:36.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:36.970 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:38:37.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:37.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:37.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:37.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:37.443 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:38:37.914 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:38:38.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:38.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:38.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:38.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:38.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:38.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:38.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:38.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:38.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:38.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:38.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:38.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:38.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:38.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:38.159 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:38.159 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:38.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:38.204 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:38.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:38.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:38.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:38.386 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:38:38.859 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:38:39.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:39.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:39.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:39.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:39.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:39.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:39.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:39.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:39.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:39.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:39.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:39.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:39.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:39.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:39.330 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:38:39.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:39.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:39.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:39.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:39.802 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:38:40.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:38:40.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:38:40.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:38:40.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:38:40.274 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:38:40.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:40.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:40.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:40.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:40.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:40.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:40.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:40.747 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:38:40.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:40.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:40.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:40.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:40.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:40.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:40.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:40.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:40.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:40.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:41.220 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:38:41.692 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:38:41.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:41.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:41.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:41.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:41.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:41.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:41.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:41.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:41.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:41.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:41.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:41.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:41.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:41.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:41.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:41.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:41.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.163 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:38:42.636 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:38:42.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:42.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:42.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:42.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:42.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:42.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:42.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:42.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:42.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:42.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:42.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:42.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:42.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:42.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:42.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:43.108 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:38:43.581 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:38:43.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:43.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:43.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:43.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:43.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:43.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:43.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:43.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:43.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:43.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:43.878 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:43.878 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:43.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:43.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:43.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:43.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:43.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:43.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:44.054 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:38:44.527 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:38:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:44.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:44.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:44.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:44.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:44.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:44.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:44.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:44.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:44.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:44.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:44.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:44.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:44.954 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:44.954 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:44.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:44.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:44.999 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:38:45.470 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:38:45.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:45.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:45.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:45.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:45.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:45.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:45.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:45.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:45.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:45.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:45.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:45.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:45.941 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:38:45.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:38:45.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:45.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:45.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:45.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:45.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:46.412 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:38:46.883 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:38:47.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:47.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:47.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:47.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:47.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:47.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:47.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:47.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:47.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:47.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:47.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:47.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:47.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:47.355 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:38:47.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:47.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:47.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:47.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:47.828 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:38:48.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:48.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:48.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:48.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:48.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:48.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:48.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:48.271 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:48.271 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:48.271 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:48.300 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:38:48.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:48.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:48.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:48.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:48.771 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:38:49.245 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:38:49.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:49.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:49.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:49.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:49.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:49.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:49.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:49.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:49.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:49.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:49.289 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:49.289 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:49.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:49.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:49.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:49.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:49.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:49.717 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:38:50.189 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:38:50.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:50.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:50.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:50.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:50.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:50.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:50.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:50.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:50.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:50.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:50.367 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:50.367 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:50.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:50.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:50.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:50.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:50.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:50.660 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:38:51.131 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:38:51.599 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:38:51.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:51.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:51.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:51.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:51.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:51.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:51.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:51.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:51.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:51.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:51.775 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:51.775 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:51.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:51.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:51.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:51.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:51.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:52.063 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:38:52.527 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:38:52.999 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:38:53.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:53.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:53.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:53.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:53.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:53.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:53.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:53.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:53.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:53.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:53.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:53.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:53.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:53.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:53.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:53.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:53.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:53.469 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:38:53.941 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:38:54.413 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:38:54.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:54.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:54.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:54.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:54.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:54.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:54.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:54.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:54.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:54.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:54.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:54.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:54.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:54.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:54.884 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:38:55.355 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:38:55.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:55.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:55.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:55.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:55.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:55.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:55.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:55.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:55.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:55.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:55.770 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:55.770 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:55.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:55.827 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:38:55.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:55.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:55.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:55.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:56.300 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:38:56.772 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:38:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:57.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:57.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:57.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:57.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:57.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:57.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:57.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:57.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:57.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:57.242 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:38:57.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:57.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:57.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:57.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:57.714 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:38:58.186 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:38:58.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:58.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:58.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:58.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:58.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:38:58.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:38:58.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:38:58.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:58.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:58.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:58.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:38:58.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:38:58.657 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:38:58.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:38:58.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:38:58.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:38:58.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:58.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:38:59.128 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:38:59.601 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:39:00.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:00.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:00.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:00.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:00.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:00.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:00.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:00.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:00.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:00.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:00.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:00.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:00.054 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:00.054 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:39:00.054 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:39:05.062 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:05.062 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:39:05.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:05.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:05.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:05.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:05.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:05.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:05.072 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:05.072 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:05.072 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:39:05.076 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:39:05.077 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:39:05.077 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:05.077 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:05.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:05.077 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:39:05.077 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:05.077 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:39:05.081 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:39:05.082 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:39:05.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:05.082 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:05.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:05.082 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:39:05.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:05.082 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:39:05.085 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:39:05.085 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:39:05.086 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:05.086 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:05.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:05.086 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:39:05.086 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:05.086 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:39:05.089 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:39:05.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:39:05.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:39:05.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:39:05.090 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:39:05.090 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:39:05.090 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:05.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:05.095 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:39:05.572 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:39:05.613 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:39:05.616 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:39:05.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:05.617 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:39:05.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:05.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:05.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:05.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:05.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:05.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:05.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:05.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:05.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:05.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:05.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:05.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:05.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:06.041 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:39:06.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:06.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:06.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:06.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:06.515 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:39:06.987 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:39:07.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:07.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:07.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:07.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:07.458 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:39:07.932 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:39:08.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:08.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:08.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:08.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:08.404 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:39:08.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:08.876 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:39:09.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:09.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:09.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:09.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:09.347 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:39:09.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:09.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:09.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:09.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:09.421 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=936 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:09.421 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=936 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:09.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:09.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:09.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:09.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:09.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:09.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:09.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:09.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:09.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:09.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:09.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:09.821 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:39:10.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:10.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:10.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:10.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:10.293 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:39:10.766 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:39:11.236 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:39:11.707 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:39:12.180 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:39:12.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:12.653 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:39:13.125 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:39:13.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:13.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:13.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:13.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:13.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:13.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:13.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:13.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:13.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:13.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:13.293 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:13.293 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:13.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:13.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:13.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:13.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:13.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:13.596 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:39:14.069 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:39:14.542 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:39:15.014 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:39:15.485 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:39:15.956 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:39:16.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:16.427 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:39:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:16.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:16.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:16.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:16.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:16.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:16.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:16.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:16.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:16.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:16.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:16.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:16.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:16.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:16.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:16.899 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:39:17.372 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:39:17.845 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:39:18.316 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:39:18.789 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:39:19.261 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:39:19.734 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:39:19.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:20.207 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:39:20.679 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:39:20.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:20.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:20.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:20.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:20.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:20.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:20.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:20.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:20.756 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:20.756 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:20.756 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:20.756 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:20.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:20.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:20.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:20.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:20.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:21.151 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:39:21.623 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:39:22.093 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:39:22.564 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:39:23.035 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:39:23.506 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:39:23.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:23.979 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:39:24.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:24.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:24.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:24.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:24.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:24.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:24.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:24.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:24.419 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:24.419 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:24.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:24.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:24.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:24.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:24.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:24.452 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:39:24.924 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:39:25.395 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:39:25.868 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:39:26.340 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:39:26.812 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:39:27.284 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:39:27.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:27.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:27.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:27.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:27.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:27.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:27.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:27.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:27.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:27.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:27.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:27.741 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:27.741 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:27.754 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:39:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:27.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:27.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:27.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:27.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:28.225 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:39:28.699 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:39:29.171 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:39:29.643 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:39:30.114 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:39:30.587 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:39:30.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:31.060 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:39:31.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:31.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:31.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:31.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:31.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:31.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:31.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:31.455 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:31.456 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:31.456 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:31.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:31.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:31.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:31.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:31.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:31.532 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:39:32.003 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:39:32.476 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:39:32.948 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:39:33.420 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:39:33.894 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:39:34.366 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:39:34.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:34.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:34.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:34.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:34.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:34.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:34.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:34.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:34.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:34.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:34.769 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:34.769 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:39:34.769 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:39:34.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:34.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:39.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:39:39.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:39:39.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:39.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:39.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:39.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:39.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:39:39.779 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:39.779 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:39.779 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:39:39.779 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:39:39.780 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:39:39.780 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:39:39.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:39.780 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:39.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:39:39.780 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:39:39.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:39:39.780 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:39:39.781 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:39:39.781 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:39:39.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:39.781 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:39.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:39:39.781 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:39:39.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:39:39.781 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:39:39.782 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:39:39.783 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:39:39.783 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:39.783 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:39:39.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:39:39.783 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:39:39.783 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:39:39.783 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:39:39.785 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:39:39.785 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:39:39.785 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:39:39.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:39:39.790 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:39:40.267 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:39:40.310 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:39:40.312 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:39:40.315 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:39:40.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:40.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:40.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:40.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:40.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:40.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:40.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:40.347 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:40.347 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:40.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:40.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:40.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:40.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:40.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:40.740 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:39:40.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:40.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:40.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:40.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:41.211 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:39:41.682 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:39:41.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:41.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:41.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:41.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:42.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:39:42.628 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:39:42.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:42.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:42.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:42.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:43.100 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:39:43.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:43.574 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:39:43.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:43.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:43.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:43.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:44.046 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:39:44.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:44.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:44.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:44.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:44.122 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=936 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:44.122 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=936 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:44.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:44.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:44.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:44.123 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:44.123 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:44.123 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:44.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:44.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:44.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:44.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:44.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:44.519 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:39:44.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:39:44.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:39:44.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:39:44.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:39:44.990 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:39:45.463 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:39:45.936 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:39:46.408 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:39:46.882 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:39:47.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:47.354 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:39:47.826 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:39:47.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:47.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:47.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:47.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:47.974 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1768 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:47.974 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1768 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:47.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:47.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:47.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:47.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:47.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:47.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:48.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:48.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:48.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:48.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:48.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:48.300 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:39:48.772 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:39:49.244 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:39:49.715 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:39:50.189 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:39:50.661 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:39:51.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:51.134 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:39:51.607 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:39:51.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:51.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:51.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:51.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:51.827 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=2600 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:51.827 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=2600 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:39:51.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:51.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:51.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:51.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:51.827 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:51.827 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:51.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:51.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:51.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:51.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:51.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:52.080 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:39:52.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:52.552 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:39:52.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:52.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:52.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:52.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:52.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:52.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:52.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:52.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:52.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:52.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:52.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:52.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:52.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:52.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:52.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:52.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:52.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:53.023 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:39:53.497 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:39:53.969 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:39:54.441 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:39:54.912 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:39:55.385 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:39:55.858 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:39:55.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:56.330 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:39:56.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:56.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:56.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:39:56.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:39:56.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:39:56.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:56.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:56.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:56.406 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:39:56.406 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:39:56.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:39:56.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:39:56.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:39:56.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:56.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:39:56.801 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:39:57.272 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:39:57.745 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:39:58.217 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:39:58.689 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:39:59.161 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:39:59.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:39:59.634 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:40:00.106 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:40:00.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:00.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:00.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:00.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:00.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:00.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:00.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:00.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:00.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:00.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:00.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:00.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:00.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:00.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:00.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:00.578 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:40:01.049 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:40:01.523 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:40:01.995 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:40:02.467 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:40:02.941 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:40:03.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:03.413 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:40:03.886 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:40:04.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:04.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:04.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:04.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:04.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:04.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:04.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:04.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:04.110 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:04.110 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:04.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:04.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:04.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:04.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:04.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:04.357 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:40:04.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:04.827 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:40:05.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:05.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:05.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:05.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:05.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:05.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:05.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:05.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:05.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:05.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:05.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:05.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:05.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:05.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:05.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:05.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:05.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:05.300 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:40:05.773 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:40:06.245 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:40:06.716 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:40:07.189 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:40:07.662 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:40:08.133 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:40:08.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:08.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:08.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:08.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:08.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:08.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:08.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:08.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:08.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:08.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:08.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:08.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:08.605 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:40:08.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:08.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:08.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:08.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:09.075 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:40:09.546 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:40:10.017 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:40:10.490 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:40:10.963 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:40:11.434 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:40:11.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:11.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:11.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:11.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:11.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:11.874 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=6931 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:11.874 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=6931 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:11.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:11.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:11.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:11.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:11.875 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:11.875 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:11.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:11.906 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:40:11.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:11.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:11.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:11.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:12.377 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:40:12.850 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:40:13.322 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:40:13.794 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:40:14.265 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:40:14.736 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:40:14.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:15.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:15.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:15.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:15.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:15.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:15.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:15.176 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:15.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:15.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:15.177 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:15.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:15.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:15.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:15.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:15.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:15.209 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:40:15.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:15.682 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:40:16.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:16.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:16.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:16.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:16.122 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=7849 tn=3 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:16.122 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=7849 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:16.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:16.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:16.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:16.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:16.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:16.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:16.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:16.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:16.153 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:40:16.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:16.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:16.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:16.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:16.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:16.625 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:40:17.098 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:40:17.570 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:40:18.042 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:40:18.515 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:40:18.988 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:40:19.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:19.460 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:40:19.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:19.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:19.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:19.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:19.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:19.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:19.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:19.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:19.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:19.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:19.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:19.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:19.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:19.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:19.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:19.931 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:40:20.404 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:40:20.877 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:40:21.349 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:40:21.820 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:40:22.290 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:40:22.761 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:40:22.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:23.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:23.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:23.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:23.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:23.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:23.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:23.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:23.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:23.156 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:23.156 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:23.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:23.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:23.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:23.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:23.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:23.232 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:40:23.706 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:40:24.178 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:40:24.650 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:40:25.121 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:40:25.594 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:40:26.066 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:40:26.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:26.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:26.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:26.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:26.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:26.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:26.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:26.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:26.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:26.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:40:26.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:26.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:26.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:26.539 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:40:27.009 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:40:27.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:27.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:27.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:27.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:27.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:27.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:27.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:27.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:27.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:27.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:27.408 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:27.408 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:40:27.408 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:40:32.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:32.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:40:32.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:32.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:32.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:32.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:32.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:32.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:32.425 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:32.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:32.425 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:40:32.429 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:40:32.430 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:40:32.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:32.430 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:32.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:32.431 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:40:32.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:32.432 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:40:32.434 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:40:32.435 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:40:32.435 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:32.435 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:32.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:32.436 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:40:32.436 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:32.436 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:40:32.439 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:40:32.439 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:40:32.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:32.439 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:32.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:32.440 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:40:32.440 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:32.440 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:40:32.443 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:40:32.444 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:40:32.444 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:40:32.444 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:32.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:32.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:32.449 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:40:32.928 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:40:32.970 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:40:32.973 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:40:32.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:32.975 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:40:32.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:32.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:32.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:32.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:32.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:32.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:32.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:32.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:33.400 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:40:33.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:33.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:33.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:33.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:33.871 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:40:34.342 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:40:34.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:34.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:34.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:34.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:34.813 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:40:35.286 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:40:35.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:35.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:35.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:35.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:35.759 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:40:36.230 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:40:36.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:36.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:36.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:36.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:36.702 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:40:37.172 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:40:37.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:37.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:37.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:37.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:37.643 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:40:38.113 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:40:38.585 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:40:39.055 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:40:39.526 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:40:39.996 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:40:40.468 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:40:40.938 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:40:41.407 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:40:41.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:41.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:41.760 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=2017 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:41.760 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=2017 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:41.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:41.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:41.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:41.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:41.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:41.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:41.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:41.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:41.770 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:41.770 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:40:41.770 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:40:41.770 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:41.770 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:41.770 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:41.770 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:41.771 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:41.771 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:46.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:46.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:40:46.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:46.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:46.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:46.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:46.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:46.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:46.780 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:46.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:40:46.780 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:40:46.785 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:40:46.785 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:40:46.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:46.785 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:46.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:46.786 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:40:46.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:40:46.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:40:46.790 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:40:46.790 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:40:46.790 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:46.790 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:46.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:46.791 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:40:46.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:40:46.791 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:40:46.795 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:40:46.795 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:40:46.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:46.795 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:40:46.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:46.795 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:40:46.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:40:46.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:40:46.801 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:40:46.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:40:46.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:40:46.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:40:46.801 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:40:46.802 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:40:46.802 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:40:46.802 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:40:46.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:40:46.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:40:46.807 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:40:47.285 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:40:47.335 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:40:47.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:40:47.338 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:40:47.341 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:40:47.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:47.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:47.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:40:47.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:40:47.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:40:47.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:40:47.347 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:40:47.347 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:40:47.753 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:40:47.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:47.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:47.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:47.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:48.224 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:40:48.694 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:40:48.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:48.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:48.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:48.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:49.166 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:40:49.636 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:40:49.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:49.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:49.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:49.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:50.106 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:40:50.577 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:40:50.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:50.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:50.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:50.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:51.049 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:40:51.520 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:40:51.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:51.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:51.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:51.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:51.990 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:40:52.461 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:40:52.932 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:40:53.402 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:40:53.873 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:40:54.343 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:40:54.815 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:40:55.285 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:40:55.756 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:40:56.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:40:56.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:40:56.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:40:56.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:40:56.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:40:56.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:40:56.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:40:56.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:40:56.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:40:56.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:40:56.126 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:40:56.126 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:40:56.126 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:40:56.127 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2020 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:56.127 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2020 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:56.127 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2020 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:56.127 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2020 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:56.127 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2020 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:40:56.127 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2020 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:01.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:01.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:01.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:01.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:01.129 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:01.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:01.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:01.137 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:01.138 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:01.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:01.138 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:01.142 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:01.142 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:01.143 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:01.143 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:01.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:01.144 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:01.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:01.145 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:01.147 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:01.147 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:01.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:01.148 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:01.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:01.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:01.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:01.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:01.151 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:01.151 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:01.151 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:01.151 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:01.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:01.152 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:01.152 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:01.152 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.155 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:41:01.155 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:41:01.155 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:01.155 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:01.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:01.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:01.160 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:01.639 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:01.678 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:01.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:01.682 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:01.684 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:01.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:01.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:01.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:02.111 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:02.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:02.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:02.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:02.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:02.587 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:02.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:02.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:02.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:02.690 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:02.690 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:03.059 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:03.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:03.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:03.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:03.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:03.530 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:04.001 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:41:04.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:04.162 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:04.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:04.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:04.474 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:41:04.944 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:41:05.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:05.162 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:05.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:05.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:05.412 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:41:05.884 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:41:06.163 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:06.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:06.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:06.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:06.354 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:41:06.825 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:41:07.295 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:41:07.766 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:41:08.237 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:41:08.707 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:41:09.178 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:41:09.648 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:41:10.114 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:41:10.582 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:41:11.051 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:41:11.519 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:41:11.990 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:41:12.463 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:41:12.935 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:41:13.407 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:41:13.878 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:41:14.351 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:41:14.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:14.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:14.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:14.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:14.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:14.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:14.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:14.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:14.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:14.490 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:14.490 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:14.490 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:14.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:19.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:19.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:19.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:19.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:19.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:19.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:19.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:19.507 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:19.507 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:19.508 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:19.508 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:19.512 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:19.512 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:19.512 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:19.512 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:19.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:19.513 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:19.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:19.513 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:19.517 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:19.517 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:19.517 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:19.517 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:19.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:19.517 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:19.517 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:19.517 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:19.521 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:19.522 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:19.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:19.522 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:19.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:19.522 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:19.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:19.522 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:19.526 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:19.526 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:41:19.527 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:41:19.527 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:19.527 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:19.532 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:20.009 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:20.055 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:20.058 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:20.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:20.060 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:20.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:20.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:20.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:20.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:20.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:20.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:20.065 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:20.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:20.481 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:20.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:20.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:20.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:20.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:20.952 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:21.099 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:21.426 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:21.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:21.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:21.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:21.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:21.625 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:21.898 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:22.146 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:22.370 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:41:22.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:22.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:22.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:22.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:22.841 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:41:23.312 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:41:23.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:23.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:23.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:23.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:23.785 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:41:24.161 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:24.258 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:41:24.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:24.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:24.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:24.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:24.696 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:24.730 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:41:25.201 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:41:25.213 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:25.674 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:41:25.730 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:26.147 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:41:26.619 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:41:27.092 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:41:27.564 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:41:27.736 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:28.036 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:41:28.510 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:41:28.982 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:41:29.454 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:41:29.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:29.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:29.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:29.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:29.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:29.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:29.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:29.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:29.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:29.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:29.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:29.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:29.796 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:29.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2218 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:29.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2218 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:29.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2218 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:29.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2218 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:29.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2218 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:29.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2218 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:34.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:34.799 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:34.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:34.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:34.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:34.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:34.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:34.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:34.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:34.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:34.807 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:34.808 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:34.808 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:34.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:34.808 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:34.808 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:34.808 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:34.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:34.808 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:34.810 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:34.810 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:34.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:34.810 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:34.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:34.810 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:34.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:34.810 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:34.812 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:34.812 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:34.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:34.812 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:34.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:34.812 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:34.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:34.812 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:41:34.814 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:41:34.814 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:34.814 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:34.819 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:35.296 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:35.339 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:35.341 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:35.344 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:35.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:35.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:35.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:35.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:35.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:35.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:35.369 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:35.369 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:35.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:35.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:35.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:35.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:35.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:35.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:35.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:35.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:35.484 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:35.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:35.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:35.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:35.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:35.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:35.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:35.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:35.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:35.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:35.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:35.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:35.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:35.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:35.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:35.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:35.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:35.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:35.738 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:35.738 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:35.768 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:35.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:35.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:35.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:35.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:35.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:35.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:35.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:35.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:35.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:35.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:35.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:35.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:35.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:35.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:35.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:35.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:35.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:35.998 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:35.998 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.239 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:36.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.256 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.256 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.318 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.318 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:36.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.512 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.512 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.598 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.598 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.634 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.634 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.705 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:36.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:36.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:36.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:36.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:36.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:36.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:36.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:36.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:36.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:36.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:36.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:36.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:36.850 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:36.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:36.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:37.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:37.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:37.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.176 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:37.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:37.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.296 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:37.296 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:37.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:37.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:37.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:37.556 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:37.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:37.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.603 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.647 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:41:37.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:37.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:37.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:37.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:37.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.807 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:37.807 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:37.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:37.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:37.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:37.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:37.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:37.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:37.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:37.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:37.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:38.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:38.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:38.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:38.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:38.120 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:41:38.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:38.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:38.297 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=755 tn=2 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:38.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:38.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:38.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.316 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:38.316 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:38.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:38.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:38.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:38.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:38.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:38.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:38.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:38.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:38.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:38.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:38.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:38.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:38.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:38.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:38.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:38.562 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:38.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:38.562 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:43.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:43.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:43.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:43.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:43.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:43.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:43.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:43.577 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:43.577 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:43.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:43.578 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:43.583 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:43.583 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:43.583 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:43.583 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:43.583 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:43.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:43.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:43.584 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:43.588 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:43.589 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:43.589 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:43.589 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:43.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:43.589 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:43.589 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:43.589 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:43.592 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:43.592 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:43.592 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:43.592 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:43.592 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:43.592 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:43.593 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:43.593 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:43.596 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:43.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:43.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:43.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:43.596 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:43.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:41:43.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:41:43.597 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:43.597 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:43.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:43.602 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:44.080 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:44.125 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:44.126 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:44.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:44.128 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:44.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:44.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:44.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:41:44.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:44.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:44.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:44.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:41:44.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:41:44.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 01:41:44.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:41:44.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:41:44.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:44.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:41:44.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:44.550 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:44.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:44.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:44.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:44.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:45.023 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:45.496 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:45.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:45.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:45.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:45.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:45.969 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:46.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:41:46.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:41:46.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:46.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:46.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:46.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:46.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:46.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:46.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:46.246 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:46.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:46.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:46.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:46.246 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=572 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.246 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=572 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.246 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=572 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:46.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=573 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:41:51.251 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:51.251 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:51.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:51.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:51.251 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:51.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:51.256 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:51.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:51.257 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:51.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:51.257 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:51.259 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:51.260 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:51.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:51.260 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:51.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:51.261 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:51.261 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:51.261 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:51.263 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:51.263 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:51.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:51.263 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:51.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:51.264 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:51.264 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:51.264 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:51.265 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:51.265 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:51.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:51.265 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:51.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:51.266 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:51.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:51.266 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:51.269 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:41:51.269 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:41:51.269 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:51.269 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:51.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:51.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:51.270 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:51.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.277 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:41:56.277 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:41:56.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:56.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:56.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:56.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:56.282 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:41:56.283 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:56.283 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:56.284 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:41:56.284 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:41:56.287 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:41:56.287 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:41:56.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:56.288 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:56.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:41:56.288 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:41:56.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:41:56.289 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:41:56.290 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:41:56.290 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:41:56.290 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:56.290 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:56.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:41:56.291 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:41:56.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:41:56.291 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:41:56.293 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:41:56.293 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:41:56.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:56.293 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:41:56.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:41:56.293 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:41:56.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:41:56.293 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:41:56.296 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:41:56.296 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:41:56.296 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:41:56.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:41:56.301 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:41:56.779 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:41:56.822 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:41:56.824 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:41:56.826 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:41:56.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:41:57.251 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:41:57.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:57.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:57.299 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:57.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:57.722 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:41:58.191 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:41:58.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:58.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:58.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:58.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:58.655 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:41:59.125 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:41:59.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:41:59.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:41:59.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:41:59.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:41:59.593 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:42:00.059 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:42:00.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:00.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:00.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:00.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:00.533 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:42:01.004 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:42:01.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:01.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:01.473 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:42:01.945 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:42:02.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:02.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:02.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:02.335 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:07.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:07.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:07.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:07.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:07.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:07.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:07.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:07.351 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:07.351 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:07.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:07.352 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:07.356 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:07.356 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:07.356 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:07.357 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:07.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:07.358 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:07.358 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:07.358 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:07.361 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:07.361 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:07.362 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:07.362 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:07.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:07.363 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:07.363 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:07.363 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:07.366 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:07.366 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:07.366 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:07.366 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:07.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:07.367 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:07.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:07.367 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:07.371 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:07.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:07.371 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:07.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:07.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:07.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:07.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:42:07.372 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:42:07.372 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:07.372 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:07.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:07.377 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:07.854 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:07.899 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:07.902 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:07.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:07.904 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:08.321 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:08.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:08.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:08.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:08.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:08.792 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:09.267 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:42:09.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:09.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:09.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:09.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:09.739 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:42:10.214 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:42:10.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:10.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:10.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:10.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:10.686 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:42:11.162 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:42:11.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:11.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:11.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:11.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:11.634 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:42:12.099 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:42:12.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:12.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:12.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:12.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:12.571 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:42:12.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:12.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:12.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:12.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:12.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:12.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:12.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:12.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:12.919 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:12.919 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:12.919 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:12.919 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1199 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:12.920 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1199 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:12.920 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1199 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:12.920 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1199 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:12.920 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1199 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:12.920 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1199 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:17.926 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:17.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:17.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:17.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:17.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:17.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:17.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:17.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:17.934 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:17.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:17.934 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:17.938 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:17.938 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:17.938 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:17.938 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:17.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:17.939 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:17.939 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:17.939 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:17.942 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:17.942 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:17.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:17.942 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:17.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:17.943 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:17.943 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:17.943 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:17.945 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:17.945 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:17.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:17.946 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:17.946 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:17.946 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:17.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:17.946 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.950 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:42:17.950 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:42:17.950 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:17.951 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:17.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:17.953 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:17.953 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:17.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.959 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:22.959 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:22.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:22.959 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:22.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:22.959 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:22.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:22.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:22.969 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:22.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:22.970 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:22.973 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:22.973 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:22.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:22.974 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:22.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:22.974 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:22.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:22.975 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:22.976 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:22.976 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:22.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:22.977 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:22.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:22.977 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:22.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:22.977 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:22.979 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:22.979 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:22.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:22.979 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:22.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:22.979 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:22.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:22.979 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.982 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:42:22.982 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:42:22.982 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:22.982 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:22.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:22.987 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:23.460 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:23.512 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:23.514 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:23.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:23.516 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:23.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:23.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:42:23.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:42:23.932 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:23.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:23.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:23.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:23.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:24.406 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:24.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:24.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:24.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:24.523 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:42:24.523 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:42:24.878 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:42:24.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:24.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:24.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:24.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:25.350 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:42:25.822 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:42:25.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:25.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:25.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:25.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:26.292 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:42:26.763 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:42:26.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:26.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:26.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:26.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:27.233 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:42:27.704 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:42:27.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:27.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:27.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:27.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:28.175 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:42:28.645 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:42:29.117 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:42:29.588 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:42:30.057 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:42:30.529 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:42:31.000 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:42:31.470 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:42:31.941 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:42:32.412 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:42:32.883 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:42:33.352 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:42:33.825 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:42:34.298 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:42:34.770 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:42:35.242 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:42:35.713 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:42:36.187 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:42:36.659 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:42:37.131 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:42:37.602 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:42:38.075 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:42:38.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:38.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:42:38.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:38.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:38.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:38.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:38.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:38.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:38.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:38.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:38.281 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:38.281 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:38.281 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:38.281 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:38.281 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:38.281 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:38.281 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:38.281 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:38.281 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:43.284 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:43.284 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:43.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:43.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:43.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:43.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:43.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:43.298 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:43.298 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:43.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:43.299 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:43.301 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:43.301 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:43.301 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:43.301 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:43.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:43.302 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:43.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:43.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:43.303 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:43.303 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:43.303 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:43.303 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:43.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:43.303 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:43.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:43.304 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:43.305 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:43.305 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:43.305 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:43.305 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:43.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:43.305 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:43.305 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:43.305 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:42:43.307 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:42:43.307 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:43.307 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:43.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:43.312 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:43.790 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:43.830 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:43.832 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:43.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:43.834 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:43.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:43.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:42:43.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:42:43.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:43.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:43.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:43.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:42:43.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:42:43.882 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:43.886 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:43.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:43.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:43.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:43.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:43.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:44.262 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:44.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:44.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:44.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:44.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:44.733 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:44.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:44.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:42:44.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:44.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:44.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:44.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:44.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:44.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:44.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:44.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:44.761 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:44.761 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:44.761 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:44.761 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:44.761 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:44.761 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:44.761 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:44.761 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:44.761 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:42:49.764 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:49.764 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:49.764 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:49.764 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:49.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:49.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:49.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:49.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:49.776 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:49.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:49.776 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:49.779 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:49.779 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:49.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:49.779 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:49.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:49.779 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:49.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:49.780 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:49.782 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:49.782 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:49.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:49.782 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:49.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:49.783 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:49.783 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:49.783 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:49.786 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:49.786 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:49.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:49.786 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:49.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:49.787 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:49.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:49.787 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.792 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:42:49.792 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:42:49.792 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:49.793 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:49.797 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:50.276 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:50.321 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:50.322 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:50.323 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:50.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:50.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:50.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:42:50.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:42:50.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:50.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:50.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:50.347 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:42:50.347 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:42:50.368 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:50.372 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:50.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:50.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:50.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:50.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:50.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:50.748 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:50.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:50.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:50.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:50.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:51.219 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:51.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:51.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:42:51.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:51.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:51.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:51.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:51.248 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:51.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:51.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:51.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:51.248 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:51.248 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:51.248 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:42:56.252 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:42:56.252 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:42:56.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:56.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:56.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:56.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:56.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:42:56.262 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:56.262 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:56.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:42:56.263 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:42:56.268 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:42:56.268 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:42:56.268 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:56.268 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:56.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:42:56.269 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:42:56.269 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:42:56.269 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:42:56.272 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:42:56.273 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:42:56.273 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:56.273 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:56.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:42:56.273 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:42:56.273 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:42:56.273 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:42:56.276 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:42:56.276 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:42:56.276 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:56.276 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:42:56.276 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:42:56.277 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:42:56.277 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:42:56.277 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:42:56.280 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:42:56.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:42:56.280 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:42:56.281 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:42:56.281 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:42:56.281 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:42:56.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:42:56.286 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:42:56.764 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:42:56.809 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:56.810 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:56.811 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:42:56.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:56.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:42:56.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:42:56.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:42:56.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:56.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:56.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:56.836 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:42:56.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:42:56.857 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:42:56.861 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:42:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:42:56.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:42:56.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:42:56.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:56.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:42:57.237 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:42:57.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:57.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:57.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:57.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:57.708 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:42:58.181 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:42:58.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:58.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:58.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:58.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:58.654 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:42:59.126 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:42:59.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:42:59.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:42:59.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:42:59.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:42:59.597 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:43:00.068 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:43:00.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:00.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:00.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:00.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:00.541 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:43:01.014 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:43:01.288 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:01.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:01.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:01.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:01.486 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:43:01.957 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:43:02.430 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:43:02.903 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:43:03.375 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:43:03.846 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:43:04.319 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:43:04.792 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:43:04.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:04.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:04.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:04.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:04.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:04.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:04.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:43:04.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:04.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:04.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:04.888 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:43:04.888 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:43:04.930 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:04.934 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:04.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:04.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:04.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:04.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:04.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:05.264 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:43:05.736 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:43:06.209 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:43:06.681 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:43:07.153 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:43:07.624 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:43:08.098 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:43:08.571 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:43:09.043 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:43:09.514 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:43:09.987 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:43:10.460 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:43:10.932 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:43:11.406 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:43:11.879 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:43:12.351 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:43:12.822 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:43:12.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:12.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:12.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:12.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:12.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:12.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:12.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:12.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:12.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:12.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:12.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:12.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:12.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:12.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:43:12.967 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:43:12.967 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:12.968 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:12.968 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:12.968 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:12.968 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:12.968 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:17.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:17.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:43:17.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:17.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:17.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:17.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:17.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:17.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:17.979 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:17.980 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:17.980 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:43:17.989 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:43:17.990 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:43:17.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:17.991 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:17.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:17.992 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:43:17.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:17.992 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:43:17.999 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:43:18.000 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:43:18.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:18.000 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:18.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:18.001 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:43:18.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:18.001 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:43:18.005 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:43:18.006 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:43:18.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:18.006 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:18.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:18.007 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:43:18.007 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:18.007 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:43:18.013 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:43:18.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:43:18.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:43:18.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:43:18.013 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:43:18.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:43:18.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:43:18.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:43:18.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:43:18.014 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:43:18.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.015 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:43:18.015 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:43:18.015 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:43:18.016 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:18.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:18.020 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:43:18.499 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:43:18.542 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:18.544 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:18.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:18.546 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:43:18.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:18.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:18.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:43:18.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:18.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:18.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:18.578 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:43:18.578 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:43:18.591 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:18.594 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:18.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:18.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:18.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:18.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:18.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:18.971 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:43:19.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:19.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:19.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:19.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:19.442 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:43:19.913 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:43:20.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:20.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:20.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:20.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:20.384 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:43:20.857 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:43:21.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:21.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:21.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:21.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:21.329 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:43:21.802 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:43:22.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:22.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:22.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:22.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:22.275 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:43:22.748 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:43:23.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:23.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:23.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:23.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:23.220 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:43:23.691 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:43:24.164 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:43:24.637 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:43:25.109 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:43:25.580 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:43:26.051 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:43:26.524 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:43:26.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:26.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:26.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:26.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:26.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:26.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:26.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:43:26.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:26.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:26.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:26.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:43:26.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:43:26.658 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:26.663 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:26.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:26.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:26.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:26.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:26.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:26.997 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:43:27.469 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:43:27.942 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:43:28.415 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:43:28.887 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:43:29.358 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:43:29.828 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:43:30.299 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:43:30.773 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:43:31.245 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:43:31.718 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:43:32.191 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:43:32.664 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:43:33.135 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:43:33.607 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:43:34.080 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:43:34.553 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:43:34.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:34.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:34.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:34.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:34.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:34.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:34.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:34.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:34.693 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:34.694 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:34.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:34.694 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:34.694 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:34.694 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:43:34.694 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:43:34.694 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3602 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:34.695 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3602 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:34.695 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3602 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:34.695 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3602 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:34.695 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3602 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:34.695 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3602 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:43:39.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:39.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:43:39.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:39.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:39.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:39.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:39.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:39.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:39.705 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:39.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:43:39.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:43:39.710 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:43:39.710 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:43:39.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:39.711 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:39.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:39.711 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:43:39.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:43:39.712 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:43:39.714 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:43:39.714 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:43:39.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:39.714 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:39.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:39.715 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:43:39.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:43:39.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:43:39.717 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:43:39.717 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:43:39.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:39.717 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:43:39.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:39.718 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:43:39.718 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:43:39.718 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.721 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:43:39.721 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:43:39.721 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:43:39.721 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:43:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:43:39.726 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:43:40.204 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:43:40.245 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:40.247 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:40.249 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:43:40.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:40.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:40.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:40.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:43:40.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:40.276 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:40.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:40.277 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:43:40.277 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:43:40.296 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:40.300 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:40.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:40.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:40.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:40.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:40.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:40.676 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:43:40.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:40.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:40.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:40.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:41.147 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:43:41.620 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:43:41.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:41.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:41.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:41.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:42.093 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:43:42.565 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:43:42.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:42.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:42.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:42.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:43.036 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:43:43.509 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:43:43.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:43.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:43.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:43.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:43.982 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:43:44.454 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:43:44.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:44.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:44.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:44.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:44.925 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:43:45.399 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:43:45.871 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:43:46.343 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:43:46.817 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:43:47.289 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:43:47.761 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:43:48.232 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:43:48.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:48.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:48.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:48.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:48.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:48.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:48.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:43:48.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:48.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:48.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:48.334 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:43:48.334 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:43:48.369 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:43:48.374 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:43:48.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:48.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:43:48.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:43:48.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:48.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:48.705 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:43:49.178 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:43:49.650 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:43:50.121 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:43:50.594 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:43:51.067 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:43:51.539 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:43:52.012 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:43:52.485 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:43:52.957 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:43:53.428 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:43:53.902 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:43:54.374 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:43:54.846 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:43:55.320 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:43:55.792 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:43:56.264 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:43:56.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:43:56.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:43:56.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:43:56.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:43:56.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:43:56.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:43:56.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:43:56.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:43:56.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:43:56.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:43:56.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:43:56.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:43:56.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:43:56.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:43:56.404 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:44:01.408 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:01.408 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:44:01.409 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:01.409 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:01.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:01.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:01.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:01.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:01.416 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:01.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:01.417 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:44:01.420 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:44:01.421 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:44:01.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:01.421 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:01.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:01.421 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:44:01.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:01.421 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:44:01.424 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:44:01.424 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:44:01.424 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:01.424 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:01.424 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:01.424 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:44:01.425 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:01.425 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:44:01.427 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:44:01.427 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:44:01.427 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:01.427 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:01.427 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:01.427 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:44:01.427 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:01.427 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:44:01.429 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:44:01.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:44:01.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:44:01.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:44:01.429 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:44:01.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:44:01.430 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:44:01.430 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:01.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:01.435 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:44:01.913 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:44:01.952 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:01.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:01.954 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:01.957 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:44:01.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:01.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:01.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:44:01.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:01.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:01.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:01.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:44:01.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:44:02.005 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:02.008 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:02.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:02.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:02.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:02.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:02.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:02.384 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:44:02.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:02.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:02.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:02.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:02.856 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:44:03.330 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:44:03.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:03.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:03.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:03.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:03.802 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:44:04.275 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:44:04.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:04.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:04.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:04.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:04.747 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:44:05.221 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:44:05.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:05.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:05.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:05.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:05.693 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:44:06.164 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:44:06.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:06.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:06.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:06.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:06.634 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:44:07.105 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:44:07.578 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:44:08.051 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:44:08.523 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:44:08.994 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:44:09.468 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:44:09.940 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:44:10.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:10.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:10.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:10.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:10.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:10.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:10.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:44:10.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:10.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:10.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:10.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:44:10.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:44:10.079 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:10.083 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:10.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:10.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:10.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:10.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:10.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:10.412 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:44:10.884 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:44:11.352 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:44:11.821 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:44:12.294 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:44:12.767 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:44:13.239 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:44:13.712 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:44:14.185 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:44:14.657 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:44:15.128 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:44:15.599 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:44:16.073 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:44:16.545 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:44:17.017 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:44:17.488 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:44:17.959 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:44:18.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:18.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:18.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:18.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:18.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:18.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:18.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:44:18.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:18.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:18.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:18.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:44:18.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:44:18.141 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:18.143 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:18.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:18.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:18.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:18.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:18.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:18.432 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:44:18.905 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:44:19.378 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:44:19.851 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:44:20.324 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:44:20.796 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:44:21.267 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:44:21.741 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:44:22.214 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:44:22.686 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:44:23.157 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:44:23.628 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:44:24.099 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:44:24.569 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:44:25.040 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:44:25.511 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:44:25.981 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:44:26.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:26.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:26.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:26.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:26.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:26.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:44:26.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:26.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:26.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:44:26.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:44:26.215 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:26.218 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:26.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:26.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:26.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:26.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:26.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:26.452 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:44:26.920 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:44:27.389 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:44:27.860 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:44:28.333 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:44:28.806 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:44:29.279 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:44:29.752 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:44:30.224 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:44:30.697 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:44:31.170 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:44:31.643 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:44:32.115 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:44:32.588 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:44:33.061 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:44:33.534 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:44:34.005 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:44:34.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:34.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:34.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:34.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:34.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:34.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:34.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:34.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:34.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:34.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:34.255 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:34.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:44:34.255 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:44:34.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:34.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:34.255 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:34.255 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:34.255 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:34.255 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:34.255 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:34.255 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:39.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:39.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:44:39.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:39.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:39.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:39.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:39.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:39.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:39.268 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.269 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:44:39.269 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:44:39.272 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:44:39.272 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:44:39.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:39.273 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:39.274 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:44:39.274 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:44:39.276 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:44:39.276 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:44:39.276 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:39.276 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:39.277 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:44:39.277 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:44:39.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:44:39.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:44:39.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:39.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:44:39.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:39.279 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:44:39.279 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:44:39.282 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:44:39.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:44:39.283 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:44:39.283 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.283 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:44:39.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:44:39.288 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:44:39.767 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:44:39.816 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:39.819 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:39.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:39.821 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:44:39.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:39.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:39.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:44:39.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:39.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:39.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:39.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:44:39.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:44:39.905 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:39.909 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:39.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:39.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:39.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:39.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:39.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:40.239 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:44:40.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:40.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:40.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:40.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:40.710 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:44:41.181 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:44:41.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:41.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:41.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:41.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:41.652 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:44:42.125 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:44:42.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:42.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:42.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:42.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:42.597 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:44:43.070 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:44:43.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:43.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:43.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:43.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:43.543 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:44:44.015 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:44:44.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:44.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:44.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:44.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:44.488 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:44:44.961 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:44:45.434 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:44:45.906 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:44:46.377 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:44:46.848 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:44:47.319 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:44:47.792 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:44:47.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:47.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:47.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:47.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:47.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:47.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:47.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:44:47.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:47.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:47.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:47.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:44:47.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:44:47.973 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:44:47.978 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:44:47.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:47.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:44:47.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:44:47.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:47.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:48.265 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:44:48.737 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:44:49.208 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:44:49.681 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:44:50.153 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:44:50.626 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:44:51.096 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:44:51.567 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:44:52.038 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:44:52.509 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:44:52.982 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:44:53.454 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:44:53.927 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:44:54.398 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:44:54.871 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:44:55.344 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:44:55.816 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:44:55.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:44:55.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:44:55.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:44:55.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:44:56.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:44:56.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:44:56.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:44:56.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:44:56.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:44:56.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:44:56.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:44:56.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:44:56.006 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:44:56.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:44:56.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:44:56.006 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3613 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:56.006 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3613 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:56.006 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3613 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:56.006 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3613 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:56.006 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3613 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:44:56.006 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3613 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:01.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:45:01.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:45:01.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:01.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:01.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:01.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:01.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:01.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:45:01.021 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:01.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:45:01.021 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:45:01.027 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:45:01.027 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:45:01.028 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:45:01.028 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:01.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:01.029 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:45:01.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:45:01.030 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:45:01.032 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:45:01.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:45:01.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:45:01.033 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:01.034 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:01.034 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:45:01.034 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:45:01.035 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:45:01.037 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:45:01.037 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:45:01.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:45:01.037 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:01.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:01.038 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:45:01.038 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:45:01.038 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:45:01.042 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:45:01.042 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:01.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:01.047 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:45:01.524 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:45:01.566 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:01.567 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:01.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:01.569 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:45:01.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:01.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:01.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:45:01.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:01.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:01.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:01.594 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:45:01.594 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:45:01.616 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:01.620 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:01.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:01.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:01.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:01.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:01.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:01.995 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:45:02.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:02.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:02.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:02.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:02.467 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:45:02.940 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:45:03.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:03.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:03.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:03.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:03.411 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:45:03.884 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:45:04.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:04.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:04.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:04.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:04.356 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:45:04.828 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:45:05.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:05.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:05.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:05.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:05.299 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:45:05.772 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:45:06.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:06.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:06.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:06.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:06.245 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:45:06.717 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:45:07.188 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:45:07.661 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:45:08.134 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:45:08.606 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:45:09.080 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:45:09.552 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:45:09.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:09.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:09.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:09.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:09.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:09.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:09.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:45:09.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:09.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:09.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:09.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:45:09.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:45:09.690 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:09.692 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:09.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:09.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:09.696 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:09.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:09.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:10.024 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:45:10.495 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:45:10.968 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:45:11.440 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:45:11.912 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:45:12.383 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:45:12.857 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:45:13.329 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:45:13.801 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:45:14.272 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:45:14.746 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:45:15.218 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:45:15.690 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:45:16.161 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:45:16.635 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:45:17.107 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:45:17.579 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:45:17.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:17.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:17.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:17.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:17.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:17.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:17.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:45:17.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:17.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:17.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:17.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:45:17.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:45:17.713 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:17.713 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:17.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:17.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:17.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:17.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:17.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:18.050 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:45:18.521 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:45:18.994 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:45:19.467 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:45:19.939 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:45:20.410 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:45:20.881 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:45:21.354 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:45:21.827 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:45:22.299 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:45:22.770 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:45:23.243 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:45:23.716 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:45:24.188 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:45:24.661 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:45:25.134 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:45:25.606 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:45:25.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:25.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:25.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:25.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:25.722 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=5331 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:45:25.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:25.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:25.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:45:25.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:25.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:25.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:25.733 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:45:25.733 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:45:25.740 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:25.741 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:25.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:25.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:25.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:25.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:25.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:26.076 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:45:26.547 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:45:27.021 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:45:27.493 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:45:27.965 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:45:28.437 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:45:28.910 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:45:29.382 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:45:29.854 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:45:30.325 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:45:30.796 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:45:31.270 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:45:31.742 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:45:32.214 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:45:32.685 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:45:33.159 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:45:33.631 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:45:33.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:33.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:33.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:33.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:45:33.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:45:33.758 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:45:33.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:33.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:38.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:45:38.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:45:38.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:38.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:38.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:38.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:38.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:45:38.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:45:38.774 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:38.774 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:45:38.774 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:45:38.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:45:38.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:45:38.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:45:38.777 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:38.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:45:38.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:45:38.778 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:45:38.778 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:45:38.779 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:45:38.779 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:45:38.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:45:38.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:38.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:45:38.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:45:38.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:45:38.779 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:45:38.781 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:45:38.781 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:45:38.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:45:38.781 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:45:38.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:45:38.781 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:45:38.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:45:38.782 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:45:38.784 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:45:38.784 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:45:38.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.784 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:45:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:45:38.789 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:45:39.267 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:45:39.306 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:39.307 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:39.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:39.308 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:45:39.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:39.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:39.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:45:39.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:39.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:39.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:39.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:45:39.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:45:39.359 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:39.363 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:39.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:39.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:39.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:39.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:39.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:39.739 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:45:39.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:39.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:39.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:39.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:40.210 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:45:40.683 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:45:40.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:40.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:40.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:40.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:41.156 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:45:41.628 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:45:41.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:41.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:41.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:41.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:42.099 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:45:42.572 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:45:42.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:42.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:42.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:42.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:43.045 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:45:43.517 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:45:43.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:45:43.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:45:43.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:45:43.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:45:43.988 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:45:44.461 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:45:44.934 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:45:45.406 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:45:45.877 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:45:46.350 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:45:46.822 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:45:47.294 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:45:47.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:47.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:47.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:47.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:47.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:47.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:47.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:45:47.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:47.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:47.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:47.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:45:47.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:45:47.431 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:47.435 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:47.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:47.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:47.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:47.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:47.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:47.765 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:45:48.239 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:45:48.711 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:45:49.183 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:45:49.654 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:45:50.128 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:45:50.600 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:45:51.072 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:45:51.543 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:45:52.016 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:45:52.488 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:45:52.960 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:45:53.431 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:45:53.905 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:45:54.377 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:45:54.849 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:45:55.323 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:45:55.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:55.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:55.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:55.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:55.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:45:55.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:45:55.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:45:55.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:55.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:55.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:55.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:45:55.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:45:55.503 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:45:55.506 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:45:55.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:45:55.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:45:55.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:45:55.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:55.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:45:55.794 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:45:56.266 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:45:56.738 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:45:57.209 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:45:57.683 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:45:58.155 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:45:58.627 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:45:59.098 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:45:59.569 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:46:00.042 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:46:00.514 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:46:00.986 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:46:01.458 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:46:01.931 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:46:02.403 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:46:02.875 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:46:03.348 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:46:03.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:03.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:03.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:03.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:03.526 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=5345 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:03.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:03.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:03.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:46:03.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:03.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:03.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:03.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:46:03.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:46:03.579 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:03.581 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:03.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:03.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:03.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:03.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:03.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:03.820 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:46:04.292 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:46:04.763 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:46:05.236 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:46:05.708 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:46:06.180 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:46:06.651 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:46:07.124 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:46:07.597 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:46:08.069 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:46:08.540 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:46:09.013 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:46:09.486 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:46:09.958 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:46:10.428 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:46:10.899 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:46:11.373 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:46:11.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:11.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:11.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:11.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:11.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:11.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:11.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:46:11.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:11.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:11.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:11.617 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:46:11.617 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:46:11.650 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:11.653 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:11.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:11.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:11.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:11.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:11.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:11.843 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:46:12.316 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:46:12.788 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:46:13.259 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:46:13.732 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:46:14.205 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:46:14.676 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:46:15.148 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:46:15.621 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:46:16.093 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:46:16.565 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:46:17.036 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:46:17.510 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:46:17.982 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:46:18.454 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:46:18.925 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:46:19.399 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:46:19.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:19.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:19.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:19.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:19.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:19.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:19.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:46:19.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:19.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:19.690 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:19.690 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:46:19.690 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:46:19.721 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:19.725 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:19.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:19.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:19.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:19.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:19.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:19.871 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:46:20.343 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:46:20.816 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:46:21.289 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:46:21.760 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:46:22.232 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:46:22.705 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:46:23.177 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:46:23.649 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:46:24.121 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:46:24.594 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:46:25.066 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:46:25.538 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:46:26.009 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:46:26.483 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:46:26.955 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:46:27.426 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:46:27.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:27.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:27.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:27.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:27.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:27.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:27.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:46:27.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:27.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:27.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:27.761 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:46:27.761 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:46:27.800 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:27.805 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:27.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:27.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:27.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:27.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:27.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:27.897 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:46:28.369 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:46:28.840 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:46:29.313 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:46:29.785 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:46:30.257 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:46:30.728 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:46:31.199 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:46:31.670 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:46:32.140 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:46:32.611 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:46:33.084 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:46:33.557 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:46:34.028 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:46:34.500 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:46:34.973 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:46:35.446 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:46:35.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:35.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:35.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:35.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:35.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:35.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:35.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:46:35.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:35.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:35.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:35.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:46:35.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:46:35.865 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:35.869 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:35.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:35.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:35.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:35.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:35.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:35.917 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:46:36.388 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:46:36.859 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:46:37.333 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:46:37.805 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:46:38.277 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:46:38.748 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:46:39.222 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:46:39.693 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:46:40.165 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:46:40.636 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:46:41.109 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:46:41.582 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 01:46:42.054 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 01:46:42.525 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 01:46:42.999 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 01:46:43.471 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 01:46:43.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:43.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:43.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:43.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:43.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:43.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:43.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:43.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:43.905 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:43.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:43.905 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:43.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:43.905 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:46:43.905 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:46:43.905 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:46:43.906 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=14070 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:43.906 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=14070 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:43.906 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=14070 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:43.906 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=14070 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:43.906 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=14070 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:43.906 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=14070 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:43.906 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=14070 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:46:48.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:46:48.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:46:48.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:48.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:48.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:48.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:48.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:46:48.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:46:48.912 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:48.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:46:48.912 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:46:48.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:46:48.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:46:48.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:46:48.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:48.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:46:48.915 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:46:48.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:46:48.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:46:48.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:46:48.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:46:48.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:46:48.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:48.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:46:48.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:46:48.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:46:48.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:46:48.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:46:48.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:46:48.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:46:48.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:46:48.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:46:48.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:46:48.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:46:48.920 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:46:48.923 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:46:48.923 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:46:48.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:46:48.928 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:46:49.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:46:49.450 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:49.453 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:49.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:49.455 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:46:49.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:49.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:49.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:46:49.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:49.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:49.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:49.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:46:49.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:46:49.496 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:49.498 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:49.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:49.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:49.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:49.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:49.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:49.877 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:46:49.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:49.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:49.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:49.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:50.348 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:46:50.819 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:46:50.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:50.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:50.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:50.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:51.290 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:46:51.761 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:46:51.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:51.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:51.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:51.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:52.232 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:46:52.705 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:46:52.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:52.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:52.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:52.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:53.177 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:46:53.650 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:46:53.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:46:53.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:46:53.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:46:53.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:46:54.120 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:46:54.594 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:46:55.066 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:46:55.538 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:46:56.009 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:46:56.480 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:46:56.953 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:46:57.426 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:46:57.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:57.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:57.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:57.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:57.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:46:57.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:46:57.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:46:57.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:57.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:57.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:57.530 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:46:57.530 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:46:57.564 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:46:57.569 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:46:57.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:46:57.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:46:57.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:46:57.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:57.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:46:57.898 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:46:58.369 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:46:58.841 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:46:59.314 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:46:59.787 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:47:00.257 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:47:00.728 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:47:01.201 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:47:01.674 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:47:02.146 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:47:02.617 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:47:03.090 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:47:03.563 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:47:04.035 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:47:04.508 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:47:04.981 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:47:05.452 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:47:05.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:05.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:05.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:05.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:05.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:05.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:05.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:05.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:05.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:05.595 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:05.595 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:05.595 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:05.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:05.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:05.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:05.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:05.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:05.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:05.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:05.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:05.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3603 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:10.601 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:10.601 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:10.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:10.601 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:10.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:10.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:10.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:10.607 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:10.607 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:10.608 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:10.608 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:10.612 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:10.612 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:10.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:10.612 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:10.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:10.613 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:10.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:10.613 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:10.616 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:10.617 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:10.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:10.617 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:10.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:10.617 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:10.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:10.617 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:10.620 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:10.620 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:10.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:10.620 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:10.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:10.620 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:10.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:10.621 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.624 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:47:10.624 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:47:10.624 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:10.625 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:10.629 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:11.107 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:11.153 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:11.156 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:11.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:11.159 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:11.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:11.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:11.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:47:11.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:11.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:11.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:11.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:47:11.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:47:11.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:11.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:11.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:11.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:11.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:11.580 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:47:11.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:11.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:11.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:11.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:12.050 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:47:12.521 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:47:12.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:12.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:12.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:12.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:12.995 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:47:13.467 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:47:13.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:13.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:13.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:13.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:13.940 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:47:14.410 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:47:14.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:14.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:14.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:14.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:14.881 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:47:15.354 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:47:15.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:15.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:15.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:15.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:15.827 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:47:16.300 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:47:16.770 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:47:17.244 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:47:17.716 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:47:18.189 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:47:18.662 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:47:19.135 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:47:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:19.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:19.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:19.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:19.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:19.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:19.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:19.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:19.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:19.238 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:19.238 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:19.238 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:19.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:19.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:19.239 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:19.239 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:19.239 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:19.239 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:19.239 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:19.239 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:19.239 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:24.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:24.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:24.242 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:24.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:24.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:24.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:24.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:24.251 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:24.251 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:24.252 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:24.252 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:24.255 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:24.255 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:24.255 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:24.255 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:24.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:24.256 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:24.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:24.256 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:24.258 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:24.258 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:24.258 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:24.258 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:24.258 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:24.258 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:24.258 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:24.258 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:24.260 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:24.260 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:24.260 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:24.260 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:24.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:24.260 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:24.261 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:24.261 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.263 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:47:24.263 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:47:24.263 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:24.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:24.268 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:24.746 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:24.791 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:24.793 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:24.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:24.796 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:24.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:24.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:24.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:47:24.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:24.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:24.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:24.818 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:47:24.818 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:47:24.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:24.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:24.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:24.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:24.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:25.218 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:47:25.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:25.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:25.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:25.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:25.689 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:47:26.160 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:47:26.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:26.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:26.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:26.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:26.631 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:47:27.104 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:47:27.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:27.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:27.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:27.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:27.577 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:47:28.049 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:47:28.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:28.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:28.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:28.271 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:28.520 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:47:28.994 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:47:29.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:29.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:29.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:29.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:29.466 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:47:29.938 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:47:30.409 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:47:30.883 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:47:31.355 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:47:31.827 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:47:32.300 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:47:32.773 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:47:32.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:32.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:32.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:32.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:32.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:32.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:32.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:32.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:32.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:32.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:32.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:32.878 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:32.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:32.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:32.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:32.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:32.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:32.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:32.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:32.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:32.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:47:37.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:37.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:37.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:37.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:37.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:37.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:37.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:37.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:37.886 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:37.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:37.888 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:37.888 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:37.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:37.888 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:37.889 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:37.889 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:37.891 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:37.891 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:37.891 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:37.891 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:37.891 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.891 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:37.891 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:37.893 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:37.893 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:37.893 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:37.893 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:37.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:37.893 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.893 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:37.893 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:47:37.896 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:47:37.896 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:37.901 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:38.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:38.419 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:38.419 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:38.420 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:38.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:38.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:38.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:38.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:47:38.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:38.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:38.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:38.443 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:47:38.443 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:47:38.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:38.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:38.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:38.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:38.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:38.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:38.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:38.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:38.636 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:38.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:38.636 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:38.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:38.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:43.642 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:43.642 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:43.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:43.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:43.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:43.642 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:43.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:43.653 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:43.653 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:43.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:43.654 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:43.660 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:43.660 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:43.661 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:43.661 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:43.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:43.661 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:43.661 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:43.661 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:43.666 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:43.666 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:43.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:43.666 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:43.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:43.666 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:43.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:43.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:43.670 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:43.670 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:43.671 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:43.671 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:43.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:43.671 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:43.671 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:43.671 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:43.675 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:43.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:47:43.676 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:47:43.676 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:43.676 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:43.681 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:44.160 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:44.205 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:44.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:44.210 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:44.212 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:44.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:44.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:44.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:47:44.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:44.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:44.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:44.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:47:44.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:47:44.631 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:47:44.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:44.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:44.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:44.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:45.103 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:47:45.574 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:47:45.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:45.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:45.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:45.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:46.047 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:47:46.519 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:47:46.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:46.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:46.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:46.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:46.991 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:47:47.462 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:47:47.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:47.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:47.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:47.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:47.936 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:47:48.408 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:47:48.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:48.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:48.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:48.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:48.880 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:47:48.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:48.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:48.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:48.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:47:48.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:48.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:48.910 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:48.910 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:48.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:48.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:49.358 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:47:49.838 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:47:50.318 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:47:50.797 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:47:51.276 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:47:51.756 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:47:52.237 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:47:52.717 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:47:53.195 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:47:53.675 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:47:53.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:53.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:53.913 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:53.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:53.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:53.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:53.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:53.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:53.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:53.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:53.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:53.919 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:53.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:53.919 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:53.920 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:53.920 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:53.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:53.920 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:53.921 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:53.921 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:53.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:53.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:53.922 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:53.922 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:53.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:53.922 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:53.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:53.922 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:53.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:53.922 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:53.923 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:53.923 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:53.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:53.923 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:53.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:53.923 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:53.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:53.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:47:53.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:47:53.925 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:53.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.926 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:53.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:53.927 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:53.927 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:53.927 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:47:53.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:53.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:58.933 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:47:58.933 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:47:58.933 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:58.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:58.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:58.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:58.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:47:58.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:58.946 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:58.946 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:47:58.946 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:47:58.951 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:47:58.952 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:47:58.952 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:58.952 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:58.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:47:58.953 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:47:58.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:47:58.954 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:47:58.957 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:47:58.958 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:47:58.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:58.958 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:58.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:47:58.959 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:47:58.959 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:47:58.959 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:47:58.962 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:47:58.962 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:47:58.962 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:58.963 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:47:58.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:47:58.963 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:47:58.963 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:47:58.963 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.967 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:47:58.967 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:47:58.967 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.967 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:47:58.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:47:58.972 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:47:59.450 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:47:59.495 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:47:59.497 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:47:59.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:47:59.500 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:47:59.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:47:59.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:47:59.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:47:59.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:47:59.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:47:59.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:47:59.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:47:59.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:47:59.922 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:47:59.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:47:59.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:47:59.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:47:59.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:00.394 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:48:00.867 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:48:00.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:00.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:00.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:00.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:01.339 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:48:01.811 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:48:01.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:01.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:01.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:01.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:02.282 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:48:02.756 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:48:02.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:02.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:02.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:02.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:03.228 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:48:03.700 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:48:03.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:03.974 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:03.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:03.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:04.171 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:48:04.645 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:48:05.117 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:48:05.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:05.589 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:48:06.060 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:48:06.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:06.533 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:48:07.005 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:48:07.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:07.477 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:48:07.948 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:48:08.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:08.423 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:48:08.895 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:48:09.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:09.193 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:09.367 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:48:09.841 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:48:10.313 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:48:10.789 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:48:11.256 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:48:11.727 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:48:12.202 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:48:12.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:12.674 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:48:13.145 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:48:13.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:13.616 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:48:14.090 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:48:14.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:14.562 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:48:15.034 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:48:15.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:15.505 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:48:15.979 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:48:16.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:16.451 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:48:16.923 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:48:17.394 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:48:17.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:17.867 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:48:18.340 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:48:18.812 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:48:19.283 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:48:19.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:19.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:19.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:19.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:19.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:19.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:19.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:19.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:19.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:19.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:19.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:19.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:48:19.658 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:48:19.658 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4469 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:19.658 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4469 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:24.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:24.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:48:24.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:24.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:24.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:24.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:24.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:24.671 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:24.671 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:24.672 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:24.672 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:48:24.675 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:48:24.675 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:48:24.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:24.675 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:24.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:24.676 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:48:24.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:24.676 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:48:24.678 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:48:24.678 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:48:24.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:24.679 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:24.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:24.679 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:48:24.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:24.679 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:48:24.681 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:48:24.681 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:48:24.682 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:24.682 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:24.682 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:24.682 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:48:24.682 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:24.682 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:48:24.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.688 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:48:24.688 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:48:24.688 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:48:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.688 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:48:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:24.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:24.693 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:48:25.170 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:48:25.218 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:25.220 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:25.222 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:48:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:25.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:25.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:25.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:48:25.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:25.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:25.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:25.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:48:25.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:48:25.263 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:25.266 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:25.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:25.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:25.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:25.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:25.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:25.643 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:48:25.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:25.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:25.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:25.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:26.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:26.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:26.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:26.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:26.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:26.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:26.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:26.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:26.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:26.090 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:26.090 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:48:26.090 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:48:26.090 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:26.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:26.090 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:26.090 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:26.090 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:26.090 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:26.090 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:26.091 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:26.091 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:48:31.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:31.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:48:31.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:31.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:31.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:31.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:31.103 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:31.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:31.104 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:31.105 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:31.105 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:48:31.109 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:48:31.109 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:48:31.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:31.110 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:31.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:31.111 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:48:31.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:31.111 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:48:31.113 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:48:31.113 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:48:31.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:31.113 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:31.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:31.114 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:48:31.114 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:31.114 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:48:31.116 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:48:31.116 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:48:31.116 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:31.117 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:31.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:31.117 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:48:31.117 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:31.117 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.120 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:48:31.120 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:48:31.120 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:48:31.120 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:31.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:31.125 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:48:31.603 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:48:31.650 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:31.652 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:31.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:31.655 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:48:31.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:31.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:31.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:48:31.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:31.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:31.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:31.676 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:48:31.676 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:48:31.695 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:31.699 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:31.706 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:31.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:31.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:31.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:31.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:32.075 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:48:32.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:32.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:32.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:32.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:32.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 01:48:32.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:32.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:32.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:32.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:32.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:32.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:32.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:32.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:32.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:32.523 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:32.523 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:48:32.523 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:48:32.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:32.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:37.529 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:48:37.529 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:48:37.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:37.529 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:37.529 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:37.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:37.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:48:37.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:37.539 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:37.539 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:48:37.539 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:48:37.542 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:48:37.542 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:48:37.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:37.543 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:37.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:48:37.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:48:37.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:48:37.544 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:48:37.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:48:37.545 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:48:37.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:37.545 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:37.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:48:37.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:48:37.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:48:37.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:48:37.548 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:48:37.548 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:48:37.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:37.548 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:48:37.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:48:37.548 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:48:37.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:48:37.548 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:48:37.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:48:37.551 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:48:37.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:48:37.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:48:38.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:48:38.077 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:48:38.079 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:48:38.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:38.081 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:48:38.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:38.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:38.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:48:38.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:38.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:38.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:38.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:48:38.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:48:38.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:38.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:38.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:38.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:38.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:38.505 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:48:38.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:38.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:38.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:38.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:38.977 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:48:39.451 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:48:39.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:39.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:39.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:39.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:39.923 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:48:40.396 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:48:40.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:40.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:40.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:40.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:40.866 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:48:41.340 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:48:41.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:41.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:41.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:41.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:41.812 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:48:42.284 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:48:42.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:48:42.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:48:42.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:48:42.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:48:42.755 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:48:43.229 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:48:43.702 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:48:44.173 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:48:44.646 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:48:45.119 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:48:45.591 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:48:46.062 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:48:46.536 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:48:47.008 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:48:47.481 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:48:47.952 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:48:48.425 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:48:48.898 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:48:49.370 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:48:49.843 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:48:50.316 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:48:50.788 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:48:51.260 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:48:51.733 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:48:52.206 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:48:52.678 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:48:53.151 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:48:53.624 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:48:53.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:53.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:53.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:53.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:53.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:48:53.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:48:53.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:48:53.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:53.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:53.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:53.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:48:53.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:48:54.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:48:54.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:48:54.007 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:48:54.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:54.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:48:54.096 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:48:54.567 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:48:55.041 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:48:55.513 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:48:55.986 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:48:56.456 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:48:56.927 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:48:57.401 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:48:57.873 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:48:58.346 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:48:58.819 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:48:59.292 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:48:59.764 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:49:00.235 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:49:00.709 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:49:01.181 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:49:01.653 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:49:02.124 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:49:02.598 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:49:03.070 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:49:03.543 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:49:04.016 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:49:04.489 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:49:04.962 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:49:05.435 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:49:05.908 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:49:06.380 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:49:06.854 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:49:07.326 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:49:07.798 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:49:08.269 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:49:08.743 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:49:09.215 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:49:09.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:09.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:09.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:09.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:49:09.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:09.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:49:09.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:49:09.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:09.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:09.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:09.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:49:09.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:49:09.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:09.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:09.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:09.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:09.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:09.688 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:49:10.159 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:49:10.630 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:49:11.103 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:49:11.576 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:49:12.048 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 01:49:12.519 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 01:49:12.992 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 01:49:13.465 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 01:49:13.937 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 01:49:14.411 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 01:49:14.883 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 01:49:15.356 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 01:49:15.829 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 01:49:16.302 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 01:49:16.774 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 01:49:17.248 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 01:49:17.721 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 01:49:18.193 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 01:49:18.664 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 01:49:19.137 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 01:49:19.610 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 01:49:20.082 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 01:49:20.556 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 01:49:21.029 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 01:49:21.501 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 01:49:21.972 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 01:49:22.443 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 01:49:22.916 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 01:49:23.389 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 01:49:23.861 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 01:49:24.335 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 01:49:24.808 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 01:49:24.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:24.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:24.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:24.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:49:24.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:24.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:49:24.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:49:24.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:24.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:24.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:24.907 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:49:24.907 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:49:24.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:24.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:24.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:24.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:24.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:24.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:25.280 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 01:49:25.753 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 01:49:26.226 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 01:49:26.699 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 01:49:27.172 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 01:49:27.644 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 01:49:28.117 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 01:49:28.590 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 01:49:29.062 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 01:49:29.535 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 01:49:30.006 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 01:49:30.479 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 01:49:30.951 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 01:49:31.424 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 01:49:31.897 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 01:49:32.370 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 01:49:32.842 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 01:49:33.313 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 01:49:33.787 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 01:49:34.259 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 01:49:34.731 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 01:49:35.205 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 01:49:35.678 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 01:49:36.149 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 01:49:36.622 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 01:49:37.094 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 01:49:37.566 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 01:49:38.038 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 01:49:38.511 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 01:49:38.983 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 01:49:39.456 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 01:49:39.929 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 01:49:40.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:40.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:40.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:40.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:49:40.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:40.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:40.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:40.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:40.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:40.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:40.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:40.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:40.373 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:40.373 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:49:40.373 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:49:40.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:40.375 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:49:45.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:45.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:49:45.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:45.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:45.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:45.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:45.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:45.384 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:45.385 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.385 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:45.385 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:49:45.388 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:49:45.389 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:49:45.389 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:45.389 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:45.390 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.390 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:45.390 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:49:45.392 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:49:45.392 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:49:45.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:45.392 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.393 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:45.393 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.393 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:45.393 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:49:45.395 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:49:45.395 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:49:45.395 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:45.395 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:45.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:45.395 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:45.396 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:49:45.398 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:49:45.399 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:49:45.399 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:49:45.399 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:45.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:49:45.401 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:45.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.410 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:49:50.410 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:49:50.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:50.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:50.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:50.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:50.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:49:50.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:50.421 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:50.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:49:50.422 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:49:50.425 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:49:50.426 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:49:50.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:50.426 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:50.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:49:50.427 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:49:50.428 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:49:50.428 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:49:50.429 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:49:50.430 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:49:50.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:50.430 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:50.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:49:50.430 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:49:50.431 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:49:50.431 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:49:50.432 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:49:50.433 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:49:50.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:50.433 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:49:50.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:49:50.433 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:49:50.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:49:50.433 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.436 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:49:50.436 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:49:50.436 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:49:50.436 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:49:50.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:49:50.441 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:49:50.920 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:49:50.968 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:49:50.970 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:49:50.972 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:49:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:50.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:49:50.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:49:50.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:49:51.006 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:49:51.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:51.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:51.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:51.011 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:49:51.011 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:49:51.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:49:51.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:49:51.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:49:51.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:51.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:49:51.392 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:49:51.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:51.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:51.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:51.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:51.866 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:49:52.339 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:49:52.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:52.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:52.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:52.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:52.811 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:49:53.284 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:49:53.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:53.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:53.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:53.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:53.757 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:49:54.229 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:49:54.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:54.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:54.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:54.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:54.700 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:49:55.173 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:49:55.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:49:55.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:49:55.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:49:55.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:49:55.646 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:49:56.118 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:49:56.592 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:49:57.064 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:49:57.537 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:49:58.008 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:49:58.478 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:49:58.952 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:49:59.425 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:49:59.897 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:50:00.368 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:50:00.839 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:50:01.312 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:50:01.785 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:50:01.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:01.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:01.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:01.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:50:01.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:01.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:01.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:01.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:01.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:01.886 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:01.886 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:01.886 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:50:01.886 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:50:01.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:01.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:06.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:06.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:50:06.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:06.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:06.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:06.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:06.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:06.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:06.902 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:06.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:06.903 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:50:06.905 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:50:06.906 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:50:06.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:06.906 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:06.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:06.907 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:50:06.907 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:06.907 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:50:06.908 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:50:06.908 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:50:06.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:06.909 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:06.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:06.909 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:50:06.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:06.909 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:50:06.910 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:50:06.910 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:50:06.911 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:06.911 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:06.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:06.911 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:50:06.911 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:06.911 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:50:06.913 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:50:06.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:50:06.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:50:06.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:50:06.913 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:50:06.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:50:06.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:50:06.914 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:50:06.914 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:50:06.914 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:06.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:06.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:06.918 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:50:07.397 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:50:07.440 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:50:07.442 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:07.443 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:50:07.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:07.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:07.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:50:07.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:50:07.475 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:07.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:07.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:07.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:07.478 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:50:07.478 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:50:07.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:07.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:07.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:07.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:07.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:07.868 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:50:07.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:07.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:07.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:07.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:08.340 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:50:08.811 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:50:08.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:08.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:08.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:08.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:09.285 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:50:09.757 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:50:09.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:09.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:09.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:09.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:10.229 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:50:10.700 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:50:10.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:10.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:10.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:10.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:11.171 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:50:11.642 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:50:11.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:11.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:11.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:11.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:12.115 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:50:12.588 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:50:13.060 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:50:13.531 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:50:14.005 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:50:14.477 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:50:14.949 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:50:15.420 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:50:15.894 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:50:16.366 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:50:16.839 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:50:17.313 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:50:17.785 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:50:17.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:17.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:17.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:17.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:50:17.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:17.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:17.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:17.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:17.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:17.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:17.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:50:17.897 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:50:17.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:17.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:17.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:17.897 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2372 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:17.897 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2372 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:17.897 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2372 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:17.897 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2372 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:17.897 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2372 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:17.897 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2372 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:50:22.899 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:22.899 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:50:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:22.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:22.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:22.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:22.908 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:22.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:22.908 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:50:22.913 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:50:22.913 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:50:22.914 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:22.914 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:22.914 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:22.914 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:50:22.914 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:22.914 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:50:22.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:50:22.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:50:22.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:22.919 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:22.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:22.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:50:22.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:22.920 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:50:22.924 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:50:22.924 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:50:22.924 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:22.924 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:22.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:22.924 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:50:22.925 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:22.925 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:50:22.930 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:50:22.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:50:22.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:50:22.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:50:22.930 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.931 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:50:22.931 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:50:22.931 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:50:22.932 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:22.936 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:50:23.413 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:50:23.465 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:50:23.467 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:23.469 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:50:23.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:23.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:23.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:50:23.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:50:23.511 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:23.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:23.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:23.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:23.513 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:50:23.513 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:50:23.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:23.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:23.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:23.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:23.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:23.885 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:50:23.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:23.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:23.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:23.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:24.357 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:50:24.828 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:50:24.851 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:24.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:24.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:24.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:24.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:25.301 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:50:25.774 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:50:25.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:25.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:25.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:25.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:26.246 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:50:26.717 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:50:26.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:26.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:26.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:26.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:27.188 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:50:27.661 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:50:27.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:27.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:27.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:27.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:28.134 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:50:28.606 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:50:29.080 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:50:29.552 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:50:30.025 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:50:30.496 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:50:30.969 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:50:31.442 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:50:31.914 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:50:32.388 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:50:32.860 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:50:33.332 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:50:33.803 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:50:34.296 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:50:34.769 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:50:35.242 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:50:35.715 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:50:36.187 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:50:36.661 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:50:37.133 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:50:37.606 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:50:38.079 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:50:38.551 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:50:39.024 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:50:39.495 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:50:39.968 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:50:40.441 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:50:40.913 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:50:41.387 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:50:41.859 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:50:42.332 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:50:42.805 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:50:43.278 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:50:43.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:43.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:43.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:43.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:50:43.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:43.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:43.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:43.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:43.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:43.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:43.593 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:43.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:43.593 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:43.593 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:50:43.593 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:50:48.600 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:50:48.600 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:50:48.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:48.600 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:48.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:48.600 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:48.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:50:48.609 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:48.609 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:48.609 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:50:48.609 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:50:48.612 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:50:48.613 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:50:48.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:48.613 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:48.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:50:48.614 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:50:48.614 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:50:48.614 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:50:48.615 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:50:48.615 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:50:48.615 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:48.615 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:48.616 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:50:48.616 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:50:48.616 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:50:48.616 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:50:48.618 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:50:48.618 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:50:48.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:48.618 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:50:48.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:50:48.618 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:50:48.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:50:48.618 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:50:48.620 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:50:48.621 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:50:48.621 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:50:48.621 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:50:48.622 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:50:48.626 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:50:49.101 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:50:49.147 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:50:49.149 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:49.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:49.151 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:50:49.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:50:49.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:50:49.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:50:49.189 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:50:49.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:49.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:49.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:49.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:50:49.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:50:49.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:50:49.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:50:49.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:50:49.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:49.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:50:49.573 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:50:49.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:49.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:49.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:49.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:50.044 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:50:50.518 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:50:50.539 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:50.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:50.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:50.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:50.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:50.991 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:50:51.463 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:50:51.505 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:51.626 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:51.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:51.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:51.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:51.934 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:50:52.407 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:50:52.465 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:52.628 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:52.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:52.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:52.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:52.880 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:50:53.352 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:50:53.431 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:53.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:50:53.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:50:53.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:50:53.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:50:53.826 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:50:54.298 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:50:54.397 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:54.771 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:50:55.242 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:50:55.357 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:55.715 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:50:56.188 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:50:56.324 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:56.660 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:50:57.131 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:50:57.284 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:57.604 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:50:58.077 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:50:58.250 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:58.549 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:50:59.020 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:50:59.210 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:50:59.494 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:50:59.966 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:51:00.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:00.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:00.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:00.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:00.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:00.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:00.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:00.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:00.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:00.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:00.081 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:00.081 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:00.081 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:00.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:00.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:05.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:05.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:05.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:05.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:05.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:05.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:05.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:05.091 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:05.091 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:05.092 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:05.092 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:05.093 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:05.094 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:05.094 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:05.094 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:05.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:05.095 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:05.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:05.095 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:05.096 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:05.097 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:05.097 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:05.097 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:05.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:05.097 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:05.097 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:05.097 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:05.098 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:05.099 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:05.099 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:05.099 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:05.099 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:05.099 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:05.099 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:05.099 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:05.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:51:05.102 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:51:05.102 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:05.102 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:05.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:05.106 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:05.583 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:05.627 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:05.630 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:05.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:05.632 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:05.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:05.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:05.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:05.670 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:05.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:05.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:05.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:05.673 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:05.673 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:05.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:05.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:05.734 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:05.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:05.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:05.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:06.056 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:06.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:06.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:06.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:06.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:06.529 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:07.002 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:51:07.027 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:51:07.028 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:07.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:07.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:07.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:07.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:07.475 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:51:07.948 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:51:08.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:08.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:08.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:08.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:08.421 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:51:08.893 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:51:09.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:09.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:09.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:09.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:09.364 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:51:09.837 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:51:10.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:10.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:10.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:10.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:10.310 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:51:10.782 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:51:11.253 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:51:11.726 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:51:12.199 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:51:12.671 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:51:12.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:12.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:12.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:12.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:12.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:12.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:12.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:12.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:12.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:12.827 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:12.827 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:12.827 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:12.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:12.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:12.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:12.828 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1668 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:12.828 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1668 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:12.828 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1668 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:12.828 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1668 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:12.828 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1668 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:12.828 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1668 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:12.828 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1668 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:17.832 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:17.832 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:17.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:17.832 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:17.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:17.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:17.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:17.839 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:17.839 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:17.840 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:17.844 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:17.844 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:17.844 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:17.845 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.845 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:17.845 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.845 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:17.845 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:17.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:17.849 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:17.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:17.849 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:17.849 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:17.850 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:17.852 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:17.852 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:17.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:17.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:17.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:17.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:17.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:51:17.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:51:17.857 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:17.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:17.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:17.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:17.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:18.341 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:18.381 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:18.381 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:18.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:18.383 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:18.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:18.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:18.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:18.427 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:18.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:18.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:18.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:18.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:18.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:18.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:18.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:18.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:18.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:18.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:18.812 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:18.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:18.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:18.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:18.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:19.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:19.758 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:51:19.778 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:51:19.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:19.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:19.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:19.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:20.230 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:51:20.702 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:51:20.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:20.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:20.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:20.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:21.176 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:51:21.649 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:51:21.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:21.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:21.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:21.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:22.121 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:51:22.592 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:51:22.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:22.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:22.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:22.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:23.065 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:51:23.538 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:51:24.010 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:51:24.481 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:51:24.954 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:51:25.427 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:51:25.899 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:51:26.373 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:51:26.845 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:51:27.318 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:51:27.788 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:51:28.259 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:51:28.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:28.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:28.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:28.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:28.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:28.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:28.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:28.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:28.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:28.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:28.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:28.513 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:28.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:28.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:28.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:28.513 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2301 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:28.513 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2301 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:28.513 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2301 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:28.513 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2301 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:28.513 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2301 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:28.513 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2301 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:33.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:33.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:33.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:33.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:33.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:33.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:33.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:33.525 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:33.525 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:33.526 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:33.526 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:33.529 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:33.529 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:33.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:33.530 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:33.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:33.531 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:33.531 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:33.531 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:33.533 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:33.533 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:33.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:33.534 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:33.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:33.534 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:33.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:33.534 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:33.536 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:33.536 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:33.536 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:33.536 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:33.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:33.536 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:33.536 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:33.536 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:51:33.540 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:51:33.540 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:33.540 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:33.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:33.544 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:34.022 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:34.062 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:34.064 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:34.066 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:34.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:34.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:34.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:34.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:34.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:34.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:34.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:34.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:34.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:34.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:34.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:34.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.493 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:34.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:34.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:34.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:34.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:34.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:34.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:34.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:34.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:34.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:34.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:34.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:34.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:34.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:34.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:34.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:34.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:34.543 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:34.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:34.965 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:35.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:35.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:35.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:35.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:35.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:35.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:35.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:35.248 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:35.248 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:35.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:35.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:35.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:35.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:35.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:35.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:35.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:35.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:35.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:35.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:35.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:35.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:35.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:35.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:35.435 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:51:35.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:35.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:35.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:35.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:35.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:35.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:35.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:35.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:35.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:35.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:35.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:35.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:35.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:35.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:35.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:35.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:35.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:35.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:35.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:35.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:35.840 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:40.847 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:40.847 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:40.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:40.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:40.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:40.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:40.855 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:40.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:40.855 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:40.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:40.856 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:40.858 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:40.859 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:40.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:40.859 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:40.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:40.860 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:40.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:40.860 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:40.862 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:40.862 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:40.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:40.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:40.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:40.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:40.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:40.863 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:40.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:40.865 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:40.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:40.865 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:40.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:40.865 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:40.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:40.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.868 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:51:40.868 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:51:40.868 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:40.868 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:40.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:40.873 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:41.351 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:41.396 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:41.398 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:41.400 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:41.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:41.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:41.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:41.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:41.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:41.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:41.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:41.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:41.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:41.442 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:41.444 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 01:51:41.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:41.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:41.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:41.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:41.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:41.822 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:41.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:41.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:41.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:41.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:41.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:41.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:41.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:41.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:41.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:41.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:41.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:41.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:41.840 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:51:41.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:41.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:41.840 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=210 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:41.840 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=210 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:41.840 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=210 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:41.840 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:41.840 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:51:46.846 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:51:46.846 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:51:46.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:46.846 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:46.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:46.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:46.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:51:46.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:46.859 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:46.859 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:51:46.859 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:51:46.865 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:51:46.866 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:51:46.866 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:46.866 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:46.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:51:46.867 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:51:46.868 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:51:46.868 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:51:46.871 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:51:46.871 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:51:46.871 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:46.871 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:46.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:51:46.872 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:51:46.872 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:51:46.872 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:51:46.874 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:51:46.874 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:51:46.875 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:46.875 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:51:46.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:51:46.875 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:51:46.875 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:51:46.875 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:51:46.879 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:51:46.879 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:51:46.879 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:51:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:51:46.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:51:46.884 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:51:47.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:51:47.409 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:51:47.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:47.412 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:51:47.416 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:51:47.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:47.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:47.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:47.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:47.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:47.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:47.447 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:47.447 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:47.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:47.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:47.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:47.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:47.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:47.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:47.834 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:51:47.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:47.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:47.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:47.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:48.305 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:51:48.778 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:51:48.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:48.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:48.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:48.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:49.251 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:51:49.723 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:51:49.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:49.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:49.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:49.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:50.196 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:51:50.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:50.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:50.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:50.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:50.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:50.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:50.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:50.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:50.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:50.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:50.594 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:50.594 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:50.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:50.614 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:50.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:50.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:50.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:50.669 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:51:50.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:50.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:50.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:50.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:50.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:51.141 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:51:51.612 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:51:51.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:51:51.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:51:51.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:51:51.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:51:52.086 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:51:52.558 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:51:53.030 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:51:53.501 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:51:53.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:53.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:53.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:53.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:53.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:53.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:53.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:53.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:53.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:53.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:53.787 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:53.787 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:53.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:53.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:53.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:53.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:53.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:53.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:53.974 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:51:54.446 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:51:54.918 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:51:55.389 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:51:55.860 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:51:56.334 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:51:56.806 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:51:56.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:56.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:56.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:56.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:56.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:51:56.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:51:56.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:51:56.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:56.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:56.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:56.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:51:56.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:51:57.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:57.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:51:57.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:51:57.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:57.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:51:57.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:51:57.278 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:51:57.749 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:51:58.222 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:51:58.695 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:51:59.167 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:51:59.640 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:52:00.112 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:52:00.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:00.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:00.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:00.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:52:00.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:00.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:00.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:00.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:00.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:00.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:00.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:00.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:52:00.213 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:52:00.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:00.213 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:05.220 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:05.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:52:05.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:05.220 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:05.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:05.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:05.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:05.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:05.228 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:05.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:05.228 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:52:05.232 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:52:05.232 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:52:05.233 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:05.233 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:05.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:05.234 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:52:05.234 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:05.234 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:52:05.236 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:52:05.237 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:52:05.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:05.237 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:05.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:05.237 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:52:05.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:05.238 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:52:05.240 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:52:05.240 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:52:05.240 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:05.240 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:05.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:05.241 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:52:05.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:05.241 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:52:05.244 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:52:05.244 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:52:05.244 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:05.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:05.249 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:52:05.727 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:52:05.770 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:52:05.772 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:52:05.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:05.774 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:52:05.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:05.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:52:05.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:52:05.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:05.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:05.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:05.780 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:52:05.780 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:52:06.200 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:52:06.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:06.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:06.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:06.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:06.671 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:52:07.141 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:52:07.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:07.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:07.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:07.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:07.612 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:52:08.086 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:52:08.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:08.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:08.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:08.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:08.558 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:52:09.030 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:52:09.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:09.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:09.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:09.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:09.504 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:52:09.976 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:52:10.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:10.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:10.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:10.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:10.448 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:52:10.919 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:52:11.390 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:52:11.863 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:52:12.335 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:52:12.807 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:52:13.278 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:52:13.749 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:52:14.222 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:52:14.695 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:52:15.167 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:52:15.638 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:52:16.111 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:52:16.583 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:52:17.055 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:52:17.526 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:52:17.999 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:52:18.472 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:52:18.943 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:52:19.415 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:52:19.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:19.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:52:19.710 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:19.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:19.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:19.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:19.712 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:19.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:19.712 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:19.712 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:52:19.712 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:52:19.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:19.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:24.715 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:24.715 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:52:24.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:24.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:24.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:24.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:24.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:24.727 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:24.727 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.727 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:24.727 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:52:24.734 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:52:24.734 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:52:24.735 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:24.735 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:24.735 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.735 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:24.736 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:52:24.739 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:52:24.739 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:52:24.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:24.740 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:24.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:24.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:52:24.744 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:52:24.744 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:52:24.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:24.744 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:24.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:24.745 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.745 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:24.745 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:52:24.749 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:52:24.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:52:24.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:52:24.750 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:52:24.750 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:52:24.750 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:24.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:24.755 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:52:25.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:52:25.277 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:52:25.279 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:52:25.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:25.281 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:52:25.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:25.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:52:25.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:52:25.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:25.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:25.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:25.310 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:52:25.310 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:52:25.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:25.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:25.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:25.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:25.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:25.705 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:52:25.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:25.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:25.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:25.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:26.176 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:52:26.647 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:52:26.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:26.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:26.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:26.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:27.120 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:52:27.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:27.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:27.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:52:27.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:52:27.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:27.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:27.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:27.340 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:52:27.340 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:52:27.593 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:52:27.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:27.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:27.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:27.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:28.064 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:52:28.536 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:52:28.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:28.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:28.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:28.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:29.009 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:52:29.481 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:52:29.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:29.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:29.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:29.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:29.953 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:52:30.424 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:52:30.895 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:52:31.365 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:52:31.836 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:52:32.309 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:52:32.782 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:52:33.253 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:52:33.725 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:52:34.198 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:52:34.670 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:52:35.142 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:52:35.613 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:52:36.087 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:52:36.559 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:52:37.031 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:52:37.502 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:52:37.976 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:52:38.448 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:52:38.920 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:52:39.391 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:52:39.862 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:52:40.333 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:52:40.806 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:52:41.278 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:52:41.751 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:52:42.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:42.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:42.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:52:42.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:42.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:42.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:42.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:42.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:42.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:42.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:42.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:42.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:42.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:52:42.049 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:42.049 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3739 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:52:47.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:52:47.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:52:47.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:47.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:47.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:47.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:47.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:52:47.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:47.064 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:47.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:52:47.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:52:47.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:52:47.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:52:47.068 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:47.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:47.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:52:47.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:52:47.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:52:47.070 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:52:47.072 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:52:47.072 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:52:47.072 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:47.072 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:47.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:52:47.073 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:52:47.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:52:47.073 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:52:47.075 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:52:47.075 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:52:47.075 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:47.075 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:52:47.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:52:47.075 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:52:47.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:52:47.076 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.079 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:52:47.079 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:52:47.079 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:52:47.080 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:52:47.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:52:47.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:52:47.084 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:52:47.562 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:52:47.606 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:52:47.609 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:52:47.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:52:47.611 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:52:47.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:52:47.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:52:47.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:52:47.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:52:47.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:52:47.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:52:47.616 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:52:47.616 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:52:48.034 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:52:48.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:48.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:48.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:48.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:48.505 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:52:48.979 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:52:49.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:49.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:49.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:49.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:49.451 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:52:49.923 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:52:50.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:50.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:50.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:50.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:50.394 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:52:50.867 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:52:51.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:51.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:51.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:51.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:51.340 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:52:51.812 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:52:52.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:52:52.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:52:52.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:52:52.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:52:52.286 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:52:52.757 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:52:53.229 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:52:53.700 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:52:54.174 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:52:54.646 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:52:55.118 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:52:55.592 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:52:56.064 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:52:56.536 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:52:57.007 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:52:57.480 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:52:57.953 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:52:58.425 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:52:58.896 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:52:59.369 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:52:59.841 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:53:00.313 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:53:00.784 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:53:01.258 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:53:01.730 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:53:02.202 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:53:02.673 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:53:03.147 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:53:03.619 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:53:04.092 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:53:04.565 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:53:05.037 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:53:05.509 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:53:05.980 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:53:06.454 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:53:06.926 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:53:07.398 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:53:07.869 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:53:08.343 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:53:08.815 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:53:09.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:09.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:53:09.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:09.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:09.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:09.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:09.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:09.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:09.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:09.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:09.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:09.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:53:09.102 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:53:09.102 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4756 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:09.102 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4756 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:09.102 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4756 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:09.102 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4756 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:09.102 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4756 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:09.102 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4756 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:14.107 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:14.107 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:53:14.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:14.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:14.107 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:14.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:14.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:14.115 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:14.116 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:14.116 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:14.116 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:53:14.118 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:53:14.118 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:53:14.119 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:14.119 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:14.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:14.119 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:53:14.120 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:14.120 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:53:14.121 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:53:14.122 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:53:14.122 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:14.122 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:14.122 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:14.122 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:53:14.123 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:14.123 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:53:14.124 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:53:14.124 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:53:14.124 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:14.124 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:14.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:14.125 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:53:14.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:14.125 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:53:14.128 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:53:14.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:53:14.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:53:14.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:53:14.128 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:53:14.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:53:14.129 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:53:14.129 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:53:14.129 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:14.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:14.134 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:53:14.612 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:53:14.658 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:53:14.660 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:53:14.662 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:53:14.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:53:14.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:14.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:53:14.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:53:14.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:53:14.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:53:14.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:53:14.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:53:14.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:53:15.084 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:53:15.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:15.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:15.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:15.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:15.555 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:53:16.028 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:53:16.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:16.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:16.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:16.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:16.501 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:53:16.973 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:53:17.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:17.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:17.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:17.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:17.444 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:53:17.918 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:53:18.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:18.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:18.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:18.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:18.390 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:53:18.861 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:53:19.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:19.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:19.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:19.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:19.333 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:53:19.806 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:53:20.278 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:53:20.750 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:53:21.224 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:53:21.696 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:53:22.168 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:53:22.639 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:53:23.112 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:53:23.585 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:53:24.057 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:53:24.528 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:53:25.001 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:53:25.473 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:53:25.945 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:53:26.416 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:53:26.890 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:53:27.362 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:53:27.833 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:53:28.305 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:53:28.778 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:53:29.251 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:53:29.722 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:53:30.194 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:53:30.667 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:53:31.139 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:53:31.611 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:53:32.082 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:53:32.553 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:53:33.024 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:53:33.498 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:53:33.969 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:53:34.441 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:53:34.912 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:53:35.385 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:53:35.858 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:53:36.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:36.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:53:36.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:36.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:36.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:36.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:36.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:36.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:36.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:36.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:36.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:36.152 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:53:36.152 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:53:36.152 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4757 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:36.152 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4757 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:36.152 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4757 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:36.152 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4757 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:36.152 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4757 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:36.152 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4757 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:53:41.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:53:41.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:53:41.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:41.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:41.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:41.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:41.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:53:41.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:41.164 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:41.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:53:41.164 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:53:41.167 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:53:41.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:53:41.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:41.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:41.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:53:41.168 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:53:41.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:53:41.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:53:41.170 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:53:41.170 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:53:41.171 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:41.171 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:41.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:53:41.171 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:53:41.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:53:41.172 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:53:41.173 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:53:41.173 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:53:41.174 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:41.174 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:53:41.174 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:53:41.174 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:53:41.174 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:53:41.174 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:53:41.177 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:53:41.178 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:53:41.178 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:53:41.178 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:53:41.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:53:41.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:53:41.183 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:53:41.661 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:53:41.704 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:53:41.706 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:53:41.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:53:41.708 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:53:41.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:53:41.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:53:41.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:53:41.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:53:41.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:53:41.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:53:41.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:53:41.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:53:42.133 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:53:42.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:42.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:42.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:42.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:42.605 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:53:43.078 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:53:43.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:43.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:43.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:43.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:43.551 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:53:44.023 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:53:44.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:44.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:44.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:44.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:44.494 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:53:44.967 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:53:45.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:45.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:45.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:45.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:45.439 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:53:45.911 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:53:46.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:53:46.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:53:46.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:53:46.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:53:46.382 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:53:46.855 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:53:47.327 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:53:47.799 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:53:48.270 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:53:48.744 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:53:49.216 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:53:49.688 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:53:50.159 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:53:50.630 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:53:51.104 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:53:51.576 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:53:52.048 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:53:52.521 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:53:52.994 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:53:53.466 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:53:53.937 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:53:54.410 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:53:54.882 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:53:55.354 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:53:55.825 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:53:56.297 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:53:56.771 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:53:57.242 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:53:57.714 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:53:58.187 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:53:58.659 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:53:59.131 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:53:59.602 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:54:00.076 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:54:00.548 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:54:01.020 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:54:01.491 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:54:01.965 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:54:02.437 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:54:02.909 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:54:03.380 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:54:03.853 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:54:04.326 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:54:04.798 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:54:05.269 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:54:05.742 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:54:06.214 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:54:06.686 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:54:07.157 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:54:07.631 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:54:08.102 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:54:08.574 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:54:09.045 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:54:09.519 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:54:09.991 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:54:10.463 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:54:10.934 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:54:11.405 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:54:11.879 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:54:12.351 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:54:12.823 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:54:13.294 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:54:13.767 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:54:14.240 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:54:14.712 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:54:15.183 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:54:15.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:54:15.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:15.203 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:15.203 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:54:15.203 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:20.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:20.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:54:20.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:20.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:20.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:20.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:20.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:20.219 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:20.219 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:20.219 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:20.220 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:54:20.222 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:54:20.222 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:54:20.222 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:20.223 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:20.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:20.223 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:54:20.223 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:20.223 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:54:20.224 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:54:20.225 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:54:20.225 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:20.225 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:20.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:20.225 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:54:20.225 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:20.225 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:54:20.227 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:54:20.227 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:54:20.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:20.227 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:20.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:20.227 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:54:20.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:20.227 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:54:20.230 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:54:20.230 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:54:20.230 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:20.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:20.235 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:54:20.709 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:54:20.757 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:54:20.760 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:54:20.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:54:20.761 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:54:20.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:54:20.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:54:20.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:54:20.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:54:20.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:54:20.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:54:20.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:54:20.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:54:21.181 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:54:21.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:21.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:21.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:21.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:21.653 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:54:22.126 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:54:22.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:22.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:22.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:22.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:22.598 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:54:23.070 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:54:23.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:23.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:23.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:23.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:23.541 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:54:24.014 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:54:24.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:24.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:24.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:24.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:24.487 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:54:24.959 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:54:25.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:25.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:25.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:25.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:25.430 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:54:25.903 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:54:26.375 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:54:26.848 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:54:27.318 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:54:27.792 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:54:28.264 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:54:28.736 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:54:29.207 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:54:29.681 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:54:30.153 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:54:30.625 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:54:31.096 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:54:31.569 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:54:32.042 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:54:32.514 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:54:32.985 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:54:33.458 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:54:33.931 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:54:34.403 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:54:34.874 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:54:35.347 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:54:35.820 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:54:36.292 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:54:36.765 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:54:37.238 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:54:37.710 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:54:38.181 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:54:38.654 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:54:39.127 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:54:39.599 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:54:40.070 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:54:40.543 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:54:41.016 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:54:41.488 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:54:41.961 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:54:42.433 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:54:42.905 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:54:43.376 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:54:43.850 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:54:44.322 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:54:44.794 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:54:45.265 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:54:45.738 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:54:46.211 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:54:46.683 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:54:47.154 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:54:47.627 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:54:48.100 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:54:48.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:54:48.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:54:48.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:48.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:48.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:48.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:48.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:48.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:48.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:48.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:48.255 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:48.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:54:48.255 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:53.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:53.260 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:54:53.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:53.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:53.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:53.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:53.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:53.267 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:53.267 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:53.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:53.268 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:54:53.271 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:54:53.272 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:54:53.272 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:53.272 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:53.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:53.273 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:54:53.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:53.274 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:54:53.275 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:54:53.276 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:54:53.276 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:53.276 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:53.276 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:53.276 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:54:53.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:53.277 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:54:53.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:54:53.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:54:53.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:53.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:53.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:53.279 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:54:53.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:53.279 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:54:53.282 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:54:53.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:54:53.282 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:54:53.282 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:54:53.282 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:54:53.283 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:54:53.283 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:54:53.283 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:54:53.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:53.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:53.288 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:54:53.764 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:54:53.809 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:54:53.811 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:54:53.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:54:53.813 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:54:53.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:53.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:53.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:53.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:53.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:53.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:53.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:53.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:53.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:53.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:54:53.829 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:58.832 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:58.832 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:54:58.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:58.832 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:58.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:58.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:58.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:58.839 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:58.839 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:58.839 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:54:58.840 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:54:58.843 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:54:58.844 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:54:58.844 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:58.844 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:58.845 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:58.845 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:54:58.845 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:54:58.845 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:54:58.848 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:54:58.848 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:54:58.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:58.849 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:58.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:58.850 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:54:58.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:54:58.850 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:54:58.852 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:54:58.852 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:54:58.852 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:58.852 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:54:58.852 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:58.852 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:54:58.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:54:58.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:54:58.856 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:54:58.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:54:58.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:54:58.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:54:58.857 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:54:58.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:54:58.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:54:58.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:54:59.340 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:54:59.383 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:54:59.383 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:54:59.384 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:54:59.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:54:59.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:54:59.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:54:59.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:54:59.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:54:59.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:54:59.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:54:59.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:54:59.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:54:59.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:54:59.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:54:59.401 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:54:59.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:04.405 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:04.405 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:04.405 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:04.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:04.405 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:04.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:04.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:04.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:04.413 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:04.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:04.413 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:04.416 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:04.416 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:04.416 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:04.416 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:04.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:04.417 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:04.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:04.417 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:04.421 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:04.421 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:04.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:04.421 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:04.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:04.421 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:04.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:04.422 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:04.425 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:04.425 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:04.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:04.425 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:04.425 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:04.426 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:04.426 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:04.426 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:04.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.432 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:55:04.432 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:55:04.432 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:04.432 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:04.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:04.437 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:04.915 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:04.965 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:04.967 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:04.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:04.970 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:04.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:04.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:04.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:04.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:04.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:04.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:04.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:04.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:04.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:04.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:04.988 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:04.988 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:04.988 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:04.988 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:04.988 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:09.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:09.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:09.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:09.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:09.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:09.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:10.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:10.002 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:10.002 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:10.002 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:10.002 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:10.006 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:10.006 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:10.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:10.006 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:10.007 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:10.007 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:10.007 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:10.007 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:10.009 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:10.009 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:10.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:10.009 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:10.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:10.009 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:10.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:10.009 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:10.011 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:10.012 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:10.012 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:10.012 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:10.012 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:10.012 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:10.012 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:10.012 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:55:10.015 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:55:10.015 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:10.015 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:10.020 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:10.497 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:10.540 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:10.542 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:10.544 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:10.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:10.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:10.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:10.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:55:10.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:10.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:10.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:10.549 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:55:10.549 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:55:10.970 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:11.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:11.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:11.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:11.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:11.441 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:11.911 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:12.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:12.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:12.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:12.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:12.383 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:12.856 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:13.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:13.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:13.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:13.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:13.328 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:13.800 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:14.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:14.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:14.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:14.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:14.271 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:14.742 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:15.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:15.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:15.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:15.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:15.215 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:15.687 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:16.160 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:16.630 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:17.101 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:17.575 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:18.047 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:18.519 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:55:18.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:18.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:18.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:18.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:18.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:18.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:18.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:18.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:18.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:18.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:18.603 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:18.603 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:18.603 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:18.603 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.603 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.603 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.603 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.603 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:18.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:23.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:23.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:23.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:23.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:23.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:23.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:23.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:23.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:23.617 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:23.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:23.618 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:23.624 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:23.624 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:23.625 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:23.625 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:23.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:23.625 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:23.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:23.626 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:23.629 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:23.629 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:23.630 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:23.630 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:23.630 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:23.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:23.630 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:23.630 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:23.634 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:23.634 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:23.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:23.634 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:23.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:23.634 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:23.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:23.634 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:23.638 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:23.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:23.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:23.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:23.638 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:55:23.639 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:55:23.639 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:23.639 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:23.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:23.644 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:24.122 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:24.166 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:24.168 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:24.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:24.170 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:24.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:24.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:24.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:55:24.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:24.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:24.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:24.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:55:24.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:55:24.594 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:24.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:24.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:24.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:24.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:25.066 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:25.539 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:25.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:25.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:25.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:25.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:26.011 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:26.483 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:26.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:26.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:26.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:26.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:26.954 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:27.425 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:27.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:27.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:27.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:27.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:27.896 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:28.369 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:28.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:28.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:28.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:28.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:28.841 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:29.313 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:29.784 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:30.258 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:30.730 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:31.201 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:31.673 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:32.146 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:55:32.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:32.219 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:32.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:32.224 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:32.224 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:32.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:32.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:32.226 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:32.226 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:32.226 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:32.226 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:32.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:32.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:32.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:32.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:32.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:32.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:32.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:32.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:37.231 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:37.231 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:37.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:37.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:37.231 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:37.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:37.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:37.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:37.241 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:37.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:37.241 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:37.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:37.243 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:37.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:37.243 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:37.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:37.243 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:37.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:37.244 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:37.245 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:37.245 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:37.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:37.246 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:37.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:37.246 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:37.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:37.246 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:37.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:37.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:37.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:37.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:37.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:37.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:37.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:37.248 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:55:37.251 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:55:37.251 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:37.251 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:37.256 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:37.732 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:37.773 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:37.775 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:37.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:37.779 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:37.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:37.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:37.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:55:37.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:37.783 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:37.783 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:37.784 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:55:37.784 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:55:38.204 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:38.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:38.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:38.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:38.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:38.675 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:39.147 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:39.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:39.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:39.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:39.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:39.617 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:40.091 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:40.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:40.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:40.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:40.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:40.563 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:41.035 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:41.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:41.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:41.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:41.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:41.506 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:41.979 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:42.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:42.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:42.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:42.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:42.452 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:42.924 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:43.395 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:43.868 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:44.340 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:44.812 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:45.283 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:45.756 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:55:45.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:45.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:45.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:45.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:45.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:45.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:45.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:45.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:45.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:45.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:45.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:45.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:45.842 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:45.843 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:45.843 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:45.843 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:45.843 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:45.843 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:45.843 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:50.843 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:50.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:50.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:50.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:50.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:50.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:50.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:50.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:50.855 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:50.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:55:50.856 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:55:50.862 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:55:50.862 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:55:50.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:50.863 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:50.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:50.864 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:55:50.864 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:55:50.864 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:55:50.867 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:55:50.867 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:55:50.867 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:50.867 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:50.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:50.868 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:55:50.868 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:55:50.868 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:55:50.871 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:55:50.871 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:55:50.871 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:50.871 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:55:50.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:50.871 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:55:50.871 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:55:50.871 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:55:50.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:55:50.876 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:55:50.876 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:55:50.876 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:55:50.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:55:50.881 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:55:51.358 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:55:51.404 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:55:51.406 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:55:51.409 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:55:51.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:55:51.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:51.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:51.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:55:51.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:55:51.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:55:51.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:55:51.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:55:51.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:55:51.830 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:55:51.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:51.879 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:51.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:51.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:52.301 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:55:52.772 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:55:52.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:52.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:52.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:52.881 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:53.245 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:55:53.718 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:55:53.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:53.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:53.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:53.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:54.190 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:55:54.661 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:55:54.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:54.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:54.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:54.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:55.134 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:55:55.606 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:55:55.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:55.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:55.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:55.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:56.078 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:55:56.549 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:55:57.023 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:55:57.495 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:55:57.967 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:55:58.438 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:55:58.912 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:55:59.384 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:55:59.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:55:59.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:55:59.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:55:59.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:55:59.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:55:59.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:55:59.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:55:59.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:55:59.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:55:59.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:55:59.467 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:55:59.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:55:59.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.468 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.469 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.469 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.469 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:55:59.469 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:04.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:04.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:56:04.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:04.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:04.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:04.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:04.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:04.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:04.484 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:04.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:04.485 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:04.489 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:04.489 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:04.490 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:04.490 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:04.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:04.490 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:04.490 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:04.490 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:04.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:04.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:04.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:04.494 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:04.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:04.494 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:04.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:04.495 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:04.496 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:04.496 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:04.496 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:04.496 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:04.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:04.496 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:04.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:04.497 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.500 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:56:04.500 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:56:04.500 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:04.500 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:04.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:04.505 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:04.983 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:05.023 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:05.025 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:05.026 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:05.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:05.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:05.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:56:05.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:56:05.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:56:05.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:56:05.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:56:05.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:56:05.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:56:05.454 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:56:05.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:05.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:05.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:05.503 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:05.926 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:56:06.397 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:56:06.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:06.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:06.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:06.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:06.870 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:56:07.342 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:56:07.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:07.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:07.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:07.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:07.814 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:56:08.285 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:56:08.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:08.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:08.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:08.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:08.759 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:56:09.231 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:56:09.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:09.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:09.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:09.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:09.703 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:56:10.174 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:56:10.647 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:56:11.120 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:56:11.591 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:56:12.063 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:56:12.536 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:56:13.008 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:56:13.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:13.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:56:13.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:13.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:13.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:13.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:13.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:13.091 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:13.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:13.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:13.091 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:13.091 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:56:13.091 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:13.091 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:13.092 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:13.092 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:13.092 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:13.092 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:13.092 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:18.093 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:18.093 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:56:18.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:18.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:18.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:18.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:18.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:18.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:18.104 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:18.105 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:18.105 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:18.110 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:18.111 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:18.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:18.111 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:18.111 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:18.111 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:18.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:18.111 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:18.115 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:18.115 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:18.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:18.115 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:18.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:18.116 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:18.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:18.116 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:18.119 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:18.119 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:18.119 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:18.119 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:18.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:18.119 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:18.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:18.120 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:18.123 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:18.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:18.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:18.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:18.123 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:56:18.124 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:56:18.124 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:18.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:18.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:18.129 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:18.606 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:18.649 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:18.651 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:18.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:18.652 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:18.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:18.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:56:18.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:56:18.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:56:18.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:56:18.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:56:18.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:56:18.656 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:56:19.078 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:56:19.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:19.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:19.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:19.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:19.549 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:56:20.022 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:56:20.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:20.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:20.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:20.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:20.495 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:56:20.966 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:56:21.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:21.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:21.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:21.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:21.438 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:56:21.911 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:56:22.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:22.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:22.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:22.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:22.383 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:56:22.855 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:56:23.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:23.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:23.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:23.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:23.327 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:56:23.800 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:56:24.272 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:56:24.744 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:56:25.215 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:56:25.689 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:56:26.161 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:56:26.633 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:56:27.104 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:56:27.577 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:56:28.049 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:56:28.521 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:56:28.992 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:56:29.466 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:56:29.938 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:56:30.409 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:56:30.880 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:56:31.351 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:56:31.822 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:56:32.293 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:56:32.764 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:56:33.236 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:56:33.709 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:56:34.181 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:56:34.652 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:56:34.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:34.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:56:34.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:34.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:34.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:34.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:34.718 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:34.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:34.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:34.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:34.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:34.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:56:34.719 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:34.719 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3586 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:34.719 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3586 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:34.720 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3586 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:34.720 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3586 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:34.720 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3586 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:34.720 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3586 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:56:39.721 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:39.721 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:56:39.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:39.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:39.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:39.721 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:39.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:39.730 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:39.730 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:39.731 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:39.731 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:39.734 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:39.734 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:39.734 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:39.734 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:39.734 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:39.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:39.735 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:39.735 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:39.739 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:39.739 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:39.739 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:39.740 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:39.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:39.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:39.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:39.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:39.743 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:39.744 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:39.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:39.744 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:39.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:39.744 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:39.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:39.744 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:39.749 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:39.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:39.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:39.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:39.749 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.750 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:56:39.750 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:56:39.750 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:39.750 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:39.755 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:40.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:40.276 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:40.278 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:40.280 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:40.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:40.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:40.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:56:40.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:56:40.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:56:40.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:56:40.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:56:40.294 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:56:40.294 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:56:40.705 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:56:40.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:40.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:40.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:40.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:41.177 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:56:41.650 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:56:41.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:41.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:41.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:41.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:42.122 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:56:42.594 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:56:42.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:42.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:42.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:42.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:43.065 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:56:43.536 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:56:43.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:43.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:43.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:43.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:44.010 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:56:44.482 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:56:44.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:44.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:44.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:44.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:44.954 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:56:45.425 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:56:45.895 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:56:46.366 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:56:46.837 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:56:47.308 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:56:47.779 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:56:48.252 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:56:48.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:48.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:56:48.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:48.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:48.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:48.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:48.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:48.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:48.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:48.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:56:48.348 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:56:48.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:48.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:53.352 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:56:53.352 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:56:53.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:53.352 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:53.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:53.352 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:53.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:56:53.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:53.360 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:53.361 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:56:53.361 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:56:53.363 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:56:53.363 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:56:53.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:53.364 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:53.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:56:53.364 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:56:53.364 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:56:53.364 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:56:53.366 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:56:53.366 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:56:53.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:53.366 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:53.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:56:53.366 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:56:53.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:56:53.366 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:56:53.368 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:56:53.368 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:56:53.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:53.368 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:56:53.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:56:53.369 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:56:53.369 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:56:53.369 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:56:53.371 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:56:53.371 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:56:53.371 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:56:53.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:56:53.376 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:56:53.853 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:56:53.895 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:56:53.897 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:56:53.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:56:53.899 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:56:53.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:56:53.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:56:53.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:56:53.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:56:53.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:56:53.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:56:53.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:56:53.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:56:54.325 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:56:54.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:54.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:54.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:54.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:54.796 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:56:55.267 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:56:55.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:55.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:55.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:55.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:55.741 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:56:56.213 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:56:56.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:56.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:56.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:56.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:56.685 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:56:57.155 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:56:57.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:57.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:57.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:57.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:57.627 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:56:58.100 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:56:58.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:56:58.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:56:58.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:56:58.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:56:58.572 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:56:59.044 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:56:59.515 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:56:59.986 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:57:00.459 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:57:00.931 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:57:01.403 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:57:01.874 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:57:02.345 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:57:02.818 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:57:03.291 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:57:03.763 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:57:04.234 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:57:04.707 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:57:05.179 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:57:05.651 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:57:06.122 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:57:06.595 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:57:07.068 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:57:07.540 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:57:08.011 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:57:08.484 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:57:08.956 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:57:09.428 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:57:09.899 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:57:09.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:09.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:09.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:09.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:09.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:09.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:09.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:09.972 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:09.972 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:09.972 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:09.972 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:09.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:09.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:09.973 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3588 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:09.973 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3588 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:09.973 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3588 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:09.973 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3588 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:09.973 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3588 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:09.973 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3588 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:14.977 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:14.977 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:14.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:14.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:14.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:14.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:14.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:14.984 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:14.984 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:14.984 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:14.984 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:14.986 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:14.987 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:14.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:14.987 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:14.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:14.988 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:14.988 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:14.988 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:14.990 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:14.990 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:14.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:14.991 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:14.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:14.991 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:14.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:14.991 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:14.993 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:14.993 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:14.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:14.993 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:14.993 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:14.993 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:14.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:14.993 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:14.997 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:14.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:14.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:14.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:14.997 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:14.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:57:14.998 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:57:14.998 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:14.998 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:14.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:14.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:15.003 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:15.480 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:15.526 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:15.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:15.529 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:15.531 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:15.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:15.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:15.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:15.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:15.569 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:15.569 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:15.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:15.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:15.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:15.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:15.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:15.572 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:15.572 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:15.572 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:15.572 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:20.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:20.576 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:20.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:20.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:20.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:20.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:20.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:20.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:20.584 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:20.585 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:20.587 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:20.587 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:20.587 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:20.587 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:20.588 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.588 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:20.588 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:20.590 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:20.590 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:20.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:20.591 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:20.591 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:20.591 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:20.593 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:20.593 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:20.593 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:20.593 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:20.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:20.594 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:20.594 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:20.597 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:20.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:20.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:20.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:20.597 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:57:20.598 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:57:20.598 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:20.598 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:20.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:20.603 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:21.081 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:21.120 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:21.122 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:21.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:21.124 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:21.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:21.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:21.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:21.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:21.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:21.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:21.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:21.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:21.176 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:21.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:21.176 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:21.176 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:21.176 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:21.176 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:21.176 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:21.176 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:21.176 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:26.179 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:26.179 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:26.179 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:26.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:26.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:26.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:26.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:26.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:26.190 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:26.190 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:26.195 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:26.196 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:26.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:26.196 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:26.197 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:26.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:26.200 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:26.200 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:26.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:26.200 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:26.201 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.201 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:26.201 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:26.203 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:26.203 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:26.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:26.204 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:26.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:26.204 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.204 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:26.204 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:26.207 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:26.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:26.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:26.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:26.207 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:26.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:57:26.208 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:57:26.208 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:26.208 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:26.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:26.212 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:26.690 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:26.730 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:26.732 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:26.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:26.736 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:26.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:26.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:26.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:26.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:26.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:26.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:26.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:26.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:26.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:26.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:26.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:26.776 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:26.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:26.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:31.781 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:31.781 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:31.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:31.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:31.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:31.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:31.791 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:31.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:31.793 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:31.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:31.794 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:31.800 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:31.800 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:31.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:31.801 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:31.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:31.802 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:31.802 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:31.802 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:31.805 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:31.805 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:31.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:31.806 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:31.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:31.806 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:31.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:31.806 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:31.810 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:31.810 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:31.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:31.811 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:31.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:31.811 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:31.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:31.811 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:31.815 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:31.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:31.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:31.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:31.815 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:31.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:57:31.816 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:57:31.816 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:31.816 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:31.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:31.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:31.821 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:32.299 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:32.344 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:32.346 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:32.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:32.348 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:32.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:32.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:32.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:32.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:32.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:32.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:32.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:32.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:32.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:32.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:32.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:32.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:32.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:32.392 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:32.392 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:37.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:37.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:37.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:37.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:37.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:37.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:37.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:37.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:37.417 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:37.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:37.418 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:37.425 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:37.425 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:37.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:37.426 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:37.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:37.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:37.427 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:37.427 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:37.429 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:37.429 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:37.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:37.430 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:37.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:37.430 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:37.431 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:37.431 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:37.432 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:37.433 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:37.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:37.433 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:37.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:37.433 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:37.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:37.433 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:57:37.437 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:57:37.437 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:37.437 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:37.441 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:37.920 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:37.959 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:37.961 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:37.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:37.963 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:37.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:37.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:37.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:37.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:37.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:37.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:38.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:38.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:38.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:38.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:38.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:38.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:38.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:38.004 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:38.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:38.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:38.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:38.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:38.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:38.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:38.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:38.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:38.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:57:43.010 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:43.010 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:43.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:43.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:43.010 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:43.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:43.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:43.013 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:43.014 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:43.014 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:43.014 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:43.015 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:43.015 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:43.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:43.015 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:43.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:43.015 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:43.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:43.015 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:43.016 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:43.016 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:43.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:43.016 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:43.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:43.016 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:43.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:43.016 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:43.017 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:43.017 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:43.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:43.017 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:43.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:43.017 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:43.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:43.017 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:57:43.020 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:57:43.020 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:43.020 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:43.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:43.024 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:43.503 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:43.545 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:43.547 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:43.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:43.550 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:43.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:43.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:43.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:43.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:43.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:43.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:43.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:43.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:43.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:43.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:43.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:43.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:43.645 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:43.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:43.646 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:57:43.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:43.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:48.651 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:57:48.651 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:57:48.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:48.651 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:48.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:48.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:48.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:57:48.659 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:48.659 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:48.659 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:57:48.659 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:57:48.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:57:48.662 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:57:48.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:48.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:48.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:57:48.663 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:57:48.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:57:48.663 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:57:48.664 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:57:48.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:57:48.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:48.665 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:48.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:57:48.665 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:57:48.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:57:48.665 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:57:48.667 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:57:48.667 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:57:48.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:48.667 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:57:48.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:57:48.667 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:57:48.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:57:48.667 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:57:48.669 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:57:48.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:57:48.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:57:48.670 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:57:48.670 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:57:48.670 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:57:48.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:57:48.675 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:57:49.153 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:57:49.193 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:57:49.195 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:57:49.198 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:57:49.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:57:49.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:57:49.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:57:49.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:57:49.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:57:49.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:57:49.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:57:49.203 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:57:49.203 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:57:49.625 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:57:49.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:49.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:49.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:49.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:50.096 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:57:50.567 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:57:50.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:50.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:50.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:50.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:51.040 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:57:51.513 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:57:51.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:51.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:51.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:51.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:51.985 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:57:52.456 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:57:52.676 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:52.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:52.676 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:52.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:52.930 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:57:53.402 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:57:53.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:57:53.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:57:53.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:57:53.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:57:53.873 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:57:54.345 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:57:54.818 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:57:55.290 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:57:55.762 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:57:56.233 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:57:56.707 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:57:57.179 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:57:57.651 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 01:57:58.122 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 01:57:58.596 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 01:57:59.068 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 01:57:59.540 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 01:58:00.011 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 01:58:00.484 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 01:58:00.957 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 01:58:01.428 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 01:58:01.900 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 01:58:02.373 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 01:58:02.846 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 01:58:03.317 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 01:58:03.789 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 01:58:04.259 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 01:58:04.733 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 01:58:05.205 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 01:58:05.677 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 01:58:06.148 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 01:58:06.622 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 01:58:07.094 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 01:58:07.566 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 01:58:08.037 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 01:58:08.511 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 01:58:08.983 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 01:58:09.455 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 01:58:09.926 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 01:58:10.399 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 01:58:10.871 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 01:58:11.344 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 01:58:11.817 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 01:58:12.289 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 01:58:12.761 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 01:58:13.232 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 01:58:13.706 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 01:58:14.178 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 01:58:14.650 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 01:58:15.121 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 01:58:15.594 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 01:58:16.067 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 01:58:16.538 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 01:58:17.010 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 01:58:17.483 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 01:58:17.956 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 01:58:18.427 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 01:58:18.899 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 01:58:19.372 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 01:58:19.844 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 01:58:20.316 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 01:58:20.787 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 01:58:21.260 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 01:58:21.733 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 01:58:22.205 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 01:58:22.676 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 01:58:22.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:58:22.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:58:22.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:22.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:22.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:22.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:22.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:22.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:22.698 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:22.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:22.698 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:22.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:22.698 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:22.698 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:22.699 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:22.699 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:22.699 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:22.699 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:22.699 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:22.699 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:27.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:27.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:27.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:27.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:27.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:27.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:27.707 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:27.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:27.708 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:27.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:27.708 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:27.710 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:27.711 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:27.711 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:27.711 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:27.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:27.712 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:27.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:27.712 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:27.714 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:27.714 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:27.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:27.714 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:27.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:27.715 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:27.715 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:27.715 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:27.717 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:27.717 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:27.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:27.717 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:27.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:27.718 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:27.718 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:27.718 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:58:27.721 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:58:27.721 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:27.721 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:27.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:27.726 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:28.204 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:28.250 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:28.253 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:28.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:28.256 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:28.676 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:28.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:28.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:28.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:28.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:29.149 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:29.622 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:29.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:29.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:29.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:29.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:30.094 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:30.565 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:30.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:30.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:30.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:30.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:31.040 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:31.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:31.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:31.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:31.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:31.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:31.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:31.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:31.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:31.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:31.292 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:31.292 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:31.292 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:31.292 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=770 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:31.292 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=770 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:31.292 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=770 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:31.292 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=770 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:31.292 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=770 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:36.296 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:36.296 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:36.296 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:36.296 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:36.296 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:36.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:36.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:36.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:36.303 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:36.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:36.303 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:36.304 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:36.304 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:36.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:36.304 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:36.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:36.304 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:36.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:36.304 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:36.305 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:36.305 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:36.305 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:36.305 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:36.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:36.305 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:36.305 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:36.305 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:36.309 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:36.309 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:36.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:36.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:36.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:36.310 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:36.310 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:36.310 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:36.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:58:36.316 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:58:36.316 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:36.316 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:36.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:36.321 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:36.796 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:36.846 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:36.848 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:36.850 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:36.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:37.268 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:37.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:37.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:37.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:37.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:37.742 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:38.214 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:38.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:38.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:38.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:38.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:38.686 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:39.160 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:39.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:39.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:39.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:39.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:39.632 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:40.104 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:58:40.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:40.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:40.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:40.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:40.578 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:58:41.050 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:58:41.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:41.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:41.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:41.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:41.522 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:58:41.996 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:58:42.468 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:58:42.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:42.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:42.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:42.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:42.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:42.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:42.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:42.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:42.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:42.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:42.867 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:47.874 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:47.874 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:47.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:47.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:47.874 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:47.874 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:47.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:47.880 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:47.880 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:47.880 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:47.880 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:47.884 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:47.884 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:47.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:47.884 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:47.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:47.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:47.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:47.885 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:47.888 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:47.888 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:47.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:47.888 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:47.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:47.888 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:47.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:47.888 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:47.891 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:47.891 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:47.891 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:47.891 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:47.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:47.891 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:47.891 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:47.891 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:58:47.895 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:58:47.895 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:47.895 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:47.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:47.900 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:48.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:48.421 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:58:48.423 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:58:48.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:58:48.425 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:58:48.850 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:58:48.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:48.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:48.899 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:48.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:49.325 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:58:49.797 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:58:49.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:49.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:49.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:49.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:50.272 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:58:50.744 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:58:50.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:50.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:50.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:50.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:51.219 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:58:51.691 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:58:51.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:51.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:51.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:51.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:52.166 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:58:52.638 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:58:52.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:52.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:52.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:52.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:53.114 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:58:53.586 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:58:54.061 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:58:54.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:58:54.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:58:54.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:58:54.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:58:54.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:54.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:54.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:54.442 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:58:54.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:54.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:54.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:54.442 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1410 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:54.442 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1410 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:54.442 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1410 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:54.442 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1410 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:54.442 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1410 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:54.442 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1410 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:58:59.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:58:59.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:58:59.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:59.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:59.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:59.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:59.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:58:59.456 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:59.456 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:59.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:58:59.457 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:58:59.460 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:58:59.460 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:58:59.461 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:59.461 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:59.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:58:59.462 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:58:59.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:58:59.462 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:58:59.464 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:58:59.464 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:58:59.464 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:59.464 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:59.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:58:59.465 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:58:59.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:58:59.465 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:58:59.467 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:58:59.467 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:58:59.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:59.467 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:58:59.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:58:59.467 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:58:59.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:58:59.467 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:58:59.471 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:58:59.471 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:58:59.471 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:58:59.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:58:59.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:58:59.953 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:58:59.999 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:00.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:00.000 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:00.001 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:00.424 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:00.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:00.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:00.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:00.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:00.898 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:01.371 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:01.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:01.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:01.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:01.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:01.842 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:02.318 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:02.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:02.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:02.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:02.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:02.790 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:03.264 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:59:03.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:03.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:03.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:03.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:03.736 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:59:04.208 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:59:04.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:04.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:04.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:04.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:04.683 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:59:05.155 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:59:05.630 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:59:06.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:06.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:06.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:06.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:06.012 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:06.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:06.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:06.012 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:06.012 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:06.012 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:06.012 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:11.017 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:11.017 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:11.017 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:11.017 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:11.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:11.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:11.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:11.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:11.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:11.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:11.026 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:11.029 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:11.030 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:11.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:11.030 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:11.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:11.030 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:11.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:11.031 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:11.035 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:11.035 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:11.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:11.035 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:11.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:11.036 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:11.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:11.036 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:11.040 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:11.040 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:11.040 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:11.040 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:11.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:11.040 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:11.041 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:11.041 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:11.046 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:11.046 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:59:11.047 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:59:11.047 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:11.047 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:11.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:11.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:11.052 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:11.527 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:11.565 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:11.565 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:11.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:11.566 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:11.994 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:12.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:12.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:12.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:12.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:12.465 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:12.940 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:13.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:13.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:13.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:13.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:13.412 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:13.888 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:14.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:14.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:14.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:14.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:14.360 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:14.835 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:59:15.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:15.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:15.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:15.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:15.307 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:59:15.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:15.782 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 01:59:16.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:16.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:16.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:16.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:16.254 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 01:59:16.730 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 01:59:17.202 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 01:59:17.675 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 01:59:18.148 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 01:59:18.620 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 01:59:19.095 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 01:59:19.567 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 01:59:19.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:19.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:19.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:19.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:19.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:19.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:19.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:19.594 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:19.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:19.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:19.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:19.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:19.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:19.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:19.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:19.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:19.595 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:24.601 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:24.601 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:24.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:24.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:24.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:24.601 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:24.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:24.612 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:24.612 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:24.612 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:24.612 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:24.616 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:24.616 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:24.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:24.616 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:24.617 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:24.617 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:24.617 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:24.617 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:24.620 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:24.621 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:24.621 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:24.621 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:24.621 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:24.621 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:24.621 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:24.621 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:24.624 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:24.624 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:24.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:24.624 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:24.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:24.624 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:24.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:24.625 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:24.627 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:59:24.628 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:59:24.628 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:24.628 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:24.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:24.633 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:25.111 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:25.154 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:25.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:25.157 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:25.161 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:25.583 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:25.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:25.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:25.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:25.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:26.057 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:26.529 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:26.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:26.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:26.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:26.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:27.001 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:27.475 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:27.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:27.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:27.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:27.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:27.947 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:28.419 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 01:59:28.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:28.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:28.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:28.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:28.893 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 01:59:29.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:29.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:29.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:29.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:29.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:29.179 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:29.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:29.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:29.179 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:29.179 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:29.179 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:34.184 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:34.184 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:34.184 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:34.184 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:34.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:34.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:34.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:34.192 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:34.192 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:34.193 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:34.193 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:34.197 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:34.197 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:34.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:34.197 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:34.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:34.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:34.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:34.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:34.201 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:34.202 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:34.202 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:34.202 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:34.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:34.202 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:34.202 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:34.202 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:34.205 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:34.205 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:34.205 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:34.205 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:34.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:34.205 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:34.206 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:34.206 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.209 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:59:34.209 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:59:34.209 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:34.210 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:34.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:34.214 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:34.693 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:34.734 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:34.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:34.736 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:34.740 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:34.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:34.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:34.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:34.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:34.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:34.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:34.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:34.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:34.758 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:34.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:34.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:34.759 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:34.759 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:34.759 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:34.759 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:34.759 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:34.759 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:39.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:39.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:39.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:39.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:39.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:39.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:39.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:39.771 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:39.771 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:39.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:39.772 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:39.777 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:39.778 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:39.778 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:39.778 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:39.778 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:39.778 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:39.778 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:39.778 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:39.782 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:39.782 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:39.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:39.782 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:39.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:39.783 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:39.783 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:39.783 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:39.786 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:39.786 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:39.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:39.786 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:39.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:39.786 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:39.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:39.786 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:59:39.791 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:59:39.791 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:39.791 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:39.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:39.795 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:40.274 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:40.312 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:40.313 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:40.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:40.315 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:40.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:40.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:40.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:40.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:40.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:40.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:40.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:40.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:40.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:40.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:40.330 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:40.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:40.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:45.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:45.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:45.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:45.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:45.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:45.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:45.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:45.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:45.344 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:45.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:45.344 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:45.349 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:45.350 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:45.350 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:45.350 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:45.350 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:45.350 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:45.350 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:45.350 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:45.355 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:45.355 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:45.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:45.355 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:45.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:45.355 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:45.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:45.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:45.359 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:45.360 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:45.360 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:45.360 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:45.360 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:45.360 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:45.360 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:45.360 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:59:45.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:59:45.366 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:45.367 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:45.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:45.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:45.371 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:45.850 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:45.899 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:45.901 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:45.903 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:45.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:45.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:45.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:45.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:45.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:45.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:45.919 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:45.919 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:45.919 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:45.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:45.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:50.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:50.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:50.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:50.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:50.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:50.924 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:50.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:50.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:50.932 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:50.933 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:50.933 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:50.936 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:50.936 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:50.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:50.937 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:50.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:50.938 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:50.938 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:50.938 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:50.940 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:50.940 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:50.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:50.940 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:50.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:50.941 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:50.941 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:50.941 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:50.943 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:50.944 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:50.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:50.944 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:50.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:50.944 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:50.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:50.944 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:50.947 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:50.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:50.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:50.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:50.947 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:50.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:59:50.948 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:59:50.948 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:50.948 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:50.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:50.953 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 01:59:51.431 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 01:59:51.474 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 01:59:51.477 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 01:59:51.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:51.479 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 01:59:51.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:51.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:59:51.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 01:59:51.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:51.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:51.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:51.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 01:59:51.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 01:59:51.903 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 01:59:51.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:51.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:51.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:51.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:52.374 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 01:59:52.845 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 01:59:52.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:52.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:52.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:52.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:53.318 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 01:59:53.791 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 01:59:53.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:53.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:53.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:53.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:54.263 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 01:59:54.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 01:59:54.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 01:59:54.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:54.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 01:59:54.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 01:59:54.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 01:59:54.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 01:59:54.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 01:59:54.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 01:59:54.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 01:59:54.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 01:59:54.600 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:54.601 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:54.601 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:54.601 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 01:59:54.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:54.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:54.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:54.601 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:54.601 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:54.601 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:54.601 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:54.601 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:54.601 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 01:59:59.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 01:59:59.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 01:59:59.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:59.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:59.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:59.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:59.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 01:59:59.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:59.611 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:59.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 01:59:59.611 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 01:59:59.612 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 01:59:59.612 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 01:59:59.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:59.612 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:59.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 01:59:59.612 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 01:59:59.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 01:59:59.613 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 01:59:59.616 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 01:59:59.616 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 01:59:59.616 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:59.617 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:59.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 01:59:59.617 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 01:59:59.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 01:59:59.617 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 01:59:59.621 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 01:59:59.621 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 01:59:59.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:59.621 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 01:59:59.621 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 01:59:59.621 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 01:59:59.622 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 01:59:59.622 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 01:59:59.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 01:59:59.628 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 01:59:59.628 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 01:59:59.628 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 01:59:59.633 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:00.111 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:00.158 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:00.160 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:00.162 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:00.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:00.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:00.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:00.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:00:00.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:00.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:00.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:00.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:00:00.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:00:00.583 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:00.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:00.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:00.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:00.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:01.055 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:01.528 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:01.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:01.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:01.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:01.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:02.000 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:02.473 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:02.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:02.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:02.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:02.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:02.943 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:03.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:03.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:03.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:03.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:03.417 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:03.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:03.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:03.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:03.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:03.889 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:03.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:03.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:03.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:03.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:03.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:03.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:03.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:03.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:03.910 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:03.910 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:03.910 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:03.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:03.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:08.917 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:08.917 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:08.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:08.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:08.917 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:08.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:08.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:08.925 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:08.925 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:08.925 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:08.925 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:08.929 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:08.929 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:08.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:08.929 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:08.929 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:08.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:08.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:08.929 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:08.932 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:08.932 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:08.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:08.933 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:08.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:08.933 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:08.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:08.933 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:08.935 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:08.935 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:08.936 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:08.936 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:08.936 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:08.936 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:08.936 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:08.936 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:08.939 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:08.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:08.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:08.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:00:08.940 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:00:08.940 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:08.940 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:08.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:08.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:08.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:08.945 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:09.422 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:09.463 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:09.464 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:09.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:09.466 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:09.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:09.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:09.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:00:09.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:09.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:09.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:09.478 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:00:09.478 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:00:09.895 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:09.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:09.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:09.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:09.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:10.366 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:10.839 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:10.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:10.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:10.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:10.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:11.311 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:11.783 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:11.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:11.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:11.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:11.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:12.254 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:12.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:12.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:12.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:12.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:12.728 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:12.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:12.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:12.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:12.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:13.200 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:13.672 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:13.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:13.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:13.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:13.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:14.143 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:14.614 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:00:15.084 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:00:15.555 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:00:16.028 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:00:16.501 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:00:16.973 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:00:17.444 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:00:17.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:17.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:17.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:17.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:17.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:17.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:17.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:17.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:17.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:17.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:17.561 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:17.561 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:17.561 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:17.561 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:17.561 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1863 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:17.561 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1863 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:17.561 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1863 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:17.561 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1863 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:17.561 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1863 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:22.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:22.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:22.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:22.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:22.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:22.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:22.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:22.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:22.573 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:22.574 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:22.574 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:22.577 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:22.577 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:22.577 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:22.577 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:22.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:22.578 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:22.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:22.578 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:22.581 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:22.582 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:22.582 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:22.582 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:22.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:22.583 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:22.583 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:22.583 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:22.585 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:22.585 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:22.585 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:22.585 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:22.585 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:22.585 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:22.585 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:22.585 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.589 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:00:22.589 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:00:22.589 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:22.590 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:22.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:22.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:22.594 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:23.073 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:23.124 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:23.127 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:23.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:23.127 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:23.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:23.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:23.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:00:23.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:23.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:23.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:23.138 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:00:23.138 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:00:23.544 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:23.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:23.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:23.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:23.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:24.016 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:24.489 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:24.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:24.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:24.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:24.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:24.962 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:25.434 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:25.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:25.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:25.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:25.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:25.905 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:26.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:26.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:26.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:26.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:26.378 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:26.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:26.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:26.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:26.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:26.850 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:27.322 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:27.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:27.794 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:28.267 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:00:28.739 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:00:29.211 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:00:29.682 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:00:30.155 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:00:30.627 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:00:31.099 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:00:31.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:31.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:31.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:31.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:31.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:31.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:31.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:31.210 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:31.210 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:31.210 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:31.210 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:31.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:31.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:31.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:31.211 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:31.211 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:31.211 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:31.211 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:31.211 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:31.211 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:36.215 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:36.215 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:36.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:36.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:36.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:36.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:36.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:36.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:36.225 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:36.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:36.225 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:36.228 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:36.229 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:36.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:36.229 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:36.229 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:36.230 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:36.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:36.230 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:36.232 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:36.232 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:36.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:36.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:36.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:36.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:36.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:36.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:36.235 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:36.235 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:36.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:36.235 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:36.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:36.236 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:36.236 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:36.236 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:00:36.239 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:00:36.239 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:36.239 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:36.244 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:36.722 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:36.762 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:36.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:36.765 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:36.768 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:36.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:36.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:36.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:00:36.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:36.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:36.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:36.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:00:36.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:00:37.194 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:37.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:37.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:37.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:37.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:37.666 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:38.139 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:38.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:38.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:38.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:38.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:38.611 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:39.083 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:39.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:39.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:39.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:39.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:39.554 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:39.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:39.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:39.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:39.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:40.027 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:40.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:40.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:40.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:40.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:40.500 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:40.972 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:41.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:41.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:41.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:41.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:41.443 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:41.917 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:00:42.389 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:00:42.861 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:00:43.332 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:00:43.805 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:00:44.278 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:00:44.750 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:00:44.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:44.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:44.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:44.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:44.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:44.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:44.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:44.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:44.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:44.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:44.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:44.861 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:44.861 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:44.861 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:44.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:44.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:44.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:44.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:44.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:44.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:49.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:49.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:49.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:49.866 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:49.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:49.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:49.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:49.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:49.869 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.870 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:00:49.870 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:00:49.870 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:00:49.871 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:00:49.871 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:49.871 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:49.871 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.871 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:00:49.871 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:00:49.872 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:00:49.872 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:00:49.872 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:49.872 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:49.872 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.872 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:00:49.872 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:00:49.873 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:00:49.873 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:00:49.873 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:49.873 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:00:49.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:49.873 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.873 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:00:49.873 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.875 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:00:49.875 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:00:49.875 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:00:49.876 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:00:49.880 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:00:50.358 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:00:50.402 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:00:50.404 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:00:50.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:00:50.407 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:00:50.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:50.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:50.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:00:50.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:50.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:50.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:50.415 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:00:50.415 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:00:50.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:00:50.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:00:50.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:50.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:00:50.830 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:00:50.878 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:50.879 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:50.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:50.879 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:51.301 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:00:51.772 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:00:51.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:51.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:51.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:51.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:52.243 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:00:52.717 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:00:52.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:52.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:52.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:52.881 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:53.189 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:00:53.661 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:00:53.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:53.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:53.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:53.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:54.132 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:00:54.603 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:00:54.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:54.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:54.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:54.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:55.076 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:00:55.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:00:55.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:00:55.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:00:55.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:00:55.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:00:55.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:00:55.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:00:55.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:00:55.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:00:55.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:00:55.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:00:55.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:00:55.465 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:00:55.465 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:55.466 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:55.466 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:55.466 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:55.466 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:00:55.466 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:00.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:00.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:00.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:00.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:00.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:00.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:00.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:00.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:00.473 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:00.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:00.473 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:00.474 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:00.474 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:00.474 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:00.474 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:00.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:00.475 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:00.475 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:00.475 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:00.475 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:00.475 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:00.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:00.475 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:00.475 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:00.476 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:00.476 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:00.476 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:00.477 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:00.477 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:00.477 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:00.477 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:00.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:00.477 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:00.477 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:00.477 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:01:00.479 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:01:00.479 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:00.479 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:00.484 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:00.962 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:01.002 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:01.004 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:01.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:01.008 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:01.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:01.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:01.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:01:01.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:01.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:01.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:01.018 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:01:01.018 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:01:01.434 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:01.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:01.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:01.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:01.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:01.905 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:02.379 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:02.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:02.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:02.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:02.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:02.851 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:03.323 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:03.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:03.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:03.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:03.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:03.794 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:04.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:04.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:04.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:04.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:04.264 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:01:04.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:04.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:04.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:04.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:04.728 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:01:05.192 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:01:05.486 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:05.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:05.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:05.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:05.657 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:01:06.129 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:01:06.601 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:01:06.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:06.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:06.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:06.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:06.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:06.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:06.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:06.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:06.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:06.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:06.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:06.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:06.658 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:06.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:11.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:11.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:11.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:11.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:11.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:11.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:11.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:11.663 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:11.663 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:11.663 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:11.663 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:11.664 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:11.664 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:11.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:11.664 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:11.665 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:11.665 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:11.665 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:11.665 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:11.666 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:11.666 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:11.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:11.666 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:11.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:11.666 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:11.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:11.666 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:11.667 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:11.667 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:11.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:11.667 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:11.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:11.667 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:11.667 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:11.667 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:01:11.669 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:01:11.669 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:11.674 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:12.140 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:12.181 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:12.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:12.182 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:12.182 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:12.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:12.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:12.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:01:12.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:12.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:12.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:12.184 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:01:12.184 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:01:12.603 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:12.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:12.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:12.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:12.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:13.073 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:13.539 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:13.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:13.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:13.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:13.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:14.003 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:14.470 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:14.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:14.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:14.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:14.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:14.936 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:15.401 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:01:15.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:15.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:15.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:15.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:15.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:15.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:15.433 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:15.434 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:15.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:15.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:15.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:15.434 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:15.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:15.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:20.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:20.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:20.445 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:20.445 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:20.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:20.445 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:20.453 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:20.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:20.453 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:20.454 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:20.454 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:20.456 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:20.456 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:20.456 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:20.456 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:20.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:20.457 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:20.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:20.457 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:20.458 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:20.458 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:20.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:20.458 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:20.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:20.458 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:20.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:20.458 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:20.460 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:20.460 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:20.460 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:20.460 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:20.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:20.460 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:20.460 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:20.460 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:01:20.462 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:01:20.462 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:20.462 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:20.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:20.467 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:20.938 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:20.986 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:20.988 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:20.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:20.989 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:20.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:20.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:20.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:01:20.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:20.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:20.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:20.994 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:01:20.994 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:01:21.406 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:21.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:21.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:21.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:21.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:21.876 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:22.347 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:22.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:22.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:22.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:22.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:22.817 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:23.287 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:23.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:23.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:23.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:23.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:23.759 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:24.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:24.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:24.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:24.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:24.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:24.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:24.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:24.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:24.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:24.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:24.080 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:24.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:24.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:24.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:24.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:24.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:24.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:24.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:24.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:24.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:29.078 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:29.078 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:29.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:29.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:29.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:29.078 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:29.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:29.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:29.083 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:29.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:29.083 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:29.084 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:29.084 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:29.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:29.084 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:29.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:29.084 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:29.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:29.084 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:29.085 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:29.085 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:29.085 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:29.085 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:29.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:29.085 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:29.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:29.086 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:29.087 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:29.087 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:29.087 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:29.087 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:29.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:29.087 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:29.087 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:29.087 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:29.088 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:29.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:29.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:01:29.089 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:01:29.089 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:29.089 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:29.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:29.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:29.093 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:29.561 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:29.606 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:29.607 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:29.608 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:29.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:29.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:29.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:29.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:01:29.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:29.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:29.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:29.611 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:01:29.611 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:01:29.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:29.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:29.878 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:29.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:29.878 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:29.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:29.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:29.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:29.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:29.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:29.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:29.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:29.879 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:34.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:34.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:34.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:34.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:34.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:34.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:34.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:34.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:34.885 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:34.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:34.885 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:34.886 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:34.886 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:34.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:34.887 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:34.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:34.887 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:34.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:34.887 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:34.888 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:34.888 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:34.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:34.888 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:34.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:34.888 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:34.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:34.888 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:34.889 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:34.889 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:34.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:34.889 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:34.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:34.889 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:34.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:34.889 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:01:34.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:01:34.891 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:34.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:34.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:34.896 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:35.362 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:35.403 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:35.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:35.403 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:35.404 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:35.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:35.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:35.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:01:35.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:35.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:35.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:35.406 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:01:35.406 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:01:35.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:35.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:35.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:35.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:35.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:35.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:35.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:35.633 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:35.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:35.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:35.633 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:35.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:35.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:40.642 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:40.642 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:40.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:40.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:40.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:40.649 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:40.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:40.649 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:40.651 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:40.651 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:40.651 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:40.651 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:40.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:40.652 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:40.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:40.652 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:40.654 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:40.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:40.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:40.654 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:40.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:40.654 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:40.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:40.654 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:40.655 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:40.655 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:40.656 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:40.656 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:40.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:40.656 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:40.656 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:40.656 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:01:40.658 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:01:40.658 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:40.658 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:40.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:40.663 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:41.127 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:41.181 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:41.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:41.183 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:41.184 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:41.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:41.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:41.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:01:41.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:41.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:41.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:41.190 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:01:41.190 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:01:41.591 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:41.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:41.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:41.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:41.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:42.060 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:42.532 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:42.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:42.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:42.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:42.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:42.999 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:43.466 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:43.662 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:43.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:43.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:43.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:43.932 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:44.398 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:01:44.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:44.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:44.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:44.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:44.866 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:01:45.332 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:01:45.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:45.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:45.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:45.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:45.798 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:01:46.263 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:01:46.729 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:01:47.197 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:01:47.661 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:01:48.127 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:01:48.596 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:01:49.067 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:01:49.537 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:01:49.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:49.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:49.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:49.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:49.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:49.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:49.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:49.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:49.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:49.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:49.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:49.869 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:01:49.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:49.869 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2012 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:49.870 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2012 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:49.870 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2012 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:49.870 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2012 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:49.870 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2012 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:49.870 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2012 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:01:54.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:01:54.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:01:54.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:54.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:54.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:54.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:54.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:01:54.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:54.888 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:54.888 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:01:54.888 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:01:54.894 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:01:54.894 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:01:54.895 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:54.895 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:54.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:01:54.896 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:01:54.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:01:54.896 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:01:54.899 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:01:54.900 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:01:54.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:54.900 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:54.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:01:54.900 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:01:54.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:01:54.900 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:01:54.904 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:01:54.904 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:01:54.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:54.904 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:01:54.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:01:54.904 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:01:54.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:01:54.904 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:01:54.908 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:01:54.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:01:54.909 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:01:54.909 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:01:54.909 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:01:54.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:01:54.914 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:01:55.391 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:01:55.440 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:01:55.442 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:01:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:01:55.444 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:01:55.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:01:55.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:01:55.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:01:55.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:01:55.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:01:55.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:01:55.449 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:01:55.449 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:01:55.863 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:01:55.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:55.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:55.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:55.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:56.335 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:01:56.805 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:01:56.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:56.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:56.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:56.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:57.279 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:01:57.751 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:01:57.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:57.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:57.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:57.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:58.223 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:01:58.694 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:01:58.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:58.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:58.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:58.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:01:59.167 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:01:59.640 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:01:59.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:01:59.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:01:59.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:01:59.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:00.112 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:02:00.583 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:02:01.056 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:02:01.529 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:02:02.001 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:02:02.466 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:02:02.930 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:02:03.396 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:02:03.859 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:02:04.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:02:04.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:02:04.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:04.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:04.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:04.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:04.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:04.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:04.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:04.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:04.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:04.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:04.200 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:09.208 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:09.208 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:09.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:09.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:09.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:09.208 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:09.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:09.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:09.211 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:09.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:09.211 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:09.212 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:09.212 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:09.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:09.212 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:09.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:09.212 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:09.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:09.212 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:09.213 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:09.213 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:09.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:09.213 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:09.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:09.213 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:09.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:09.213 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:09.215 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:09.215 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:09.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:09.215 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:09.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:09.215 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:09.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:09.215 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:02:09.217 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:02:09.217 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:09.217 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:09.222 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:09.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:09.733 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:09.733 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:09.733 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:09.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:09.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:02:09.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:02:09.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:02:09.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:09.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:02:09.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:02:09.735 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:02:09.735 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:02:10.157 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:10.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:10.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:10.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:10.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:10.624 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:11.095 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:11.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:11.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:11.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:11.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:11.565 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:12.036 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:02:12.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:12.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:12.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:12.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:12.506 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:02:12.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:02:12.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:02:12.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:12.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:02:12.785 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:12.830 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:12.872 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:12.908 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:12.950 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:12.972 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:02:12.987 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.024 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.065 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.107 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.146 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.188 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:13.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:13.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:13.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:13.230 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.267 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:13.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:02:13.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:02:13.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:13.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:13.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:13.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:13.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:13.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:13.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:13.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:13.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:13.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:13.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:13.316 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:18.317 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:18.317 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:18.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:18.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:18.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:18.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:18.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:18.320 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:18.320 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:18.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:18.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:18.321 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:18.322 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:18.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:18.322 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:18.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:18.322 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:18.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:18.322 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:18.323 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:18.323 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:18.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:18.323 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:18.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:18.323 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:18.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:18.323 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:18.324 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:18.324 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:18.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:18.324 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:18.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:18.324 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:18.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:18.324 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:02:18.326 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:02:18.326 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:18.326 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:18.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:18.331 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:18.796 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:18.837 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:18.838 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:18.838 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:18.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:18.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:18.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:18.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:18.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:18.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:18.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:18.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:18.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:18.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:18.891 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:18.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:23.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:23.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:23.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:23.912 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:23.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:23.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:23.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:23.916 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:23.916 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:23.917 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:23.917 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:23.919 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:23.919 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:23.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:23.919 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:23.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:23.919 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:23.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:23.919 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:23.920 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:23.920 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:23.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:23.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:23.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:23.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:23.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:23.920 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:23.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:23.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:23.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:23.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:23.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:23.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:23.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:23.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:02:23.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:02:23.924 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:23.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:23.929 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:24.395 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:24.436 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:24.436 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:24.437 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:24.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:24.858 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:24.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:24.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:24.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:24.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:25.321 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:25.784 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:25.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:25.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:25.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:25.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:26.250 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:26.717 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:02:26.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:26.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:26.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:26.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:27.184 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:02:27.651 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:02:27.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:27.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:27.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:27.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:28.118 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:02:28.585 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:02:28.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:28.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:28.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:28.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:29.051 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:02:29.514 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:02:29.980 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:02:30.449 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:02:30.915 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:02:31.380 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:02:31.846 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:02:32.311 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:02:32.774 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:02:33.237 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:02:33.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:33.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:33.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:33.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:33.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:33.449 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:33.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:33.449 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:33.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:33.449 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:33.449 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:33.449 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:38.456 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:38.456 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:38.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:38.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:38.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:38.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:38.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:38.467 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:38.467 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:38.467 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:38.467 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:38.468 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:38.468 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:38.468 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:38.469 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:38.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:38.469 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:38.469 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:38.469 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:38.471 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:38.471 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:38.471 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:38.471 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:38.471 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:38.471 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:38.471 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:38.471 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:38.473 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:38.473 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:38.473 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:38.473 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:38.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:38.473 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:38.473 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:38.473 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:02:38.475 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:02:38.475 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:38.475 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:38.480 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:38.959 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:38.998 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:39.000 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:39.002 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:39.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:39.431 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:39.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:39.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:39.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:39.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:39.901 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:40.375 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:40.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:40.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:40.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:40.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:40.848 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:41.319 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:02:41.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:41.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:41.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:41.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:41.794 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:02:42.266 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:02:42.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:42.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:42.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:42.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:42.738 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:02:43.211 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:02:43.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:43.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:43.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:43.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:43.684 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:02:44.156 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:02:44.629 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:02:45.102 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:02:45.574 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:02:46.047 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:02:46.520 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:02:46.992 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:02:47.465 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:02:47.938 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:02:48.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:48.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:48.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:48.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:48.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:48.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:48.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:48.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:48.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:48.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:48.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:48.023 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:02:48.023 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2060 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:48.023 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2060 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:48.023 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2060 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:48.023 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2060 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:02:53.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:53.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:53.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:53.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:53.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:53.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:53.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:53.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:53.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:53.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:02:53.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:02:53.033 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:02:53.034 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:02:53.034 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:53.034 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:53.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:53.034 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:02:53.034 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:02:53.034 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:02:53.035 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:02:53.035 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:02:53.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:53.035 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:53.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:53.035 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:02:53.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:02:53.035 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:02:53.036 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:02:53.036 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:02:53.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:53.036 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:02:53.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:53.036 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:02:53.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:02:53.036 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.038 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:02:53.038 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:02:53.038 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:02:53.038 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:02:53.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:02:53.043 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:02:53.521 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:02:53.562 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:02:53.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:53.565 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:02:53.567 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:02:53.993 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:02:54.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:54.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:54.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:54.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:54.467 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:02:54.939 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:02:55.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:55.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:55.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:55.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:55.411 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:02:55.885 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:02:56.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:56.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:56.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:56.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:56.357 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:02:56.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:02:56.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:02:56.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:02:56.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:02:56.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:02:56.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:02:56.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:02:56.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:02:56.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:02:56.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:02:56.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:02:56.594 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:01.600 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:01.601 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:01.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:01.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:01.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:01.601 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:01.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:01.608 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:01.608 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:01.608 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:01.608 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:01.612 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:01.612 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:01.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:01.613 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:01.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:01.614 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:01.614 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:01.614 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:01.616 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:01.617 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:01.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:01.617 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:01.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:01.618 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:01.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:01.618 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:01.620 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:01.620 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:01.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:01.621 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:01.621 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:01.621 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:01.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:01.621 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:01.624 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:01.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:01.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:01.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:01.624 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:01.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:01.625 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:01.625 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:01.625 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:01.630 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:02.109 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:02.151 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:02.154 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:02.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:02.156 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:02.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:02.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:02.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:03:02.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:02.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:02.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:02.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:03:02.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:03:02.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:02.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:02.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:02.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:02.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:02.581 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:02.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:02.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:02.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:02.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:02.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:02.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:02.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:02.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:02.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:02.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:02.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:02.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:02.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:02.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:02.604 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:02.604 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:07.609 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:07.609 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:07.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:07.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:07.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:07.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:07.622 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:07.622 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:07.622 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:07.623 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:07.623 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:07.625 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:07.625 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:07.625 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:07.625 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:07.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:07.625 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:07.626 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:07.626 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:07.627 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:07.627 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:07.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:07.627 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:07.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:07.627 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:07.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:07.627 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:07.628 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:07.628 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:07.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:07.629 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:07.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:07.629 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:07.629 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:07.629 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:07.630 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:07.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:07.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:07.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:07.630 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:07.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:07.631 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:07.631 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:07.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:07.635 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:08.115 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:08.151 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:08.151 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:08.151 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:08.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:08.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:08.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:08.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:08.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:08.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:08.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:08.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:08.174 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:08.174 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:08.174 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:08.174 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:08.174 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:08.174 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:08.174 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:08.174 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:08.174 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:08.174 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:13.176 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:13.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:13.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:13.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:13.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:13.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:13.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:13.183 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:13.183 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:13.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:13.184 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:13.186 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:13.186 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:13.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:13.187 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:13.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:13.188 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:13.188 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:13.188 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:13.190 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:13.191 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:13.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:13.191 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:13.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:13.192 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:13.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:13.192 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:13.194 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:13.194 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:13.194 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:13.194 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:13.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:13.195 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:13.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:13.195 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.198 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:13.198 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:13.198 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:13.199 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:13.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:13.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:13.203 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:13.681 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:13.722 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:13.723 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:13.724 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:13.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:14.153 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:14.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:14.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:14.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:14.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:14.626 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:15.099 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:15.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:15.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:15.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:15.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:15.571 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:15.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:15.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:15.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:15.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:15.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:15.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:15.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:15.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:15.745 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:15.745 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:15.745 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:20.751 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:20.751 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:20.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:20.752 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:20.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:20.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:20.757 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:20.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:20.758 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:20.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:20.759 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:20.762 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:20.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:20.763 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:20.763 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:20.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:20.763 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:20.764 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:20.764 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:20.765 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:20.765 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:20.766 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:20.766 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:20.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:20.766 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:20.766 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:20.766 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:20.768 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:20.768 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:20.768 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:20.768 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:20.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:20.768 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:20.768 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:20.768 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:20.771 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:20.771 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:20.771 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:20.776 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:21.254 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:21.297 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:21.299 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:21.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:21.302 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:21.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:21.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:21.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:03:21.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:21.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:21.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:21.306 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:03:21.306 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:03:21.726 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:21.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:21.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:21.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:21.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:22.197 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:22.670 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:22.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:22.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:22.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:22.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:23.143 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:23.615 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:23.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:23.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:23.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:23.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:24.086 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:24.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:24.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:24.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:24.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:24.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:24.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:24.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:24.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:24.106 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:24.106 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:24.106 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:24.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:24.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:29.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:29.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:29.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:29.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:29.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:29.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:29.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:29.120 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:29.121 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:29.121 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:29.121 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:29.125 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:29.125 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:29.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:29.125 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:29.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:29.126 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:29.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:29.126 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:29.128 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:29.128 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:29.128 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:29.128 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:29.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:29.128 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:29.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:29.129 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:29.131 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:29.131 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:29.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:29.131 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:29.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:29.131 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:29.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:29.131 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.134 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:29.134 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:29.134 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:29.134 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:29.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:29.139 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:29.617 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:29.658 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:29.660 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:29.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:29.662 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:29.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:29.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:29.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:03:29.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:29.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:29.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:29.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:03:29.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:03:30.088 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:30.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:30.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:30.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:30.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:30.560 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:31.031 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:31.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:31.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:31.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:31.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:31.504 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:31.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:31.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:31.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:31.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:31.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:31.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:31.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:31.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:31.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:31.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:31.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:31.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:31.760 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:36.767 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:36.767 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:36.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:36.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:36.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:36.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:36.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:36.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:36.775 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:36.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:36.776 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:36.778 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:36.778 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:36.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:36.779 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:36.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:36.779 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:36.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:36.779 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:36.782 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:36.782 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:36.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:36.782 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:36.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:36.782 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:36.783 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:36.783 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:36.786 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:36.786 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:36.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:36.786 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:36.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:36.786 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:36.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:36.786 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:36.791 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:36.791 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:36.792 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:36.792 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:36.792 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:36.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:36.797 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:37.275 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:37.324 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:37.325 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:37.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:37.326 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:37.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:37.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:37.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:03:37.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:37.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:37.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:37.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:03:37.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:03:37.748 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:37.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:37.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:37.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:37.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:38.219 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:38.689 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:38.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:38.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:38.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:38.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:39.163 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:39.635 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:39.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:39.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:39.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:39.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:40.107 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:40.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:40.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:40.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:40.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:40.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:40.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:40.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:40.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:40.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:40.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:40.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:40.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:40.136 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:45.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:45.142 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:45.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:45.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:45.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:45.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:45.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:45.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:45.146 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:45.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:45.146 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:45.147 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:45.147 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:45.147 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:45.147 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:45.147 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:45.147 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:45.147 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:45.147 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:45.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:45.148 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:45.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:45.148 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:45.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:45.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:45.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:45.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:45.149 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:45.149 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:45.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:45.149 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:45.149 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:45.149 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:45.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:45.149 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:45.151 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:45.152 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:45.152 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:45.152 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:45.156 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:45.634 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:45.679 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:45.681 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:45.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:45.683 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:45.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:45.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:45.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:03:45.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:45.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:45.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:45.693 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:03:45.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:03:46.106 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:46.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:46.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:46.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:46.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:46.577 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:47.051 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:47.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:47.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:47.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:47.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:47.523 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:47.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:47.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:47.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:47.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:47.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:47.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:47.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:47.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:47.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:47.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:47.789 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:47.789 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:47.789 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:47.789 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:47.789 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:47.789 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:47.789 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:47.789 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:47.789 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:52.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:52.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:52.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:52.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:52.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:52.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:52.804 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:52.806 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:52.806 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:52.806 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:03:52.807 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:03:52.812 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:03:52.812 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:03:52.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:52.813 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:52.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:52.814 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:03:52.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:03:52.814 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:03:52.817 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:03:52.817 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:03:52.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:52.817 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:52.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:52.818 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:03:52.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:03:52.819 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:03:52.820 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:03:52.821 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:03:52.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:52.821 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:03:52.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:52.821 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:03:52.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:03:52.821 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:03:52.825 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:03:52.825 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:03:52.825 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:03:52.826 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:03:52.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:03:52.830 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:03:53.308 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:03:53.354 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:03:53.357 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:03:53.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:03:53.359 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:03:53.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:53.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:53.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:03:53.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:03:53.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:03:53.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:03:53.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:03:53.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:03:53.780 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:03:53.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:53.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:53.829 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:53.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:54.252 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:03:54.725 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:03:54.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:54.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:54.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:54.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:55.197 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:03:55.669 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:03:55.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:55.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:55.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:55.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:56.140 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:03:56.611 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:03:56.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:56.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:56.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:56.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:57.084 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:03:57.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:03:57.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:03:57.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:03:57.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:03:57.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:03:57.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:03:57.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:03:57.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:03:57.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:03:57.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:03:57.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:03:57.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:03:57.113 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:03:57.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=927 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=927 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=927 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=927 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:03:57.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=927 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:02.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:02.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:02.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:02.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:02.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:02.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:02.118 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:02.118 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:02.118 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:02.118 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:02.119 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:02.119 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:02.119 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:02.120 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:02.120 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:02.120 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:02.120 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:02.120 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:02.120 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:02.121 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:02.121 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:02.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:02.121 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:02.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:02.121 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:02.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:02.121 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:02.122 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:02.122 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:02.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:02.122 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:02.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:02.122 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:02.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:02.122 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:02.124 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:02.124 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:02.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:02.129 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:02.607 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:02.650 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:02.653 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:02.655 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:02.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:02.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:02.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:04:02.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:04:02.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:04:02.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:04:02.665 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:04:02.665 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:04:02.665 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:04:03.078 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:04:03.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:03.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:03.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:03.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:03.550 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:04:04.021 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:04:04.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:04.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:04.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:04.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:04.494 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:04:04.966 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:04:05.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:05.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:05.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:05.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:05.438 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:04:05.909 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:04:06.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:06.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:06.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:06.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:06.383 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:04:06.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:06.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:04:06.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:06.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:06.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:06.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:06.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:06.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:06.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:06.637 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:06.637 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:06.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:06.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:06.638 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=976 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:06.638 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=976 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:06.638 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=976 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:06.638 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=976 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:06.638 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=976 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:06.638 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=976 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:11.645 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:11.645 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:11.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:11.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:11.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:11.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:11.655 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:11.656 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:11.657 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:11.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:11.657 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:11.660 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:11.660 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:11.660 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:11.661 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:11.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:11.661 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:11.661 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:11.661 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:11.663 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:11.663 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:11.664 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:11.664 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:11.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:11.664 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:11.664 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:11.664 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:11.666 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:11.666 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:11.666 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:11.666 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:11.666 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:11.666 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:11.666 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:11.666 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:11.668 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:11.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:11.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:11.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:11.668 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:11.669 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:11.669 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:11.669 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:11.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:11.673 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:12.152 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:12.195 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:12.197 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:12.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:12.200 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:12.624 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:04:12.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:12.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:12.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:12.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:13.098 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:04:13.570 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:04:13.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:13.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:13.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:13.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:14.042 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:04:14.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:14.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:14.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:14.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:14.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:14.218 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:14.218 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:14.218 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:14.218 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:14.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:14.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:19.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:19.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:19.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:19.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:19.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:19.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:19.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:19.238 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:19.238 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:19.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:19.239 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:19.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:19.244 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:19.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:19.244 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:19.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:19.245 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:19.246 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:19.246 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:19.248 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:19.248 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:19.248 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:19.248 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:19.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:19.249 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:19.249 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:19.250 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:19.251 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:19.251 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:19.251 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:19.252 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:19.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:19.252 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:19.252 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:19.252 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:19.255 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:19.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:19.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:19.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:19.255 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:19.256 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:19.256 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:19.256 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:19.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.261 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:19.739 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:19.785 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:19.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:19.789 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:19.792 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:19.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:19.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:04:19.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:04:19.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:19.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:20.211 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:04:20.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:20.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:20.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:20.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:20.682 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:04:21.152 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:04:21.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:21.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:21.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:21.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:21.624 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:04:22.095 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:04:22.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:22.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:22.266 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:22.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:22.566 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:04:22.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:22.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:22.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:22.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:22.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:22.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:22.858 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:22.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:22.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:22.858 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:22.858 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:22.858 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=778 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=778 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=778 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:22.858 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=779 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:27.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:27.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:27.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:27.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:27.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:27.862 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:27.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:27.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:27.872 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:27.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:27.873 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:27.876 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:27.876 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:27.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:27.877 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:27.877 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:27.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:27.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:27.877 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:27.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:27.883 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:27.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:27.883 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:27.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:27.883 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:27.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:27.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:27.887 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:27.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:27.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:27.888 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:27.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:27.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:27.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:27.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:27.894 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:27.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:27.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:27.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:27.894 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:27.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.895 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:27.895 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:27.895 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:27.895 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:27.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:27.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:27.900 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:28.379 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:28.424 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:28.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:28.428 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:28.430 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:28.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:28.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:04:28.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:04:28.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:28.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:28.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:28.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:28.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:28.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:28.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:28.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:28.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:28.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:28.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:28.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:28.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:28.478 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:28.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:28.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:28.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:28.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:28.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:28.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:28.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:33.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:33.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:33.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:33.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:33.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:33.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:33.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:33.488 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:33.488 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:33.488 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:33.488 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:33.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:33.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:33.490 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:33.490 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:33.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:33.491 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:33.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:33.491 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:33.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:33.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:33.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:33.493 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:33.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:33.493 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:33.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:33.493 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:33.495 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:33.495 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:33.495 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:33.495 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:33.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:33.496 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:33.496 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:33.496 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:33.498 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:33.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:33.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:33.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:33.499 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:33.499 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:33.499 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:33.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:33.504 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:33.981 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:34.031 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:34.034 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:34.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:34.036 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:34.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:34.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:04:34.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:04:34.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:34.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:34.453 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:04:34.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:34.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:34.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:34.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:34.927 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:04:35.399 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:04:35.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:35.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:35.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:35.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:35.871 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:04:36.344 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:04:36.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:36.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:36.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:36.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:36.817 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:04:37.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:37.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:37.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:37.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:37.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:37.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:37.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:37.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:37.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:37.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:37.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:37.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:37.094 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:37.094 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=775 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:37.094 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=775 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:37.094 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=775 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:37.095 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=775 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:42.096 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:42.096 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:42.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:42.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:42.097 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:42.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:42.105 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:42.106 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:42.106 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:42.106 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:42.106 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:42.109 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:42.109 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:42.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:42.110 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:42.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:42.110 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:42.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:42.111 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:42.112 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:42.113 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:42.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:42.113 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:42.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:42.113 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:42.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:42.113 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:42.115 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:42.115 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:42.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:42.115 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:42.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:42.115 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:42.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:42.115 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.118 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:42.118 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:42.118 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:42.119 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:42.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.123 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:42.602 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:42.642 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:42.643 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:42.645 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:42.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:04:42.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:04:42.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:04:42.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:42.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:42.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:42.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:42.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:42.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:42.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:42.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:42.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:42.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:42.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:42.691 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:42.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:42.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:42.691 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:42.691 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:42.691 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:42.692 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:42.692 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:42.692 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:47.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:47.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:47.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:47.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:47.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:47.700 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:47.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:47.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:47.710 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:47.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:47.710 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:47.711 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:47.712 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:47.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:47.712 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:47.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:47.712 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:47.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:47.712 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:47.713 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:47.713 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:47.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:47.713 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:47.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:47.713 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:47.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:47.713 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:47.714 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:47.714 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:47.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:47.714 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:47.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:47.714 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:47.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:47.715 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:47.716 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:47.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:47.717 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:47.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:47.721 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:48.200 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:48.231 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:48.232 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:48.232 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:48.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:48.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:48.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:48.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:48.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:48.244 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:48.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:48.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:48.244 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:48.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:48.244 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:48.244 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:53.250 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:53.250 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:53.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:53.250 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:53.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:53.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:53.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:53.256 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:53.256 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:53.256 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:53.256 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:53.259 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:53.259 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:53.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:53.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:53.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:53.260 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:53.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:53.260 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:53.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:53.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:53.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:53.262 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:53.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:53.263 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:53.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:53.263 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:53.265 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:53.265 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:53.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:53.265 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:53.266 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:53.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:53.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:53.266 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:53.269 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:53.269 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:53.269 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:53.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:53.274 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:53.752 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:53.795 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:53.798 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:53.800 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:53.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:53.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:53.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:53.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:53.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:53.813 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:53.813 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:53.813 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:53.813 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:53.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:53.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:53.813 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:53.813 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:53.813 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:53.813 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:53.813 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:53.813 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:53.813 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:58.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:58.820 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:58.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:58.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:58.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:58.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:58.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:58.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:58.833 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:58.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:04:58.833 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:04:58.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:04:58.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:04:58.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:58.836 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:58.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:58.836 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:04:58.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:04:58.836 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:04:58.838 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:04:58.838 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:04:58.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:58.838 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:58.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:58.838 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:04:58.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:04:58.838 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:04:58.840 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:04:58.840 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:04:58.840 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:58.840 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:04:58.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:58.840 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:04:58.840 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:04:58.840 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:04:58.842 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:04:58.842 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:04:58.842 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:04:58.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:04:58.847 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:04:59.325 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:04:59.364 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:04:59.365 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:04:59.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:04:59.367 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:04:59.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:04:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:04:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:04:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:04:59.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:04:59.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:04:59.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:04:59.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:04:59.383 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:04:59.383 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:04:59.383 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:04:59.383 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:59.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:59.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:59.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:59.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:04:59.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.385 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:04.385 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:04.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:04.393 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:04.394 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:04.395 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:04.395 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:04.395 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:04.398 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:04.398 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:04.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:04.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:04.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:04.400 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:04.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:04.400 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:04.402 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:04.402 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:04.402 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:04.402 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:04.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:04.402 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:04.402 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:04.402 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:04.404 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:04.404 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:04.405 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:04.405 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:04.405 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:04.405 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:04.405 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:04.405 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:04.408 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:04.408 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:04.408 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:04.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:04.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:04.413 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:04.891 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:04.938 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:04.940 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:04.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:04.943 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:04.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:04.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:04.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:04.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:04.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:04.960 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:04.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:04.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:04.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:04.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:04.961 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:04.961 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.961 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:04.962 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:09.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:09.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:09.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:09.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:09.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:09.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:09.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:09.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:09.966 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:09.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:09.967 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:09.967 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:09.967 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:09.968 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:09.968 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:09.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:09.968 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:09.968 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:09.968 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:09.969 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:09.969 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:09.969 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:09.969 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:09.969 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:09.969 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:09.969 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:09.969 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:09.970 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:09.970 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:09.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:09.970 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:09.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:09.970 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:09.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:09.970 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:09.972 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:09.972 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:09.972 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:09.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:09.977 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:10.455 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:10.496 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:10.498 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:10.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:10.499 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:10.927 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:05:10.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:10.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:10.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:10.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:11.398 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:05:11.874 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:05:11.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:11.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:11.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:11.978 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:12.345 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:05:12.821 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:05:12.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:12.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:12.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:12.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:13.293 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:05:13.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:13.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:05:13.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:05:13.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:05:13.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:05:13.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:05:13.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:05:13.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:05:13.769 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:05:13.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:13.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:13.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:13.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:14.241 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:05:14.711 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:05:14.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:14.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:14.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:14.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:15.182 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:05:15.656 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:05:15.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:15.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:05:15.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:15.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:15.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:15.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:15.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:15.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:15.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:15.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:15.785 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:15.785 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:15.785 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1254 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:15.785 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1254 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:20.789 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:20.789 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:20.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:20.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:20.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:20.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:20.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:20.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:20.793 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:20.793 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:20.794 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:20.794 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:20.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:20.794 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:20.794 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:20.794 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:20.795 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:20.795 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:20.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:20.795 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:20.795 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:20.795 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:20.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:20.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:20.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:20.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:20.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:20.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:20.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:20.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:20.799 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:20.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:20.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:20.803 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:21.281 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:21.323 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:21.326 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:21.328 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:21.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:21.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:21.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:05:21.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:05:21.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:21.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:21.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:21.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:21.387 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:21.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:21.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:21.387 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:21.387 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:21.387 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:21.387 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:26.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:26.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:26.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:26.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:26.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:26.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:26.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:26.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:26.402 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:26.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:26.402 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:26.407 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:26.407 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:26.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:26.407 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:26.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:26.408 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:26.408 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:26.408 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:26.412 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:26.412 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:26.413 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:26.413 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:26.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:26.413 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:26.413 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:26.413 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:26.417 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:26.417 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:26.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:26.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:26.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:26.417 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:26.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:26.418 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:26.423 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:26.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:26.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:26.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:26.423 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.424 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:26.424 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:26.424 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:26.424 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:26.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:26.429 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:26.907 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:26.958 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:26.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:26.961 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:26.964 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:26.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:26.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:05:26.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:05:27.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:27.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:27.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:27.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:27.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:27.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:27.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:27.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:27.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:27.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:27.014 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:27.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:27.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:27.014 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:32.015 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:32.015 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:32.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:32.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:32.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:32.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:32.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:32.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:32.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:32.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:32.026 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:32.031 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:32.031 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:32.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:32.031 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:32.031 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:32.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:32.032 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:32.032 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:32.036 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:32.036 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:32.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:32.036 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:32.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:32.037 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:32.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:32.037 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:32.039 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:32.040 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:32.040 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:32.040 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:32.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:32.040 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:32.040 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:32.040 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:32.044 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:32.044 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:32.044 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.049 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:32.527 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:32.570 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:32.572 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:32.575 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:32.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:32.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:32.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:05:32.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:05:32.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:32.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:32.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:32.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:32.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:32.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:32.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:32.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:32.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:32.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:32.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:32.614 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:32.614 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:32.614 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:32.614 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:32.615 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:32.615 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:32.615 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:32.615 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:32.615 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:37.618 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:37.618 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:37.618 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:37.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:37.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:37.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:37.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:37.628 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:37.628 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:37.628 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:37.628 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:37.631 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:37.631 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:37.632 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:37.632 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:37.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:37.632 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:37.633 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:37.633 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:37.634 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:37.634 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:37.634 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:37.634 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:37.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:37.634 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:37.635 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:37.635 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:37.636 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:37.636 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:37.637 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:37.637 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:37.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:37.637 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:37.637 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:37.637 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:37.639 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:37.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:37.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:37.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:37.639 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:37.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:37.640 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:37.640 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:37.640 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:37.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:37.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:37.644 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:38.122 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:38.162 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:38.163 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:38.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.165 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:38.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:38.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:05:38.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:05:38.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:38.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:38.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:38.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:38.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:38.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:38.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:38.222 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:38.222 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:38.222 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:38.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:38.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:38.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:38.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:38.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:38.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:38.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:38.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:38.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:43.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:43.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:43.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:43.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:43.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:43.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:43.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:43.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:43.227 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:43.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:43.227 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:43.228 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:43.229 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:43.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:43.229 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:43.229 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:43.229 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:43.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:43.229 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:43.232 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:43.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:43.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:43.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:43.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:43.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:43.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:43.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:43.235 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:43.235 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:43.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:43.236 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:43.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:43.236 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:43.236 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:43.236 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:43.239 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:43.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:43.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:43.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:43.240 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:43.240 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:43.240 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:43.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:43.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:43.245 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:43.723 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:43.772 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:43.775 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:43.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:43.777 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:43.779 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:43.779 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 200
2026-01-29 02:05:43.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:44.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:44.198 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:05:44.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:44.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:44.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:44.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:44.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:44.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:44.672 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:05:45.141 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:05:45.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:45.419 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:45.419 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 0
2026-01-29 02:05:45.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:45.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:45.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:45.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:45.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:45.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:45.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:45.429 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:45.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=473 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:45.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:45.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:45.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:45.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:45.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:50.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:50.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:50.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:50.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:50.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:50.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:50.441 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:50.441 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:50.442 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:50.442 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:50.442 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:50.443 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:50.444 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:50.444 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:50.444 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:50.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:50.445 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:50.445 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:50.445 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:50.447 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:50.447 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:50.447 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:50.447 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:50.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:50.448 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:50.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:50.448 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:50.451 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:50.451 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:50.451 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:50.451 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:50.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:50.451 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:50.452 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:50.452 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:50.458 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:50.458 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:50.458 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:50.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:50.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:50.463 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:50.941 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:50.991 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:50.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:50.995 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:50.997 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:50.999 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:50.999 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 200
2026-01-29 02:05:51.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:51.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:51.414 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:05:51.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:51.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:51.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:51.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:51.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:51.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:51.888 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:05:52.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.362 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:05:52.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.633 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 02:05:52.634 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 0
2026-01-29 02:05:52.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 02:05:52.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:52.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:52.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:52.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:52.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:52.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:52.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:52.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:52.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:52.641 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:52.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:52.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:52.641 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:52.641 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:52.641 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:52.641 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:57.648 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:57.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:57.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:57.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:57.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:57.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:57.657 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:57.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:57.660 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:57.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:05:57.660 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:05:57.666 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:05:57.666 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:05:57.667 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:57.667 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:57.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:57.667 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:05:57.668 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:05:57.668 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:05:57.671 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:05:57.671 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:05:57.671 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:57.671 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:57.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:57.672 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:05:57.672 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:05:57.672 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:05:57.676 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:05:57.677 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:05:57.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:57.677 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:05:57.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:57.677 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:05:57.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:05:57.677 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:05:57.682 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:05:57.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:05:57.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:05:57.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:05:57.682 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.683 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:05:57.683 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:05:57.683 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:05:57.683 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:05:57.688 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:05:58.166 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:05:58.215 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:05:58.217 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:05:58.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:58.219 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:05:58.243 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:05:58.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:05:58.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:05:58.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:58.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:05:58.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:05:58.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:05:58.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:05:58.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:05:58.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:05:58.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:05:58.262 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:05:58.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:05:58.262 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:05:58.262 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:05:58.262 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:05:58.262 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:58.262 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:58.262 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:05:58.262 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:03.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:03.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:06:03.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:03.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:03.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:03.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:03.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:03.275 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:03.275 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:03.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:03.276 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:06:03.280 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:06:03.280 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:06:03.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:03.280 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:03.280 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:03.280 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:06:03.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:03.281 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:06:03.285 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:06:03.285 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:06:03.285 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:03.285 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:03.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:03.286 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:06:03.286 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:03.286 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:06:03.290 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:06:03.290 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:06:03.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:03.290 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:03.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:03.290 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:06:03.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:03.290 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:06:03.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:06:03.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:06:03.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:06:03.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:06:03.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.297 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:06:03.297 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:06:03.297 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:06:03.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:03.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:03.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:03.302 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:06:03.781 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:06:03.825 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:06:03.827 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:06:03.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:03.829 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:06:03.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:03.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:03.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:03.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:03.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:03.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:03.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:03.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:03.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:03.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:03.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:03.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:06:03.879 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:03.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:03.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:03.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:03.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:03.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:03.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:03.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:03.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:03.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:08.884 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:08.884 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:06:08.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:08.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:08.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:08.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:08.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:08.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:08.893 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:08.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:08.893 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:06:08.897 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:06:08.897 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:06:08.897 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:08.897 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:08.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:08.897 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:06:08.898 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:08.898 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:06:08.901 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:06:08.902 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:06:08.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:08.902 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:08.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:08.902 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:06:08.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:08.902 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:06:08.906 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:06:08.906 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:06:08.906 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:08.906 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:08.906 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:08.907 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:06:08.907 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:08.907 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:06:08.912 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:06:08.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:06:08.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:06:08.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:06:08.912 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.913 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:06:08.913 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:06:08.913 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:06:08.913 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:08.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:08.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:08.918 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:06:09.397 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:06:09.448 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:06:09.450 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:06:09.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:09.453 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:06:09.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:09.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:09.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:09.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:09.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:09.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:09.483 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:09.483 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:09.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:09.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:09.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:09.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:09.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:09.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:09.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:09.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:09.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:09.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:09.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:09.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:09.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:09.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:09.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:09.563 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:09.563 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:09.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:09.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:09.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:09.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:09.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:09.867 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:06:09.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:09.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:09.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:09.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:10.339 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:06:10.812 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:06:10.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:10.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:10.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:10.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:11.285 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:06:11.758 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:06:11.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:11.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:11.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:11.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:12.230 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:06:12.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:12.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:12.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:12.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:12.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:12.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:12.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:12.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:12.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:12.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:12.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:12.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:12.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:12.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:12.701 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:06:12.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:12.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:12.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:12.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:12.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:12.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:12.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:12.723 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:12.723 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:12.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:12.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:12.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:12.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:12.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:12.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:12.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:12.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:13.172 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:06:13.643 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:06:13.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:13.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:13.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:13.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:14.116 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:06:14.589 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:06:15.061 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:06:15.534 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:06:15.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:15.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:15.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:15.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:15.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:15.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:15.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:15.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:15.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:15.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:15.776 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:15.776 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:15.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:15.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:15.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:15.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:15.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:16.007 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:06:16.479 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:06:16.953 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:06:17.426 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:06:17.898 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:06:18.372 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:06:18.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:18.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:18.844 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:06:18.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:18.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:18.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:18.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:18.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:18.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:18.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:18.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:18.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:18.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:18.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:18.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:18.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:18.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:18.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:18.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:18.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:18.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:18.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:19.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:19.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:19.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:19.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:19.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:19.316 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:06:19.787 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:06:19.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:19.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:19.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:19.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:20.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:20.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:20.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:20.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:20.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:20.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:20.015 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:20.015 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:20.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:20.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:20.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:20.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:20.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:20.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:20.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:20.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:20.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:20.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:20.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:20.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:20.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:20.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:20.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:20.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:20.114 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:20.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:20.166 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:20.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:20.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:20.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:20.258 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:06:20.731 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:06:21.204 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:06:21.676 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:06:22.147 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:06:22.620 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:06:23.092 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:06:23.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:23.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:23.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:23.192 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:23.192 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:23.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:23.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:23.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:23.194 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:23.194 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:23.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:23.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:23.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:23.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:23.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:23.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:23.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:23.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:23.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:23.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:23.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:23.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:23.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:23.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:23.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:23.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:23.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:23.563 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:06:24.035 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:06:24.507 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:06:24.979 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:06:25.452 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:06:25.924 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:06:26.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:26.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:26.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:26.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:26.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:26.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:26.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:26.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:26.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:26.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:26.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:26.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:26.396 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:06:26.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:26.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:26.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:26.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:26.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:26.867 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:06:27.338 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:06:27.809 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:06:28.280 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:06:28.753 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:06:29.226 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:06:29.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:29.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:29.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:29.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:29.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:29.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:29.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:29.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:29.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:29.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:29.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:29.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:29.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:29.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:29.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:29.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:29.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:29.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:29.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:29.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:29.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:29.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:29.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:29.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:29.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:29.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:29.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:29.698 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:06:30.169 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:06:30.642 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:06:30.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:30.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:30.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:30.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:30.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:30.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:30.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:30.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:30.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:30.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:30.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:30.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:30.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:30.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:30.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:30.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:30.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:31.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:31.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:31.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:31.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:31.115 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:06:31.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:31.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:31.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:31.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:31.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:31.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:31.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:31.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:31.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:31.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:31.169 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:31.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:31.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:31.587 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:06:32.058 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:06:32.528 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:06:32.999 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:06:33.473 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:06:33.945 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:06:34.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:34.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:34.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:34.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.197 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:34.197 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:34.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:34.416 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:06:34.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:34.430 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:34.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:34.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.431 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:34.431 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:34.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:34.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:34.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:34.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:34.888 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:06:35.359 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:06:35.829 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:06:36.300 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:06:36.773 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:06:37.246 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:06:37.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:37.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:37.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:37.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:37.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:37.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:37.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:37.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:37.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:37.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:37.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:37.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:37.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:37.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:37.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:37.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:37.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:37.718 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:06:38.189 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:06:38.662 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:06:39.135 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:06:39.607 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:06:40.078 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:06:40.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:40.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:40.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:40.549 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:06:40.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:40.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:40.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:40.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:40.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:40.563 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:40.563 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:40.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:40.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:40.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:40.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:40.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:40.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:40.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:40.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:40.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:40.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:40.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:40.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:40.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:40.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:40.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:40.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:40.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:40.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.019 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:06:41.490 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:06:41.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:41.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:41.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:41.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:41.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:41.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:41.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:41.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:41.549 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:41.549 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:41.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:41.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:41.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:41.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:41.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:41.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:41.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:41.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:41.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:41.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:41.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:41.669 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:41.669 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:41.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:41.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:41.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:41.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:41.961 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:06:42.434 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:06:42.907 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:06:43.378 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:06:43.850 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:06:44.323 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:06:44.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:44.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:44.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:44.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:44.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:44.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:44.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:44.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:44.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:44.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:44.696 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:44.696 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:44.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:44.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:44.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:44.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:44.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:44.795 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:06:44.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:44.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:44.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:44.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:44.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:44.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:44.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:44.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:44.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:44.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:44.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:44.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:44.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:44.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:44.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:44.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:44.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:45.267 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:06:45.738 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:06:46.212 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:06:46.684 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:06:47.156 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:06:47.627 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:06:47.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:47.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:47.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:47.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:47.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:47.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:47.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:47.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:47.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:47.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:47.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:47.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:48.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:48.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:48.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:48.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:48.100 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:06:48.573 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:06:49.045 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:06:49.516 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:06:49.987 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:06:50.460 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:06:50.932 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:06:51.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:51.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:51.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:51.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:51.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:51.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:51.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:51.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:51.080 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:51.080 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:51.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:51.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:51.124 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:51.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:51.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:51.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:51.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:51.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:51.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:51.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:51.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:51.345 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:51.345 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:51.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:51.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:51.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:51.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.403 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:06:51.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:51.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:51.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:51.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:51.875 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:06:51.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:51.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:51.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:51.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:51.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:51.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:51.885 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:06:51.885 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:51.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:51.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:51.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:51.885 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9286 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:51.885 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9286 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:51.886 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9286 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:51.886 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9286 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:51.886 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9286 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:51.886 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9286 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:56.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:56.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:06:56.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:56.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:56.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:56.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:56.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:56.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:56.902 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:56.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:06:56.902 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:06:56.904 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:06:56.904 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:06:56.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:56.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:56.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:56.905 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:06:56.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:06:56.905 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:06:56.906 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:06:56.906 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:06:56.906 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:56.906 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:56.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:56.907 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:06:56.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:06:56.907 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:06:56.908 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:06:56.908 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:06:56.908 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:56.908 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:06:56.908 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:56.908 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:06:56.908 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:06:56.908 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.910 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:06:56.910 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:06:56.910 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:06:56.910 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:06:56.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:06:56.915 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:06:57.393 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:06:57.437 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:06:57.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:57.442 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:06:57.444 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:06:57.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:57.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:57.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:57.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:57.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:57.473 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:57.473 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:57.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:57.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:57.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:57.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:57.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:57.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:57.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:57.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:57.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:57.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:57.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:57.574 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:57.574 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:57.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:57.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:57.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:57.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:57.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:57.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:57.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:57.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:57.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:57.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:57.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:57.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:57.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:57.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:57.780 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:57.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:57.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:57.865 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:06:57.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:57.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:57.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:57.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:58.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:58.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:58.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:58.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:58.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:58.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:58.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:06:58.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:58.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:58.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:58.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:06:58.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:06:58.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:58.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:06:58.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:06:58.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:58.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:58.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:06:58.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:06:58.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:06:58.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:06:58.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:06:58.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:06:58.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:06:58.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:06:58.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:06:58.204 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:06:58.204 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:06:58.204 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:06:58.204 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:06:58.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:06:58.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:06:58.205 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=279 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:58.205 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=279 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:58.205 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=279 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:58.205 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=279 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:58.205 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=279 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:06:58.205 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=279 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:03.205 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:03.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:03.206 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:03.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:03.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:03.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:03.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:03.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:03.215 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:03.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:03.215 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:03.220 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:03.220 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:03.221 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:03.221 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:03.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:03.222 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:03.222 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:03.223 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:03.226 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:03.226 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:03.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:03.227 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:03.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:03.228 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:03.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:03.228 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:03.232 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:03.233 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:03.233 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:03.233 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:03.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:03.234 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:03.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:03.234 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:07:03.242 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:07:03.242 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:03.242 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:03.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:03.247 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:03.724 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:03.783 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:03.786 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:03.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:03.790 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:03.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:03.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:03.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:03.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:03.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:03.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:03.812 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:03.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:03.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:03.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:03.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:03.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:03.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.196 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:04.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:04.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:04.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:04.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:04.668 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:04.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:04.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:04.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:04.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:04.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:04.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:04.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:04.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:04.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:04.706 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:04.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:04.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:04.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:04.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:04.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.138 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:05.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:05.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:05.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:05.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:05.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:05.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:05.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:05.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:05.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:05.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:05.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:05.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:05.429 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:05.429 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:05.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:05.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:05.475 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:05.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:05.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:05.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:05.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:05.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:05.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:05.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:05.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:05.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:05.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:05.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:05.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:05.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:05.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:05.609 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:07:06.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:06.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:06.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:06.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:06.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:06.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:06.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:06.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:06.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:06.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:06.018 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:06.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:06.018 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:06.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:06.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:11.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:11.022 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:11.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:11.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:11.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:11.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:11.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:11.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:11.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:11.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:11.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:11.035 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:11.036 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:11.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:11.036 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:11.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:11.037 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:11.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:11.037 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:11.039 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:11.039 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:11.039 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:11.039 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:11.039 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:11.039 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:11.039 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:11.039 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:11.041 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:11.042 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:11.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:11.042 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:11.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:11.042 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:11.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:11.042 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:07:11.045 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:07:11.045 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:11.045 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:11.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:11.050 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:11.528 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:11.568 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:11.570 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:11.571 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:11.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:11.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:11.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:11.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:11.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:11.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:11.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:11.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:11.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:11.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:11.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:11.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:11.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:11.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:11.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:11.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:11.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:11.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:11.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:11.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:11.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:11.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:11.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:11.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:11.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:11.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:11.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:11.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:11.864 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:11.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:11.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:11.999 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:12.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:12.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:12.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:12.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:12.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:12.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:12.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:12.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:12.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:12.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:12.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:12.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:12.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:12.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:12.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:12.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:12.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:12.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:12.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:12.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:12.471 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:12.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:12.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:12.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:12.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:12.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:12.482 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:12.482 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:12.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:12.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:12.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:12.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:12.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:12.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:12.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:12.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:12.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:12.869 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:12.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:17.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:17.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:17.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:17.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:17.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:17.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:17.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:17.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:17.885 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:17.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:17.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:17.889 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:17.890 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:17.890 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:17.890 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:17.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:17.890 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:17.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:17.891 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:17.894 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:17.894 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:17.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:17.894 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:17.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:17.895 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:17.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:17.895 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:17.897 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:17.897 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:17.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:17.897 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:17.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:17.897 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:17.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:17.897 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.901 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:07:17.901 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:07:17.901 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:17.901 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:17.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:17.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:17.906 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:18.385 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:18.430 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:18.432 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:18.435 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:18.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:18.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:18.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:18.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:18.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:18.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:18.462 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:18.462 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:18.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:18.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:18.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:18.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:18.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:18.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:18.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:18.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:18.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:18.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:18.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:18.673 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:18.673 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:18.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:18.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:18.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:18.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.856 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:18.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:18.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:18.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:18.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:18.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:18.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:18.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:18.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:19.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:19.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:19.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:19.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:19.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:19.015 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:19.015 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:19.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:19.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:19.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:19.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:19.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:19.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:19.327 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:19.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:19.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:19.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:19.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:19.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:19.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:19.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:19.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:19.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:19.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:19.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:19.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:19.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:19.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:19.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:19.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:19.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:19.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:19.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:19.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:19.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:19.738 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:19.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:19.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:19.738 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=397 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:19.739 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=397 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:24.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:24.739 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:24.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:24.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:24.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:24.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:24.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:24.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:24.748 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:24.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:24.748 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:24.753 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:24.753 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:24.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:24.753 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:24.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:24.754 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:24.754 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:24.754 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:24.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:24.758 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:24.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:24.758 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:24.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:24.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:24.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:24.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:24.763 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:24.763 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:24.763 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:24.763 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:24.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:24.763 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:24.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:24.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:24.769 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:24.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:24.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:24.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:24.769 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.770 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:07:24.770 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:07:24.770 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:24.770 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:24.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:24.775 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:25.254 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:25.307 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:25.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:25.309 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:25.311 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:25.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:25.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:25.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:25.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:25.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:25.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:25.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:25.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:25.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:25.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:25.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:25.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:25.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:25.726 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:25.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:25.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:25.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:25.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:26.197 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:26.668 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:26.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:26.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:26.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:26.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:27.141 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:07:27.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:27.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:27.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:27.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:27.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:27.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:27.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:27.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:27.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:27.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:27.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:27.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:27.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:27.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:27.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:27.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:27.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:27.613 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:07:27.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:27.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:27.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:27.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:28.086 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:07:28.556 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:07:28.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:28.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:29.027 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:07:29.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:29.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:29.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:29.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:29.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:29.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:29.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:29.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:29.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:29.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:29.382 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:29.382 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:29.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:29.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:29.403 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:29.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:29.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:29.500 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:07:29.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:29.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:29.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:29.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:29.973 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:07:30.445 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:07:30.916 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:07:30.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:30.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:30.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:30.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:30.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:30.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:30.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:30.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:30.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:30.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:30.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:30.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:31.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:31.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:31.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:31.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:31.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:31.387 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:07:31.857 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:07:32.331 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:07:32.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:32.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:32.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:32.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:32.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:32.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:32.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:32.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:32.803 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:07:32.805 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:32.806 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:32.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:32.806 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:32.806 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:32.806 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:32.806 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:37.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:37.809 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:37.809 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:37.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:37.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:37.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:37.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:37.818 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:37.818 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:37.818 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:37.819 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:37.821 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:37.822 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:37.822 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:37.822 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:37.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:37.823 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:37.823 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:37.823 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:37.824 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:37.824 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:37.824 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:37.825 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:37.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:37.825 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:37.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:37.825 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:37.826 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:37.827 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:37.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:37.827 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:37.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:37.827 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:37.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:37.827 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:37.829 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:37.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:37.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:37.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:37.829 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:07:37.830 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:07:37.830 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:37.830 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:37.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:37.835 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:38.313 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:38.352 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:38.353 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:38.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:38.355 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:38.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:38.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:38.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:38.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:38.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:38.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:38.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:38.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:38.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:38.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:38.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:38.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:38.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:38.785 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:38.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:38.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:38.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:38.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:39.257 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:39.728 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:39.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:39.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:39.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:39.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:40.198 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:07:40.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:40.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:40.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:40.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:40.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:40.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:40.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:40.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:40.266 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:40.266 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:40.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:40.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:40.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:40.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:40.669 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:07:40.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:40.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:40.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:40.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:41.143 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:07:41.615 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:07:41.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:41.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:41.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:41.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:42.087 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:07:42.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:42.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:42.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:42.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:42.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:42.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:42.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:42.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:42.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:42.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:42.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:42.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:42.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:42.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:42.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:42.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:42.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:42.557 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:07:42.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:42.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:42.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:42.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:43.029 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:07:43.502 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:07:43.974 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:07:44.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:44.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:44.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:44.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:44.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:44.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:44.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:44.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:44.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:44.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:44.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:44.037 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:44.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:44.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:44.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:44.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:44.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:44.446 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:07:44.917 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:07:45.388 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:07:45.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:45.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:45.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:45.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:45.861 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:07:45.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:45.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:45.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:45.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:45.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:45.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:45.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:45.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:45.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:45.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:45.870 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:07:45.870 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:45.871 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:45.871 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:45.871 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:45.871 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:45.871 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:45.871 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:45.871 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1738 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:07:50.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:07:50.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:07:50.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:50.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:50.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:50.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:50.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:07:50.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:50.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:50.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:07:50.882 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:07:50.886 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:07:50.886 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:07:50.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:50.886 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:50.886 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:07:50.886 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:07:50.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:07:50.887 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:07:50.890 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:07:50.890 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:07:50.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:50.890 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:50.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:07:50.890 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:07:50.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:07:50.890 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:07:50.894 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:07:50.894 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:07:50.894 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:50.894 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:07:50.894 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:07:50.894 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:07:50.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:07:50.895 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:07:50.900 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:07:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:07:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:07:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:07:50.900 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:07:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:07:50.901 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:07:50.901 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:07:50.901 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:07:50.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:07:50.906 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:07:51.384 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:07:51.433 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:07:51.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:51.437 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:07:51.440 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:07:51.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:51.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:51.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:51.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:51.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:51.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:51.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:51.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:51.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:51.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:51.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:51.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:51.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:51.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:51.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:51.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:51.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:51.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:51.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:51.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:51.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:51.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:51.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:51.683 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:51.683 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:51.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:51.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:51.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:51.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:51.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:51.857 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:07:51.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:51.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:51.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:51.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:52.328 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:07:52.801 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:07:52.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:52.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:52.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:52.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:53.273 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:07:53.745 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:07:53.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:53.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:53.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:53.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:53.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:53.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.812 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:53.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:53.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:53.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:53.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:53.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:53.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:53.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:53.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:53.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:54.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:54.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:54.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:54.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:54.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:54.029 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:54.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:54.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:54.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:54.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:54.216 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:07:54.689 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:07:54.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:54.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:54.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:54.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:55.162 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:07:55.634 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:07:55.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:07:55.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:07:55.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:07:55.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:07:56.105 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:07:56.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:56.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:56.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:56.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:56.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:56.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:56.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:56.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:56.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:56.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:56.216 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:56.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:56.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:56.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:56.244 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:56.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:56.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:56.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:56.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:56.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:56.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:56.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:56.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:56.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:56.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:56.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:56.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:56.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:56.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:56.575 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:07:56.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:56.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:56.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:56.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:56.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:57.047 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:07:57.520 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:07:57.992 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:07:58.464 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:07:58.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:58.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:58.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:58.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:58.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:58.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:58.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:58.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:58.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:58.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:58.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:58.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:58.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:58.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:58.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:58.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:58.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:58.934 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:07:59.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:59.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:59.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:59.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:59.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:07:59.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:07:59.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:07:59.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:59.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:59.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:59.185 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:07:59.185 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:07:59.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:07:59.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:07:59.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:07:59.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:59.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:07:59.406 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:07:59.879 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:08:00.351 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:08:00.824 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:08:01.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:01.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:01.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:01.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:01.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:01.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:01.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:01.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:01.267 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:01.267 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:01.294 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:08:01.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:01.299 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:01.299 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:01.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.765 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:08:01.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:01.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:01.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:01.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:01.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:01.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:01.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:01.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:01.943 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:01.943 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:01.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:01.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:01.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:01.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:01.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:02.236 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:08:02.709 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:08:03.182 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:08:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:03.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:03.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:03.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:03.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:03.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:03.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:03.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:03.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:03.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:03.653 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:08:04.125 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:08:04.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:04.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:04.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:04.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:04.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:04.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:04.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:04.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:04.302 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:04.302 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:04.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:04.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:04.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:04.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:04.596 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:08:05.069 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:08:05.541 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:08:05.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:05.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:05.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:05.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:05.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:05.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:05.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:05.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:05.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:05.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:05.998 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:05.998 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:06.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:06.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:06.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:06.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:06.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:06.013 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:08:06.484 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:08:06.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:06.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:06.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:06.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:06.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:06.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:06.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:06.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:06.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:06.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:06.580 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:06.580 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:06.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:06.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:06.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:06.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:06.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:06.955 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:08:07.426 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:08:07.899 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:08:08.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:08.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:08.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:08.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:08.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:08.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:08.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:08.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:08.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:08.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:08.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:08.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:08.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:08.372 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:08:08.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:08.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:08.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:08.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:08.844 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:08:08.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:08.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:08.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:08.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:08.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:08.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:08.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:08.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:08.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:08.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:08.947 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:08.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:08.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:08.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:08.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:08.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:08.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:09.315 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:08:09.788 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:08:10.260 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:08:10.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:10.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:10.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:10.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:10.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:10.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:10.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:10.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:10.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:10.665 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:10.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:10.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:10.665 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:10.665 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:10.665 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:15.671 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:15.671 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:15.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:15.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:15.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:15.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:15.678 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:15.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:15.679 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:15.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:15.679 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:15.682 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:15.682 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:15.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:15.682 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:15.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:15.682 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:15.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:15.682 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:15.685 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:15.685 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:15.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:15.685 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:15.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:15.685 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:15.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:15.685 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:15.687 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:15.687 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:15.687 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:15.687 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:15.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:15.687 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:15.687 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:15.687 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:08:15.691 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:08:15.691 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:15.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:15.696 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:16.174 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:16.218 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:16.221 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:16.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.223 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:16.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:16.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.253 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:16.253 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:16.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:16.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:16.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:16.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:16.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:16.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:16.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:16.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:16.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:16.646 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:16.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:16.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:16.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:16.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:16.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:16.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:16.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:16.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.758 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:16.758 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:16.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:16.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:16.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:16.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:16.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:17.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:17.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:17.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:17.061 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:17.117 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:17.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:17.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:17.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:17.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.300 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:17.300 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:17.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:17.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:17.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:17.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:17.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:17.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:17.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:17.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.588 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:08:17.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:17.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:17.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:17.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:17.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:17.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:17.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:17.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:17.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:17.688 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:17.688 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:17.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:17.688 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:17.688 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:17.689 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:17.689 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:17.689 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:17.689 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:17.689 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:17.689 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:17.689 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:17.689 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:17.690 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=432 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:08:22.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:22.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:22.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:22.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:22.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:22.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:22.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:22.704 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:22.704 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:22.704 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:22.705 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:22.706 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:22.706 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:22.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:22.707 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:22.707 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:22.707 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:22.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:22.707 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:22.708 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:22.708 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:22.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:22.709 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:22.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:22.709 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:22.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:22.709 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:22.710 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:22.710 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:22.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:22.710 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:22.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:22.710 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:22.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:22.711 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:08:22.713 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:08:22.713 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:22.713 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:22.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:22.718 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:23.196 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:23.233 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:23.235 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:23.237 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:23.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:23.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:23.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:23.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:23.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:23.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:23.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:23.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:23.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:23.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:23.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:23.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:23.668 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:23.715 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:23.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:23.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:23.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:24.139 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:24.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:24.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:24.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:24.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:24.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:24.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:24.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:24.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:24.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:24.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:24.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:24.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:24.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:24.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.612 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:08:24.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:24.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:24.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:24.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:24.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:24.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:24.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:24.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:24.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:24.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:24.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:24.708 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:24.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:24.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:24.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:24.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:24.716 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:24.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:25.085 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:08:25.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:25.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:25.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:25.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:25.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:25.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:25.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:25.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:25.383 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:25.383 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:25.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:25.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:25.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:25.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.557 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:08:25.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:25.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:25.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:25.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:25.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:25.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:25.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:25.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:25.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:25.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:25.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:25.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:25.867 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:25.867 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:25.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:25.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:25.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:25.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:25.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:25.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:25.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:26.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:26.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:26.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:26.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:26.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:26.017 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:26.017 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:26.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:26.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:26.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:26.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.027 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:08:26.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:26.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:26.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:26.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:26.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:26.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:26.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:26.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:26.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:26.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:26.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:26.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:26.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:26.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.498 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:08:26.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:26.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:26.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:26.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:26.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:26.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:26.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:26.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:26.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:26.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:26.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:26.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:26.914 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:26.914 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:26.969 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:08:26.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:26.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:26.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:26.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:26.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:27.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:27.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:27.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:27.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:27.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:27.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:27.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:27.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:27.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:27.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:27.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:27.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:27.376 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:27.376 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:27.376 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:32.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:32.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:32.382 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:32.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:32.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:32.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:32.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:32.389 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:32.390 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:32.390 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:32.390 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:32.392 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:32.392 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:32.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:32.393 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:32.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:32.393 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:32.394 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:32.394 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:32.395 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:32.395 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:32.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:32.395 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:32.396 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:32.396 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:32.396 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:32.396 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:32.398 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:32.398 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:32.398 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:32.398 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:32.398 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:32.398 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:32.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:32.399 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:32.402 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:32.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:32.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:32.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:32.402 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:32.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:08:32.403 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:08:32.403 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:32.403 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:32.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:32.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:32.408 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:32.885 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:32.927 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:32.928 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:32.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:32.929 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:32.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:32.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:32.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:32.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:32.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:32.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:32.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:32.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:32.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:32.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:32.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:32.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:32.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:33.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:33.069 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:33.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:33.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.205 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:33.205 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:33.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:33.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:33.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:33.356 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:33.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:33.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:33.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:33.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:33.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:33.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.441 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:33.441 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:33.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:33.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:33.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:33.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.828 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:33.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:33.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:33.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.836 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:33.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:33.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:33.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:33.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:33.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:33.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:33.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:34.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:34.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:34.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:34.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:34.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:34.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:34.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:34.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:34.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:34.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:34.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:34.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:34.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:34.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:34.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:34.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:34.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:34.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:34.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:34.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:34.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:34.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:34.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:34.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:34.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:34.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:34.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:34.233 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:39.236 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:39.236 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:39.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:39.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:39.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:39.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:39.244 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:39.244 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:39.244 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:39.244 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:39.244 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:39.247 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:39.247 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:39.247 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:39.247 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:39.247 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:39.247 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:39.247 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:39.248 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:39.249 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:39.250 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:39.250 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:39.250 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:39.250 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:39.250 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:39.250 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:39.250 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:39.252 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:39.252 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:39.252 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:39.252 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:39.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:39.252 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:39.252 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:39.252 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:39.255 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:39.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:39.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:08:39.256 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:08:39.256 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:39.256 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:39.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:39.261 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:39.738 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:39.790 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:39.792 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:39.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:39.795 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:39.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:39.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:39.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:39.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:39.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:39.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:39.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:39.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:39.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:39.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:39.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:39.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:39.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:40.211 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:40.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:40.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:40.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:40.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:40.685 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:40.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:40.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:40.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:40.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:40.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:40.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:40.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:40.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:40.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:40.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:40.729 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:40.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:40.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:40.781 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:40.781 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:40.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:40.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:41.156 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:08:41.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:41.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:41.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:41.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:41.628 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:08:41.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:41.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:41.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:41.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:41.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:41.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:41.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:41.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:41.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:41.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:41.693 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:41.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:41.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:41.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:41.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:41.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:41.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:42.100 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:08:42.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:42.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:42.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:42.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:42.571 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:08:42.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:42.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:42.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:42.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:42.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:42.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:42.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:42.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:42.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:42.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:42.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:42.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:42.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:42.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:42.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:42.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:42.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.044 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:08:43.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:43.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:43.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:43.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:43.517 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:08:43.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:43.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:43.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:43.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:43.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:43.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:43.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:43.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:43.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:43.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:43.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:43.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:43.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:43.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:43.988 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:08:44.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:44.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:44.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:44.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:44.459 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:08:44.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:44.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:44.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:44.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:44.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:44.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:44.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:44.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:44.512 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:44.512 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:44.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:44.559 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:44.559 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:44.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:44.930 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:08:45.401 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:08:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:45.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:45.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:45.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:45.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:45.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:45.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:45.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:45.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:45.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:45.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:45.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:45.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:45.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:45.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:45.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:45.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:45.872 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:08:46.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:46.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:46.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:46.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:46.346 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:08:46.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:46.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:46.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:46.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:46.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:46.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:46.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:46.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:46.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:46.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:46.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:46.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:46.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:46.818 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:08:47.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:47.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:47.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:47.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:47.289 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:08:47.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:47.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:47.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:47.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:47.295 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:47.295 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:47.295 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:47.295 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:47.295 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:47.295 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:47.295 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:52.305 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:52.305 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:52.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:52.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:52.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:52.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:52.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:52.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:52.319 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:52.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:52.320 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:52.322 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:52.322 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:52.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:52.323 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:52.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:52.323 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:52.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:52.324 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:52.326 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:52.326 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:52.326 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:52.326 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:52.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:52.327 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:52.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:52.327 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:52.330 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:52.330 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:52.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:52.330 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:52.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:52.330 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:52.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:52.330 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:52.335 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:52.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:52.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:52.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:52.335 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:52.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:52.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:08:52.336 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:08:52.336 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:52.336 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:52.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:52.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:52.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:52.341 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:52.818 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:52.870 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:52.872 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:52.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:52.874 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:52.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:52.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:52.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:52.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:52.900 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:52.900 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:52.900 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:52.900 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:52.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:52.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:52.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:52.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:52.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:53.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:53.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:53.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:53.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:53.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:53.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:53.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:53.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:53.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:53.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:53.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:53.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:53.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:53.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.203 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:53.203 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:53.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:53.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:53.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:53.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:53.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:53.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:53.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:53.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:53.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:53.241 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:53.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.289 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:53.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:53.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:53.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:53.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:53.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:53.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:53.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:53.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:53.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:53.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:53.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:53.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:53.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:53.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:53.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:53.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:53.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:53.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.761 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:08:53.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:53.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:53.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:53.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:53.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:53.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:53.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:53.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:08:53.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:53.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:53.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:53.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:53.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:53.931 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:08:53.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:58.936 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:08:58.936 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:08:58.936 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:58.936 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:58.936 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:58.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:58.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:08:58.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:58.943 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:58.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:08:58.943 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:08:58.948 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:08:58.948 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:08:58.948 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:58.948 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:58.948 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:08:58.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:08:58.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:08:58.949 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:08:58.953 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:08:58.953 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:08:58.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:58.954 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:58.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:08:58.954 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:08:58.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:08:58.954 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:08:58.958 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:08:58.958 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:08:58.958 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:58.958 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:08:58.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:08:58.958 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:08:58.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:08:58.959 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:08:58.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:08:58.965 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:08:58.965 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:08:58.965 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:08:58.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:08:58.970 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:08:59.447 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:08:59.493 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:08:59.494 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:08:59.495 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:08:59.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:59.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:59.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:59.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:59.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:59.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:59.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:59.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:59.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:59.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:59.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:59.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:59.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:59.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:59.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:59.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:59.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:59.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:59.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:59.671 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:59.671 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:59.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:59.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:59.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:59.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:59.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:59.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:59.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:08:59.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:08:59.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:08:59.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:59.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:59.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:08:59.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:08:59.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:08:59.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:08:59.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:08:59.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:08:59.919 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:08:59.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:08:59.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:08:59.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:08:59.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:00.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:00.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:00.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:00.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:00.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:00.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:00.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:00.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:00.169 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:00.169 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:00.169 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:00.169 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:00.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:00.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:00.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:00.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:00.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:00.390 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:00.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:00.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:00.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:00.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:00.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:00.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:00.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:00.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:00.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:00.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:00.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:00.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:00.558 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:00.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:00.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:00.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:00.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:05.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:05.570 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:05.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:05.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:05.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:05.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:05.578 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:05.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:05.580 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:05.580 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:05.584 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:05.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:05.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:05.585 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.585 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:05.585 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:05.586 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:05.590 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:05.590 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:05.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:05.590 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:05.590 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:05.591 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:05.594 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:05.595 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:05.595 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:05.595 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:05.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:05.595 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.595 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:05.595 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:05.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:05.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:05.602 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:05.602 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:05.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:05.607 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:06.084 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:06.127 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:06.127 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:06.128 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:06.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:06.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:06.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.147 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:06.147 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:06.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:06.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:06.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:06.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:06.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:06.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:06.555 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:06.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:06.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:06.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.569 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:06.569 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:06.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:06.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:06.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:06.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:06.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:06.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:06.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:06.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:06.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:06.806 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:06.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:06.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:06.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:06.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:06.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:07.027 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:07.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:07.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:07.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:07.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:07.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:07.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:07.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:07.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:07.189 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:07.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:07.189 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:07.189 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:07.189 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:07.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:07.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:12.196 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:12.196 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:12.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:12.197 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:12.197 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:12.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:12.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:12.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:12.206 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:12.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:12.206 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:12.210 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:12.211 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:12.211 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:12.211 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:12.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:12.211 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:12.211 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:12.211 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:12.216 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:12.216 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:12.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:12.216 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:12.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:12.217 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:12.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:12.217 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:12.221 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:12.221 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:12.221 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:12.221 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:12.221 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:12.221 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:12.222 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:12.222 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:12.227 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:12.229 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:12.229 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:12.229 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:12.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:12.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:12.234 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:12.711 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:12.763 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:12.764 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:12.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:12.766 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:12.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:12.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:12.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:12.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:12.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:12.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:12.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:12.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:12.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:12.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:12.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:12.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:12.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:12.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:12.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:12.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:12.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:12.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:12.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:12.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:12.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:12.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:12.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:12.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:12.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:12.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:12.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:12.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:12.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:12.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:13.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:13.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:13.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:13.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:13.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:13.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:13.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:13.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:13.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:13.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:13.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:13.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:13.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.183 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:13.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:13.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:13.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:13.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:13.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:13.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:13.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:13.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:13.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:13.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:13.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:13.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:13.433 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:13.433 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:13.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:13.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:13.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:13.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.654 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:13.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:13.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:13.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:13.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:13.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:13.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:13.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:13.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:13.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:13.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:13.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:13.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:13.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:13.823 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:13.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:18.830 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:18.830 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:18.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:18.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:18.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:18.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:18.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:18.841 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:18.842 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:18.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:18.842 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:18.846 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:18.847 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:18.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:18.847 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:18.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:18.848 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:18.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:18.849 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:18.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:18.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:18.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:18.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:18.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:18.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:18.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:18.852 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:18.854 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:18.854 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:18.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:18.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:18.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:18.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:18.855 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:18.855 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.858 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:18.858 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:18.858 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:18.859 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:18.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:18.863 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:19.341 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:19.387 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:19.389 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:19.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:19.391 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:19.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:19.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:19.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:19.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:19.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:19.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:19.423 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:19.423 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:19.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:19.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:19.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:19.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:19.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:19.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:19.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:19.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:19.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:19.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:19.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:19.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:19.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:19.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:19.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:19.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:19.813 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:19.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:19.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:19.819 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:19.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:19.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:19.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:19.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:19.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:19.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:20.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:20.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:20.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:20.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:20.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:20.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:20.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:20.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:20.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:20.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:20.321 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:20.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:20.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:20.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:20.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:20.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:20.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:20.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:20.757 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:20.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:20.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:20.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:20.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:21.230 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:21.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:21.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:21.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:21.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:21.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:21.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:21.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:21.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:21.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:21.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:21.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:21.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:21.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:21.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:21.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:21.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:21.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:21.702 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:21.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:21.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:21.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:21.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:22.173 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:22.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:22.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:22.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:22.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:22.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:22.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:22.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:22.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:22.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:22.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:22.502 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:22.502 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:22.502 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:22.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:22.502 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:27.508 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:27.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:27.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:27.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:27.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:27.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:27.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:27.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:27.523 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:27.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:27.524 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:27.527 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:27.527 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:27.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:27.527 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:27.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:27.528 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:27.528 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:27.528 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:27.531 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:27.531 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:27.531 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:27.531 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:27.531 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:27.531 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:27.531 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:27.531 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:27.534 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:27.534 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:27.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:27.535 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:27.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:27.535 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:27.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:27.535 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:27.539 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:27.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:27.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:27.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:27.539 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:27.540 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:27.540 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:27.540 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:27.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:27.545 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:28.023 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:28.074 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:28.076 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:28.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:28.078 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:28.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:28.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:28.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:28.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:28.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:28.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:28.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:28.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:28.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:28.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:28.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:28.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:28.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:28.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:28.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:28.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:28.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:28.495 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:28.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:28.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:28.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:28.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:28.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:28.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:28.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:28.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:28.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:28.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:28.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:28.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:28.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:28.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:28.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:28.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:28.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:28.966 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:29.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:29.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:29.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:29.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:29.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:29.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:29.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:29.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:29.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:29.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:29.087 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:29.087 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:29.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:29.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:29.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:29.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:29.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:29.439 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:29.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:29.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:29.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:29.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:29.912 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:30.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:30.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:30.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:30.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:30.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:30.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:30.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:30.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:30.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:30.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:30.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:30.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:30.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:30.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:30.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:30.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:30.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:30.384 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:30.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:30.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:30.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:30.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:30.855 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:31.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:31.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:31.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:31.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:31.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:31.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:31.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:31.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:31.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:31.184 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:31.184 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:31.184 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:31.184 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:31.184 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:31.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:36.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:36.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:36.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:36.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:36.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:36.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:36.219 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:36.219 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:36.219 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.219 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:36.219 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:36.220 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:36.220 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:36.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:36.220 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:36.220 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:36.220 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:36.223 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:36.223 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:36.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:36.223 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:36.224 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.224 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:36.224 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:36.226 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:36.227 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:36.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:36.227 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:36.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:36.227 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:36.227 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:36.231 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.232 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:36.232 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:36.232 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:36.232 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:36.234 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:36.237 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:36.715 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:36.753 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:36.754 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:36.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:36.755 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:36.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:36.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:36.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:36.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:36.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:36.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:36.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:36.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:36.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:36.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:36.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:36.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:36.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:37.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:37.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:37.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:37.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:37.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:37.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:37.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:37.155 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:37.155 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:37.185 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:37.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:37.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:37.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:37.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:37.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:37.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:37.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:37.658 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:37.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:37.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:37.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:37.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:37.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:37.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:37.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:37.697 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:37.697 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:37.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:37.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:37.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:37.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:37.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:38.130 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:38.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:38.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:38.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:38.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:38.601 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:38.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:38.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:38.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:38.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:38.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:38.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:38.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:38.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:38.780 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:38.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:38.780 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:38.780 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:38.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:38.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:38.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:38.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:38.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:39.072 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:39.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:39.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:39.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:39.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:39.543 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:39.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:39.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:39.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:39.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:39.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:39.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:39.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:39.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:39.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:39.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:39.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:39.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:39.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:39.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:39.878 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:39.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:39.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:39.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:39.878 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:39.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:39.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:39.879 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:44.884 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:44.884 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:44.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:44.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:44.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:44.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:44.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:44.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:44.894 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:44.895 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:44.895 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:44.898 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:44.898 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:44.898 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:44.898 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:44.898 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:44.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:44.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:44.899 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:44.902 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:44.902 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:44.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:44.902 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:44.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:44.902 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:44.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:44.902 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:44.904 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:44.904 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:44.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:44.904 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:44.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:44.905 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:44.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:44.905 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.908 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:44.908 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:44.908 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:44.909 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:44.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:44.913 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:45.391 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:45.441 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:45.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:45.444 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:45.447 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:45.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:45.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:45.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:45.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:45.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:45.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:45.479 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:45.479 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:45.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:45.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:45.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:45.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:45.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:45.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:45.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:45.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:45.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:45.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:45.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:45.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:45.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:45.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:45.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:45.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:45.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:45.863 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:09:45.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:45.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:45.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:45.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:45.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:45.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:45.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:45.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:45.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:46.334 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:09:46.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:46.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:46.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:46.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:46.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:46.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:46.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:46.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:46.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:46.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:46.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:46.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:46.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:46.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:46.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:46.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:46.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:46.807 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:09:46.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:46.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:46.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:46.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:47.280 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:09:47.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:47.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:47.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:47.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:47.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:47.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:47.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:47.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:47.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:47.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:47.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:09:47.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:09:47.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:47.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:09:47.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:09:47.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:47.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:47.752 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:09:47.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:47.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:47.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:47.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:48.223 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:09:48.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:48.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:09:48.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:48.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:48.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:48.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:48.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:48.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:48.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:48.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:48.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:48.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:48.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:48.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:48.558 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:48.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:53.560 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:53.561 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:53.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:53.561 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:53.561 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:53.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:53.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:53.570 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:53.571 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.571 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:53.571 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:53.576 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:53.577 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:53.577 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:53.577 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:53.578 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:53.578 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:53.581 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:53.582 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:53.582 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:53.582 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.583 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:53.583 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.583 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:53.584 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:53.586 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:53.587 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:53.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:53.587 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:53.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:53.588 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.588 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:53.588 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:53.592 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:53.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:53.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:53.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:53.592 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:53.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:53.593 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:53.593 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:53.593 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:53.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:53.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:53.598 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:54.076 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:54.119 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:54.119 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:54.120 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:54.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:54.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:54.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:54.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:54.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:54.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:54.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:54.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:54.149 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:54.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:54.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:54.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:54.150 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:54.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:54.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:54.150 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:59.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:59.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:59.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:59.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:59.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:59.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:59.160 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:59.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:59.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:59.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:09:59.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:09:59.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:09:59.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:09:59.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:59.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:59.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:59.168 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:09:59.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:09:59.169 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:09:59.170 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:09:59.171 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:09:59.171 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:59.171 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:59.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:59.172 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:09:59.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:09:59.172 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:09:59.174 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:09:59.174 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:09:59.174 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:59.174 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:09:59.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:59.175 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:09:59.175 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:09:59.175 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.178 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:09:59.178 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:09:59.178 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:09:59.179 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:09:59.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:09:59.183 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:09:59.661 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:09:59.711 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:09:59.715 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:09:59.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:59.717 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:09:59.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:59.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:59.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:59.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:09:59.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:09:59.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:09:59.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:09:59.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:09:59.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:09:59.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:09:59.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:09:59.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:09:59.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:09:59.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:09:59.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:09:59.781 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:09:59.781 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:09:59.781 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:09:59.781 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:59.781 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:59.781 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:59.782 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:59.782 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:59.782 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:09:59.782 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:04.787 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:04.787 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:04.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:04.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:04.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:04.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:04.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:04.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:04.797 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:04.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:04.797 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:04.801 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:04.801 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:04.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:04.801 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:04.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:04.801 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:04.802 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:04.802 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:04.805 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:04.805 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:04.805 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:04.805 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:04.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:04.805 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:04.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:04.806 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:04.808 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:04.808 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:04.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:04.809 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:04.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:04.809 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:04.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:04.809 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.814 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:10:04.814 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:10:04.814 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:04.815 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:04.819 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:10:05.298 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:10:05.350 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:10:05.352 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:10:05.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:05.354 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:10:05.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:05.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:05.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:05.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:05.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:05.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:05.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:05.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:05.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:05.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:05.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:05.394 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:05.394 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:05.395 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:10:05.395 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:05.395 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:05.395 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:05.395 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:05.395 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:05.395 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:10.398 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:10.398 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:10.398 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:10.398 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:10.398 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:10.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:10.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:10.405 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:10.405 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:10.406 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:10.406 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:10.408 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:10.408 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:10.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:10.409 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:10.409 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:10.409 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:10.410 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:10.410 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:10.411 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:10.412 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:10.412 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:10.412 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:10.412 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:10.412 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:10.412 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:10.413 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:10.414 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:10.415 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:10.415 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:10.415 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:10.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:10.415 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:10.415 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:10.415 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:10.418 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:10.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:10.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:10.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:10.418 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:10:10.419 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:10:10.419 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:10.419 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:10.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:10.421 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:10.421 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:10.421 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:10:15.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:15.428 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:15.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:15.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:15.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:15.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:15.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:15.435 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:15.435 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.436 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:15.436 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:15.440 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:15.440 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:15.440 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:15.441 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:15.441 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:15.442 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:15.444 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:15.445 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:15.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:15.445 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:15.446 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.446 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:15.446 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:15.449 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:15.449 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:15.449 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:15.449 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:15.450 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:15.450 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.450 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:15.450 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.455 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:10:15.456 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:10:15.456 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:15.456 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:15.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:15.461 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:10:15.939 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:10:15.983 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:10:15.984 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:10:15.985 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:10:15.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:15.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:15.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:15.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:16.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:16.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:16.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:16.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:16.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.411 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:10:16.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:16.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:16.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:16.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:16.883 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:10:16.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:16.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:16.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:16.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:17.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:17.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:17.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:17.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:17.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:17.016 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:17.016 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:17.016 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:17.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:17.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:17.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:17.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:17.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:17.355 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:10:17.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:17.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:17.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:17.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:17.828 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:10:17.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:17.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:17.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:17.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:17.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:17.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:17.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:17.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:17.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:17.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:17.969 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:17.969 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:18.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:18.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:18.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:18.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:18.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:18.300 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:10:18.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:18.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:18.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:18.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:18.772 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:10:18.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:18.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:18.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:18.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:18.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:18.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:18.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:18.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:18.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:18.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:18.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:18.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:18.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:18.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:18.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:18.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:18.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:19.245 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:10:19.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:19.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:19.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:19.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:19.717 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:10:19.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:19.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:19.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:19.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:19.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:19.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:19.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:19.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:19.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:19.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:19.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:19.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:19.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:19.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:19.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:19.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:19.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:20.189 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:10:20.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:20.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:20.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:20.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:20.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:20.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:20.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:20.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:20.509 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1091 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:20.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:20.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:20.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:20.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:20.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:20.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:20.528 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:20.528 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:20.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:20.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:20.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:20.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:20.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:20.661 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:10:21.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:21.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:21.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:21.108 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:21.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:21.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:21.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:21.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:21.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:21.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:21.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:21.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:21.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:21.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:21.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:21.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:21.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:21.133 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:10:21.606 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:10:21.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:21.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:21.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:21.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:21.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:21.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:21.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:21.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:21.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:21.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:21.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:21.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:21.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:21.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:21.755 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:21.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:21.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:21.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:22.079 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:10:22.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:22.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:22.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:22.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:22.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:22.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:22.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:22.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:22.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:22.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:22.363 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:22.363 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:22.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:22.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:22.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:22.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:22.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:22.552 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:10:22.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:22.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:22.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:22.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:23.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:23.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:23.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:23.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:23.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:23.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:23.019 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:23.019 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:23.024 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:10:23.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:23.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:23.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:23.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:23.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:23.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:23.496 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:10:23.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:23.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:23.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:23.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:23.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:23.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:23.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:23.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:23.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:23.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:23.640 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:23.640 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:23.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:23.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:23.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:23.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:23.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:23.967 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:10:24.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:24.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:24.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:24.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:24.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:24.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:24.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:24.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:24.287 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:24.287 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:24.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:24.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:24.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:24.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.438 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:10:24.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:24.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:24.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:24.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:24.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:24.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:24.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:24.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:24.901 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:24.901 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:24.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:24.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:24.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:24.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:24.908 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:10:25.379 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:10:25.850 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:10:25.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:25.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:25.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:25.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:25.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:25.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:25.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:25.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:25.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:25.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:25.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:25.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:25.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:25.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:25.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:25.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:25.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:26.321 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:10:26.786 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:10:26.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:26.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:26.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:26.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:26.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:26.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:26.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:26.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:26.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:26.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:26.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:26.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:26.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:26.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:26.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:26.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:26.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:27.256 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:10:27.728 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:10:27.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:27.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:27.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:27.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:27.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:27.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:27.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:27.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:27.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:27.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:27.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:27.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:27.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:27.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:27.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:27.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:27.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:28.200 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:10:28.671 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:10:28.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:28.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:28.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:28.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:28.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:28.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:28.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:28.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:28.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:28.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:28.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:28.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:28.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:28.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:28.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:28.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:28.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:29.144 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:10:29.617 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:10:29.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:29.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:29.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:29.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:29.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:29.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:29.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:29.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:29.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:29.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:29.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:29.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:29.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:29.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:29.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:29.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:29.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:30.089 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:10:30.560 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:10:30.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:30.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:30.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:30.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:30.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:30.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:30.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:30.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:30.680 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:30.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:30.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:30.680 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:30.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:30.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:30.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:30.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:30.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:31.033 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:10:31.506 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:10:31.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:31.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:31.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:31.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:31.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:31.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:31.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:31.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:31.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:31.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:31.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:31.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:31.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:31.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:31.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:31.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:31.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:31.977 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:10:32.449 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:10:32.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:32.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:32.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:32.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:32.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:32.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:32.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:32.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:32.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:32.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:32.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:32.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:32.599 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:10:32.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:32.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:37.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:37.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:37.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:37.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:37.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:37.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:37.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:37.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:37.615 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:37.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:37.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:37.618 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:37.618 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:37.618 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:37.618 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:37.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:37.619 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:37.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:37.619 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:37.621 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:37.621 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:37.621 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:37.621 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:37.621 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:37.621 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:37.621 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:37.621 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:37.623 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:37.623 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:37.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:37.623 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:37.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:37.623 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:37.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:37.623 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.626 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:10:37.626 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:10:37.626 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:37.626 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:37.631 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:10:38.110 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:10:38.152 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:10:38.154 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:10:38.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.157 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:10:38.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:38.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:38.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:38.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.183 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:38.183 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:38.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:38.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:38.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:38.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:38.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:38.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.477 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:38.477 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:38.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.581 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:10:38.628 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:38.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:38.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:38.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:38.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:38.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:38.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:38.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:38.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:38.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:38.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:38.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:38.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:38.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:38.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:38.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:10:38.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:10:38.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:10:38.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:38.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:10:38.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:10:38.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:38.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:39.053 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:10:39.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:10:39.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:10:39.229 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:10:39.229 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:10:39.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:10:39.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:10:39.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:10:39.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:10:39.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:39.237 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:39.237 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:39.237 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:39.237 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:10:39.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:39.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:39.237 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:39.237 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:39.237 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:39.237 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:10:44.243 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:10:44.243 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:10:44.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:44.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:44.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:44.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:44.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:10:44.252 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:44.252 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:44.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:10:44.253 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:10:44.256 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:10:44.256 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:10:44.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:44.256 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:44.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:10:44.257 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:10:44.257 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:10:44.257 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:10:44.259 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:10:44.260 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:10:44.260 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:44.260 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:44.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:10:44.261 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:10:44.261 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:10:44.261 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:10:44.262 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:10:44.262 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:10:44.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:44.262 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:10:44.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:10:44.262 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:10:44.263 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:10:44.263 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:10:44.265 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:10:44.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:10:44.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:10:44.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:10:44.265 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:10:44.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:10:44.266 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:10:44.266 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:10:44.266 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:10:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:10:44.270 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:10:44.749 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:10:45.221 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:10:45.692 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:10:46.165 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:10:46.638 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:10:47.110 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:10:47.584 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:10:48.056 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:10:48.528 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:10:49.002 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:10:49.474 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:10:49.941 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:10:50.407 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:10:50.878 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:10:51.347 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:10:51.810 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:10:52.274 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:10:52.737 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:10:53.209 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:10:53.677 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:10:54.140 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:10:54.604 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:10:55.067 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:10:55.530 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:10:56.002 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:10:56.474 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:10:56.945 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:10:57.409 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:10:57.874 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:10:58.348 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:10:58.820 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:10:59.294 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:10:59.766 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:11:00.238 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:11:00.711 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:11:01.184 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:11:01.656 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:11:02.130 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:11:02.602 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:11:03.074 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:11:03.547 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:11:04.020 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:11:04.492 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:11:04.966 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:11:05.438 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:11:05.910 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:11:06.384 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:11:06.856 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:11:07.328 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:11:07.802 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:11:08.274 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:11:08.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:08.296 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:08.296 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:08.296 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:08.296 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:11:08.296 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:11:08.296 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:11:08.296 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5208 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:08.296 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5208 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:08.296 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5208 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:08.296 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5208 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:08.296 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5208 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:11:13.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:11:13.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:11:13.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:13.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:13.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:13.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:13.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:13.313 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:11:13.313 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:13.314 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:11:13.314 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:11:13.316 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:11:13.316 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:11:13.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:11:13.317 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:13.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:13.317 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:11:13.318 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:11:13.318 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:11:13.319 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:11:13.319 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:11:13.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:11:13.320 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:13.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:13.320 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:11:13.320 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:11:13.320 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:11:13.321 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:11:13.321 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:11:13.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:11:13.322 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:11:13.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:13.322 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:11:13.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:11:13.322 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:11:13.324 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:11:13.325 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:11:13.325 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:11:13.325 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:11:13.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:11:13.330 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:11:13.808 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:11:14.280 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:11:14.756 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:11:15.227 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:11:15.703 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:11:16.175 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:11:16.650 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:11:17.122 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:11:17.596 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:11:18.068 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:11:18.540 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:11:19.014 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:11:19.486 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:11:19.958 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:11:20.433 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:11:20.905 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:11:21.379 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:11:21.851 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:11:22.323 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:11:22.799 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:11:23.270 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:11:23.741 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:11:24.217 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:11:24.689 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:11:25.163 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:11:25.635 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:11:26.107 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:11:26.581 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:11:27.053 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:11:27.525 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:11:27.999 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:11:28.471 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:11:28.943 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:11:29.416 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:11:29.889 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:11:30.361 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:11:30.835 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:11:31.307 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:11:31.778 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:11:32.253 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:11:32.725 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:11:33.201 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:11:33.673 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:11:34.148 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:11:34.620 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:11:35.094 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:11:35.566 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:11:36.038 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:11:36.507 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:11:36.980 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:11:37.452 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:11:37.926 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:11:38.398 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:11:38.870 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:11:39.344 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:11:39.815 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:11:40.287 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:11:40.761 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:11:41.229 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:11:41.703 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:11:42.175 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:11:42.649 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:11:43.121 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:11:43.585 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:11:44.048 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:11:44.511 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:11:44.975 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:11:45.438 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:11:45.910 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:11:46.382 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:11:46.856 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:11:47.324 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:11:47.788 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:11:48.260 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:11:48.732 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:11:49.206 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:11:49.678 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:11:50.150 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:11:50.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:50.626 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:11:51.098 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:11:51.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:51.562 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:11:52.025 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:11:52.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:52.488 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:11:52.951 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:11:53.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:53.424 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:11:53.896 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:11:54.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:54.371 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:11:54.843 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:11:55.317 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:11:55.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:11:55.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:11:55.358 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:11:55.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:11:55.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:11:55.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:11:55.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:11:55.358 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:12:00.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:00.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:12:00.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:00.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:00.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:00.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:00.374 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:00.376 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:00.376 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:00.377 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:00.377 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:12:00.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:12:00.383 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:12:00.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:00.383 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:00.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:00.385 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:12:00.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:00.385 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:12:00.388 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:12:00.388 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:12:00.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:00.388 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:00.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:00.389 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:12:00.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:00.389 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:12:00.392 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:12:00.392 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:12:00.392 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:00.392 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:00.393 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:12:00.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:00.393 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:00.393 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:12:00.398 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:12:00.398 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:12:00.398 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:00.403 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:12:00.881 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:12:00.925 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:12:00.926 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:00.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:00.927 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:12:00.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:00.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:00.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:00.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:00.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:00.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:00.947 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:00.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:00.974 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:00.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:00.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:00.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:00.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:00.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:01.352 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:12:01.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:01.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:01.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:01.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:01.824 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:12:01.840 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:02.295 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:12:02.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:02.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:02.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:02.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:02.769 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:12:03.241 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:12:03.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:03.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:03.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:03.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:03.714 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:12:04.184 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:12:04.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:04.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:04.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:04.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:04.655 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:12:05.129 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:12:05.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:05.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:05.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:05.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:05.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:05.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:05.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:05.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:05.228 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:05.228 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:05.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:05.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:05.265 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:05.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:05.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:05.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:05.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:05.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:05.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:05.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:05.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:05.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:05.600 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:12:06.072 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:12:06.411 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:06.543 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:12:07.014 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:12:07.485 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:12:07.959 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:12:08.431 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:12:08.902 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:12:09.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:09.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:09.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:09.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:09.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:09.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:09.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:09.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:09.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:09.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:09.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:09.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:09.373 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:09.373 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:12:09.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:09.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:09.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:09.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:09.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:09.808 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:09.844 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:12:10.318 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:12:10.790 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:12:11.262 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:12:11.733 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:12:12.206 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:12:12.679 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:12:13.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:13.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:13.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:13.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:13.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:13.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:13.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:13.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:13.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:13.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:13.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:13.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:13.146 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:13.150 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:12:13.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:13.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:13.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:13.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:13.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:13.622 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:12:14.010 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:14.092 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:12:14.481 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:14.563 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:12:15.037 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:12:15.423 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:15.509 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:12:15.981 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:12:16.452 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:12:16.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:16.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:16.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:16.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:16.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:16.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:16.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:16.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:16.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:16.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:16.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:16.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:16.859 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:16.859 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:12:16.859 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:12:21.863 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:21.863 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:12:21.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:21.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:21.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:21.864 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:21.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:21.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:21.873 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:21.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:21.873 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:12:21.877 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:12:21.877 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:12:21.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:21.877 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:21.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:21.878 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:12:21.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:21.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:12:21.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:12:21.882 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:12:21.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:21.882 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:21.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:21.883 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:12:21.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:21.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:12:21.886 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:12:21.887 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:12:21.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:21.887 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:21.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:21.887 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:12:21.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:21.887 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.894 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:12:21.894 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:12:21.894 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:12:21.895 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:21.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:21.899 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:12:22.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:12:22.426 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:12:22.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:22.429 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:22.432 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:12:22.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:22.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:22.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:22.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:22.466 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:22.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:22.466 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:22.466 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:22.517 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:22.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:22.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:22.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:22.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:22.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:22.848 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:12:22.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:22.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:22.899 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:22.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:23.321 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:12:23.337 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:23.794 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:12:23.817 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:23.819 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:23.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:23.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:23.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:23.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:24.267 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:12:24.297 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:24.739 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:12:24.783 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:24.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:24.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:24.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:24.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:25.212 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:12:25.263 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:25.683 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:12:25.743 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:25.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:25.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:25.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:25.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:26.154 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:12:26.223 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:26.627 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:12:26.703 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:26.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:26.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:26.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:26.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:27.099 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:12:27.189 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:27.572 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:12:27.669 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:28.045 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:12:28.149 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:28.518 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:12:28.635 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:28.990 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:12:29.115 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:29.464 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:12:29.595 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:29.936 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:12:30.081 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:30.409 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:12:30.561 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:30.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:30.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:30.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:30.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:30.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:30.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:30.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:30.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:30.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:30.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:30.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:30.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:30.588 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:30.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:30.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:30.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:30.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:30.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:30.879 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:12:31.282 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:31.353 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:12:31.762 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:31.765 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:31.825 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:12:32.248 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:32.297 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:12:32.728 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:32.768 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:12:33.208 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:33.239 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:12:33.688 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:33.710 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:12:34.168 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:34.181 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:12:34.648 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:34.651 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:12:35.122 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:12:35.128 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:35.596 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:12:35.608 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:36.068 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:12:36.094 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:36.540 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:12:36.574 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:37.011 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:12:37.054 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:37.485 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:12:37.534 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:37.957 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:12:38.020 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:38.429 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:12:38.500 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:38.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:38.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:38.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:38.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:38.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:38.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:38.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:38.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:38.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:38.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:38.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:38.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:38.568 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:38.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:38.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:38.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:38.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:38.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:38.864 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:38.900 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:12:39.334 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:39.337 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:39.373 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:12:39.805 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:39.846 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:12:40.282 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:40.318 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:12:40.752 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:40.792 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:12:41.223 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:41.264 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:12:41.700 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:41.736 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:12:42.171 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:42.207 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:12:42.642 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:42.681 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:12:43.112 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:43.153 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:12:43.589 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:43.625 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:12:44.060 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:44.096 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:12:44.530 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:44.567 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:12:45.001 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:45.038 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:12:45.472 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:45.511 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:12:45.943 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:45.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:45.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:45.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:45.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:45.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:45.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:45.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:45.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:45.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:45.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:45.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:45.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:45.974 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:45.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:45.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:45.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:45.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:45.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:45.983 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:12:46.373 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:46.455 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:12:46.844 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:46.846 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:46.926 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:12:47.314 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:47.317 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:47.399 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:12:47.785 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:47.871 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:12:48.262 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:48.264 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:12:48.343 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:12:48.732 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:48.814 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:12:49.203 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:49.287 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:12:49.674 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:49.760 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:12:50.150 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:50.232 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:12:50.621 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:50.703 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:12:51.092 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:51.177 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:12:51.563 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:51.649 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:12:52.039 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:52.120 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:12:52.510 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:52.592 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:12:52.981 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:53.065 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:12:53.451 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:53.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:53.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:53.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:53.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:53.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:53.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:53.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:53.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:53.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:53.460 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:53.460 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:53.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:53.460 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:53.460 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:12:53.460 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:12:58.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:12:58.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:12:58.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:58.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:58.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:58.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:58.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:12:58.475 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:58.476 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.476 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:12:58.476 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:12:58.480 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:12:58.480 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:12:58.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:58.481 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:12:58.481 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:12:58.482 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:12:58.483 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:12:58.483 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:12:58.484 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:58.484 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:12:58.484 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.484 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:12:58.484 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:12:58.486 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:12:58.486 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:12:58.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:58.486 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:12:58.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:12:58.486 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:12:58.486 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:12:58.489 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:12:58.489 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:12:58.489 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:12:58.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:12:58.494 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:12:58.972 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:12:59.011 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:12:59.012 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:12:59.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:59.013 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:12:59.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:12:59.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:12:59.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:12:59.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:59.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:59.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:59.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:12:59.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:12:59.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:12:59.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:12:59.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:12:59.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:59.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:12:59.444 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:12:59.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:12:59.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:12:59.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:12:59.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:12:59.915 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:00.389 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:00.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:00.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:00.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:00.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:00.861 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:01.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:01.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:01.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:01.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:01.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:01.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:01.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:01.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:01.203 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:01.203 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:01.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:01.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:01.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:01.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:01.333 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:13:01.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:01.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:01.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:01.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:01.805 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:13:02.278 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:13:02.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:02.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:02.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:02.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:02.750 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:13:03.223 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:13:03.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:03.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:03.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:03.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:03.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:03.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:03.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:03.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:03.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:03.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:03.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:03.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:03.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:03.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:03.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:03.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:03.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:03.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:03.696 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:13:04.169 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:13:04.641 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:13:05.112 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:13:05.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:05.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:05.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:05.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:05.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:05.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:05.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:05.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:05.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:05.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:05.526 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:05.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:05.526 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:05.526 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:05.526 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:05.526 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1519 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.526 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1519 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1519 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1519 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1519 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1519 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:05.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:10.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:10.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:10.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:10.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:10.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:10.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:10.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:10.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:10.536 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:10.536 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:10.539 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:10.540 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:10.540 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:10.540 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:10.541 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.541 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:10.541 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:10.543 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:10.543 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:10.543 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:10.544 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:10.544 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:10.544 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:10.546 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:10.546 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:10.546 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:10.546 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:10.546 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:10.546 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.546 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:10.546 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:10.549 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:10.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:10.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:10.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:10.549 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:10.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:13:10.550 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:13:10.550 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:10.550 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:10.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:10.555 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:11.033 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:11.075 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:11.077 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:11.078 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:11.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:11.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:11.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:11.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:11.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:11.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:11.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:11.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:11.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:11.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:11.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:11.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:11.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:11.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:11.505 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:11.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:11.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:11.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:11.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:11.976 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:12.447 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:12.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:12.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:12.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:12.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:12.918 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:13.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:13.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:13.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:13.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:13.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:13.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:13.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:13.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:13.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:13.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:13.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:13.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:13.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:13.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:13.391 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:13:13.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:13.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:13.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:13.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:13.864 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:13:14.336 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:13:14.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:14.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:14.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:14.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:14.807 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:13:15.281 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:13:15.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:15.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:15.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:15.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:15.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:15.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:15.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:15.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:15.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:15.417 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:15.417 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:15.417 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:15.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:15.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:15.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:15.418 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1052 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.418 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1052 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.418 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1052 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.418 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1052 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.418 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1052 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:15.419 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1052 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:20.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:20.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:20.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:20.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:20.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:20.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:20.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:20.429 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:20.429 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:20.430 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:20.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:20.434 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:20.434 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:20.434 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:20.434 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:20.435 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:20.438 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:20.438 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:20.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:20.438 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:20.438 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:20.438 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:20.441 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:20.441 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:20.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:20.441 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:20.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:20.442 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:20.442 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:13:20.447 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:13:20.447 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:20.447 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:20.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:20.452 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:20.930 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:20.974 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:20.976 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:20.977 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:20.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:20.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:20.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:20.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:21.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:21.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:21.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:21.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:21.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:21.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:21.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:21.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:21.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:21.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:21.402 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:21.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:21.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:21.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:21.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:21.873 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:22.347 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:22.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:22.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:22.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:22.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:22.819 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:23.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:23.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:23.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:23.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:23.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:23.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:23.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:23.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:23.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:23.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:23.159 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:23.159 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:23.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:23.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:23.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:23.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:23.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:23.292 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:13:23.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:23.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:23.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:23.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:23.762 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:13:24.233 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:13:24.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:24.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:24.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:24.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:24.704 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:13:25.175 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:13:25.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:25.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:25.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:25.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:25.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:25.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:25.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:25.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:25.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:25.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:25.316 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:25.316 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:25.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:25.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:25.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:25.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:25.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:25.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:25.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:25.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:25.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:25.645 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:13:26.116 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:13:26.590 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:13:27.062 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:13:27.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:27.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:27.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:27.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:27.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:27.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:27.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:27.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:27.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:27.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:27.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:27.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:27.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:27.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:27.478 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:27.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:27.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:27.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:27.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:27.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:27.478 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:32.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:32.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:32.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:32.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:32.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:32.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:32.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:32.494 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:32.494 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:32.494 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:32.495 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:32.500 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:32.500 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:32.501 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:32.501 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:32.501 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:32.502 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:32.502 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:32.502 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:32.505 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:32.505 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:32.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:32.505 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:32.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:32.506 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:32.506 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:32.506 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:32.508 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:32.508 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:32.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:32.509 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:32.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:32.509 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:32.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:32.509 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:32.512 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:32.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:32.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:32.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:32.512 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:32.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:13:32.513 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:13:32.513 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:32.513 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:32.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:32.518 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:32.996 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:33.035 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:33.037 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:33.039 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:33.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:33.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:33.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:33.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:33.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:33.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:33.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:33.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:33.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:33.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:33.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:33.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:33.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:33.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:33.468 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:33.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:33.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:33.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:33.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:33.940 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:34.413 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:34.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:34.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:34.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:34.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:34.885 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:35.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:35.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:35.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:35.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:35.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:35.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:35.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:35.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:35.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:35.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:35.240 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:35.240 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:35.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:35.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:35.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:35.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:35.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:35.357 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:13:35.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:35.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:35.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:35.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:35.829 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:13:36.299 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:13:36.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:36.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:36.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:36.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:36.773 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:13:37.245 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:13:37.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:37.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:37.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:37.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:37.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:37.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:37.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:37.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:37.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:37.382 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:37.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:37.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:37.382 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:37.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:37.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:42.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:42.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:42.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:42.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:42.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:42.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:42.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:42.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:42.392 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:42.392 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:42.393 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:42.393 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:42.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:42.393 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:42.393 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.394 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:42.394 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:42.394 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:42.394 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:42.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:42.394 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:42.394 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:42.395 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:42.396 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:42.396 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:42.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:42.396 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:42.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:42.396 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.396 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:42.396 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:13:42.398 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:13:42.398 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:42.398 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:42.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:42.403 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:42.881 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:42.923 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:42.926 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:42.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:42.928 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:42.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:42.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:42.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:42.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:42.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:42.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:42.954 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:42.954 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:42.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:42.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:42.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:42.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:42.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:43.354 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:43.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:43.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:43.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:43.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:43.825 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:44.296 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:44.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:44.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:44.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:44.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:44.766 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:45.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:45.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:45.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:45.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:45.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:45.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:45.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:45.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:45.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:45.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:45.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:45.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:45.177 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:45.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:45.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:45.178 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:45.178 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:45.178 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:45.178 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:45.178 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:45.178 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:50.180 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:50.180 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:50.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:50.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:50.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:50.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:50.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:50.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:50.188 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:50.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:50.188 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:50.192 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:50.192 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:50.193 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:50.193 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:50.193 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:50.194 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:50.194 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:50.194 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:50.196 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:50.196 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:50.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:50.197 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:50.197 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:50.197 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:50.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:50.198 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:50.199 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:50.200 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:50.200 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:50.200 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:50.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:50.200 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:50.200 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:50.200 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:50.203 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:50.203 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:13:50.204 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:13:50.204 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:50.204 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:50.209 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:50.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:50.731 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:50.734 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:50.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:50.736 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:50.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:50.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:50.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:50.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:50.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:50.752 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:50.752 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:50.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:50.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:50.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:50.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:50.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:51.156 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:51.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:51.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:51.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:51.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:51.629 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:52.102 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:13:52.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:52.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:52.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:52.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:52.572 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:13:53.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:53.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:53.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:53.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:53.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:53.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:53.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:53.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:53.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:53.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:53.020 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:53.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:53.020 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:53.020 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:53.020 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:13:53.020 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=609 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:53.020 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=609 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:53.020 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=609 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:53.020 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=609 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:53.020 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=609 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:53.020 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=609 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:13:58.025 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:58.025 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:58.025 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:58.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:58.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:58.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:58.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:58.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:58.033 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:58.034 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:13:58.034 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:13:58.037 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:13:58.037 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:13:58.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:58.038 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:58.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:58.038 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:13:58.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:13:58.038 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:13:58.042 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:13:58.043 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:13:58.043 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:58.043 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:58.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:58.043 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:13:58.043 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:13:58.043 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:13:58.047 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:13:58.048 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:13:58.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:58.048 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:13:58.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:58.048 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:13:58.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:13:58.048 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:13:58.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:13:58.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.056 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:13:58.056 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:13:58.056 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:13:58.056 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:13:58.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:13:58.061 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:13:58.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:13:58.589 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:13:58.591 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:13:58.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:58.593 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:13:58.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:58.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:58.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:58.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:58.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:58.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:58.664 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:58.664 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:58.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:58.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:58.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:58.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:58.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:59.009 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:13:59.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:59.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:59.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:59.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:59.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:59.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:59.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:59.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:59.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:59.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:59.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:13:59.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:59.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:59.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:59.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:13:59.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:13:59.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:59.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:13:59.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:13:59.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:59.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:59.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:13:59.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:13:59.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:13:59.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:13:59.481 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:13:59.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:13:59.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:13:59.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:13:59.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:13:59.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:13:59.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:13:59.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:13:59.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:13:59.490 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:13:59.490 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:13:59.490 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:04.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:04.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:04.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:04.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:04.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:04.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:04.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:04.503 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:04.504 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:04.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:04.504 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:04.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:04.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:04.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:04.507 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:04.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:04.508 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:04.508 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:04.508 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:04.510 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:04.510 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:04.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:04.510 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:04.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:04.510 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:04.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:04.510 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:04.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:04.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:04.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:04.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:04.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:04.512 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:04.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:04.513 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:04.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:04.516 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:04.516 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:04.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:04.520 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:04.998 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:05.042 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:05.044 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:05.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:05.045 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:05.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:05.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:05.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:05.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:05.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:05.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:05.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:05.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:05.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:05.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:05.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.466 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:05.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:05.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:05.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:05.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:05.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:05.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:05.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:05.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:05.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:05.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:05.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:05.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:05.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:05.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:05.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:05.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:05.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:05.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:05.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:05.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:05.937 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:14:05.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:05.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:05.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:05.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:05.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:05.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:05.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:05.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:05.949 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:05.949 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:05.949 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:05.949 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:10.954 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:10.954 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:10.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:10.955 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:10.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:10.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:10.957 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:10.958 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:10.958 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:10.958 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:10.958 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:10.959 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:10.959 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:10.959 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:10.959 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:10.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:10.959 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:10.959 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:10.959 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:10.960 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:10.960 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:10.960 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:10.960 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:10.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:10.960 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:10.960 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:10.960 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:10.961 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:10.961 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:10.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:10.961 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:10.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:10.962 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:10.962 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:10.962 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:10.964 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:10.964 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:10.964 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:10.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:10.969 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:11.446 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:11.490 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:11.491 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:11.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:11.494 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:11.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:11.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:11.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:11.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:11.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:11.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:11.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:11.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:11.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:11.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:11.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:11.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:11.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:11.912 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:11.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:11.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:11.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:11.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:11.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:11.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:11.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:11.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:11.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:11.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:11.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:11.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:11.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:11.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:11.968 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:11.968 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:11.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:11.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:11.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:11.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:11.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:12.376 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:14:12.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:12.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:12.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:12.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:12.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:12.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:12.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:12.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:12.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:12.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:12.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:12.431 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:12.431 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:12.431 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:12.431 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:12.431 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=320 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:12.431 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=320 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:12.431 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=320 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:12.431 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=320 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:12.431 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=320 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:12.431 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=320 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:12.431 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=320 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:17.435 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:17.435 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:17.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:17.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:17.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:17.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:17.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:17.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:17.452 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:17.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:17.452 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:17.460 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:17.460 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:17.461 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:17.461 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:17.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:17.462 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:17.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:17.462 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:17.464 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:17.465 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:17.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:17.465 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:17.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:17.466 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:17.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:17.466 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:17.468 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:17.468 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:17.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:17.468 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:17.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:17.468 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:17.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:17.468 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:17.471 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:17.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:17.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:17.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:17.471 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:17.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:17.472 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:17.472 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:17.472 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:17.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:17.477 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:17.954 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:17.985 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:17.985 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:17.986 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:17.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:17.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:17.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:17.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:18.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:18.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:18.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:18.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:18.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:18.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:18.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:18.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:18.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:18.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:18.425 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:18.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:18.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:18.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:18.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:18.897 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:14:19.370 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:14:19.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:19.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:19.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:19.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:19.843 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:14:20.316 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:14:20.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:20.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:20.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:20.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:20.788 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:14:21.259 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:14:21.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:21.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:21.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:21.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:21.732 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:14:22.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:22.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:22.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:22.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:22.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:22.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:22.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:22.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:22.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:22.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:22.060 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:22.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:22.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:27.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:27.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:27.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:27.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:27.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:27.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:27.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:27.076 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:27.077 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.077 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:27.077 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:27.081 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:27.081 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:27.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:27.082 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:27.083 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.083 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:27.083 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:27.085 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:27.085 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:27.085 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:27.085 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:27.085 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:27.086 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:27.087 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:27.087 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:27.088 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:27.088 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:27.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:27.088 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.088 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:27.088 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:27.091 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:27.091 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:27.091 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:27.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:27.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:27.096 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:27.573 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:27.640 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:27.644 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:27.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:27.646 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:27.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:27.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:27.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:27.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:27.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:27.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:27.718 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:27.718 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:27.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:27.765 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:27.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:27.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:27.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:27.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:27.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:27.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:27.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:27.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:27.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:27.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:28.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:28.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:28.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:28.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:28.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:28.046 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:28.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:28.049 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:28.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:28.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:28.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:28.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:28.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:28.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:28.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:28.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:28.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:28.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:28.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:28.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:28.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:28.273 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:28.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:28.273 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:28.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:28.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:28.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:28.273 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=255 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.273 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=255 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.273 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=255 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.273 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=255 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.273 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=255 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:28.273 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=255 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:33.275 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:33.275 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:33.275 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:33.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:33.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:33.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:33.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:33.285 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:33.285 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:33.286 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:33.289 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:33.289 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:33.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:33.289 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:33.290 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:33.290 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:33.292 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:33.293 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:33.293 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:33.293 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:33.293 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.293 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:33.293 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:33.296 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:33.296 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:33.296 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:33.296 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:33.296 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:33.296 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.296 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:33.296 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:33.300 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:33.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:33.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:33.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:33.300 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:33.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:33.301 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:33.301 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:33.301 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:33.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:33.306 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:33.784 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:33.833 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:33.835 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:33.836 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:33.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:33.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:33.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:33.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:33.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:33.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:33.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:33.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:33.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:33.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:33.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:33.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:33.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:33.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:34.256 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:34.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:34.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:34.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:34.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:34.727 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:14:35.201 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:14:35.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:35.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:35.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:35.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:35.673 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:14:36.146 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:14:36.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:36.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:36.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:36.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:36.618 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:14:37.091 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:14:37.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:37.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:37.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:37.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:37.564 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:14:37.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:37.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:37.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:37.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:37.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:37.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:37.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:37.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:37.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:37.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:37.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:37.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:37.944 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:37.944 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1002 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:37.944 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1002 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:37.944 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1002 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:37.944 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1002 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:37.944 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1002 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:37.945 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1002 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:42.945 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:42.945 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:42.945 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:42.945 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:42.945 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:42.945 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:42.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:42.965 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:42.965 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:42.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:42.966 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:42.973 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:42.974 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:42.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:42.975 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:42.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:42.975 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:42.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:42.976 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:42.979 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:42.980 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:42.980 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:42.980 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:42.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:42.981 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:42.982 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:42.982 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:42.984 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:42.984 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:42.984 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:42.984 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:42.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:42.985 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:42.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:42.985 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:42.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:42.989 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:42.990 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:42.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:42.994 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:43.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:43.519 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:43.522 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:43.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:43.523 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:43.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:43.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:43.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:43.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:43.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:43.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:43.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:43.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:43.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:43.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:43.619 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:43.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:43.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:43.943 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:43.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:43.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:43.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:43.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:44.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:44.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:44.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:44.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:44.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:44.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:44.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:44.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:44.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:44.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:44.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:44.351 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:44.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:44.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:44.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:44.351 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:44.351 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:44.351 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:44.351 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:44.351 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:44.351 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:14:49.356 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:49.356 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:49.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:49.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:49.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:49.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:49.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:49.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:49.363 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:49.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:49.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:49.368 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:49.368 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:49.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:49.368 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:49.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:49.369 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:49.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:49.370 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:49.371 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:49.371 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:49.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:49.372 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:49.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:49.372 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:49.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:49.372 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:49.374 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:49.374 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:49.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:49.374 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:49.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:49.374 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:49.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:49.374 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:49.377 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:49.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:49.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:49.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:49.378 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:49.378 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:49.378 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.378 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:49.383 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:49.860 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:49.907 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:49.909 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:49.911 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:49.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:49.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:49.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:49.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:49.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:49.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:49.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:49.986 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:49.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:50.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:50.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:50.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:50.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:50.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:50.332 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:50.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:50.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:50.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:50.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:50.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:50.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:50.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:50.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:50.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:50.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:50.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:50.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:50.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:50.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:50.742 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:50.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:50.742 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:50.742 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:50.742 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:55.746 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:55.746 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:55.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:55.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:55.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:55.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:55.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:55.757 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:55.757 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:55.757 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:14:55.757 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:14:55.761 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:14:55.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:14:55.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:55.762 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:55.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:55.763 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:14:55.764 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:14:55.764 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:14:55.765 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:14:55.766 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:14:55.766 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:55.766 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:55.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:55.766 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:14:55.767 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:14:55.767 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:14:55.768 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:14:55.769 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:14:55.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:55.769 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:14:55.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:55.769 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:14:55.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:14:55.769 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:14:55.772 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:14:55.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:14:55.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:14:55.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:14:55.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:14:55.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:14:55.773 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:14:55.773 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:14:55.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:14:55.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:14:55.778 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:14:56.255 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:14:56.301 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:14:56.303 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:14:56.305 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:14:56.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:56.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:56.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:56.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:14:56.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:56.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:56.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:56.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:14:56.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:14:56.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:56.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:14:56.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:14:56.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:56.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:56.726 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:14:56.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:56.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:56.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:56.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:57.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:14:57.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:14:57.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:14:57.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:14:57.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:14:57.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:14:57.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:14:57.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:14:57.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:14:57.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:14:57.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:14:57.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:14:57.130 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:14:57.130 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:14:57.130 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:14:57.130 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:02.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:02.140 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:02.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:02.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:02.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:02.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:02.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:02.153 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:02.153 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:02.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:02.154 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:02.155 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:02.155 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:02.155 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:02.155 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:02.155 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:02.156 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:02.156 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:02.156 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:02.156 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:02.157 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:02.157 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:02.157 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:02.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:02.157 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:02.157 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:02.157 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:02.158 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:02.158 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:02.158 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:02.158 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:02.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:02.158 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:02.158 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:02.158 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:02.160 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:02.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:02.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:15:02.161 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:15:02.161 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:02.161 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:02.165 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:02.643 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:02.686 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:02.688 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:02.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:02.690 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:02.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:02.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:02.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:15:02.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:02.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:02.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:02.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:15:02.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:15:02.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:02.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:02.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:02.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:02.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:03.111 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:03.163 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:03.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:03.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:03.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:03.585 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:03.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:03.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:03.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:03.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:03.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:03.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:03.650 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:03.650 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:03.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:03.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:03.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:03.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:03.652 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:03.652 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:03.652 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:03.652 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:03.652 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:03.652 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:03.652 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:03.652 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:03.652 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:08.656 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:08.656 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:08.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:08.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:08.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:08.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:08.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:08.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:08.664 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:08.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:08.665 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:08.667 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:08.667 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:08.668 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:08.668 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:08.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:08.668 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:08.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:08.669 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:08.670 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:08.670 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:08.671 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:08.671 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:08.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:08.671 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:08.671 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:08.671 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:08.673 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:08.674 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:08.674 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:08.674 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:08.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:08.674 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:08.674 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:08.674 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:15:08.679 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:15:08.679 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:08.679 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:08.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:08.684 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:09.161 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:09.214 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:09.216 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:09.217 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:09.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:09.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:09.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:09.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:15:09.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:09.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:09.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:09.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:15:09.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:15:09.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:09.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:09.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:09.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:09.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:09.633 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:09.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:09.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:09.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:09.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:10.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:10.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:10.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:10.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:10.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:10.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:10.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:10.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:10.041 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:10.041 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:10.041 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:10.041 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:10.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:10.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:10.041 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:10.041 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:10.041 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:10.041 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:10.041 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:10.041 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:10.041 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:15.045 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:15.045 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:15.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:15.045 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:15.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:15.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:15.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:15.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:15.054 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:15.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:15.054 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:15.057 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:15.058 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:15.058 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:15.058 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:15.058 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:15.058 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:15.058 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:15.058 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:15.062 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:15.062 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:15.062 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:15.062 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:15.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:15.062 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:15.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:15.063 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:15.065 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:15.065 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:15.066 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:15.066 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:15.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:15.066 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:15.066 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:15.066 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:15:15.070 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:15:15.070 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:15.070 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:15.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:15.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:15.075 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:15.553 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:15.601 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:15.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:15.603 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:15.604 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:15.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:15.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:15.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:15:15.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:15.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:15.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:15.648 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:15:15.648 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:15:15.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:15.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:15.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:15.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:15.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:16.025 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:16.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:16.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:16.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:16.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:16.496 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:16.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:16.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:16.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:16.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:16.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:16.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:16.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:16.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:16.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:16.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:16.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:16.567 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:16.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:16.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:16.567 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:21.571 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:21.571 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:21.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:21.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:21.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:21.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:21.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:21.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:21.580 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:21.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:21.580 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:21.582 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:21.583 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:21.583 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:21.583 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:21.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:21.584 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:21.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:21.584 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:21.585 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:21.585 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:21.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:21.585 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:21.585 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:21.585 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:21.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:21.585 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:21.588 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:21.588 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:21.588 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:21.588 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:21.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:21.588 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:21.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:21.589 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:21.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:15:21.592 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:15:21.592 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:21.592 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:21.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:21.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:21.596 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:22.075 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:22.116 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:22.118 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:22.120 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:22.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:22.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:22.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:22.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:15:22.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:22.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:22.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:22.145 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:15:22.145 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:15:22.546 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:22.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:22.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:22.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:22.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:23.018 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:23.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:23.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:23.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:23.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:23.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:23.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:23.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:15:23.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:23.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:23.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:23.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:15:23.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:15:23.489 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:15:23.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:23.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:23.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:23.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:23.960 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:15:24.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:24.433 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:15:24.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:24.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:24.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:24.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:24.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:24.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:24.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:24.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:24.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:24.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:24.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:24.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:24.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:24.483 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:24.483 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:24.483 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:24.484 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:24.484 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:24.484 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:24.484 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:15:29.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:29.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:29.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:29.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:29.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:29.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:29.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:29.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:29.492 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:29.493 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:29.493 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:29.496 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:29.496 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:29.496 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:29.497 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:29.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:29.497 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:29.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:29.498 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:29.500 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:29.500 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:29.500 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:29.500 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:29.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:29.501 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:29.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:29.501 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:29.504 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:29.504 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:29.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:29.504 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:29.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:29.504 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:29.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:29.504 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:29.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:15:29.510 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:15:29.510 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:29.510 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:29.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:29.515 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:29.993 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:30.058 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:30.060 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:30.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:30.060 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:30.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:30.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:30.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:15:30.465 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:30.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:30.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:30.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:30.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:30.940 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:31.412 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:15:31.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:31.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:31.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:31.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:31.883 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:15:32.358 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:15:32.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:32.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:32.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:32.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:32.830 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:15:33.304 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:15:33.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:33.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:33.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:33.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:33.776 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:15:34.248 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:15:34.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:34.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:34.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:34.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:34.720 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:15:35.194 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:15:35.666 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:15:36.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:36.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:36.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:36.091 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:15:36.091 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:15:36.140 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:15:36.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:36.166 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:15:36.166 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:15:36.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:36.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:36.612 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:15:37.076 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:15:37.550 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:15:38.022 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:15:38.490 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:15:38.954 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:15:39.419 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:15:39.883 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:15:40.348 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:15:40.814 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:15:41.279 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:15:41.751 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:15:42.221 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:15:42.686 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:15:43.159 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:15:43.631 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:15:44.105 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:15:44.577 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:15:45.050 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:15:45.523 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:15:45.992 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:15:46.457 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:15:46.928 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:15:47.399 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:15:47.864 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:15:48.329 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:15:48.793 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:15:49.259 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:15:49.723 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:15:50.189 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:15:50.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:15:50.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:15:50.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:50.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:50.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:50.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:50.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:50.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:50.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:50.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:50.534 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:50.534 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:50.534 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:15:50.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:50.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:55.546 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:15:55.546 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:15:55.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:55.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:55.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:55.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:55.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:15:55.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:55.557 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:55.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:15:55.557 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:15:55.560 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:15:55.560 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:15:55.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:55.560 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:55.560 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:15:55.560 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:15:55.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:15:55.560 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:15:55.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:15:55.563 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:15:55.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:55.563 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:55.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:15:55.563 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:15:55.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:15:55.563 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:15:55.565 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:15:55.565 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:15:55.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:55.565 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:15:55.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:15:55.565 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:15:55.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:15:55.565 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:15:55.569 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:15:55.569 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:15:55.569 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:15:55.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:15:55.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:15:55.574 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:15:56.051 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:15:56.100 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:15:56.102 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:15:56.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:15:56.104 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:15:56.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:15:56.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:15:56.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:15:56.523 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:15:56.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:56.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:56.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:56.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:56.997 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:15:57.469 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:15:57.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:57.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:57.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:57.574 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:57.941 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:15:58.417 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:15:58.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:58.575 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:58.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:58.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:58.888 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:15:59.359 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:15:59.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:15:59.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:15:59.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:15:59.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:15:59.835 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:16:00.306 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:16:00.578 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:00.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:00.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:00.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:00.781 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:16:01.253 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:16:01.717 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:16:02.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:02.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:02.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:02.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:16:02.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:16:02.180 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:16:02.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:02.204 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:02.205 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:02.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:02.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:02.652 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:16:03.120 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:16:03.584 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:16:04.048 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:16:04.513 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:16:04.978 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:16:05.443 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:16:05.907 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:16:06.373 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:16:06.845 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:16:07.318 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:16:07.791 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:16:08.263 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:16:08.737 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:16:08.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:08.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:08.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:08.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:16:08.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:08.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:08.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:08.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:08.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:08.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:08.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:16:08.938 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:08.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:08.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:08.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:08.939 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2902 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:08.939 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2902 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:08.939 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2902 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:08.939 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2902 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:08.939 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2902 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:08.939 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2902 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:13.943 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:13.943 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:16:13.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:13.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:13.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:13.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:13.951 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:13.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:13.952 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:13.953 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:13.953 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:13.957 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:13.957 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:13.957 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:13.957 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:13.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:13.958 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:13.958 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:13.958 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:13.962 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:13.963 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:13.963 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:13.963 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:13.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:13.963 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:13.963 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:13.963 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:13.967 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:13.968 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:13.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:13.968 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:13.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:13.968 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:13.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:13.968 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:13.974 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:13.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:13.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:13.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:13.974 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.975 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:16:13.975 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:16:13.975 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:13.975 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:13.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:13.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:13.980 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:16:14.456 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:16:14.510 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:16:14.513 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:16:14.514 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:16:14.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:16:14.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:14.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:16:14.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:16:14.928 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:16:14.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:14.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:14.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:14.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:15.402 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:16:15.874 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:16:15.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:15.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:15.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:15.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:16.346 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:16:16.817 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:16:16.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:16.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:16.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:16.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:17.292 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:16:17.764 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:16:17.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:17.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:17.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:17.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:18.239 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:16:18.715 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:16:18.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:18.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:18.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:18.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:19.186 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:16:19.658 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:16:20.133 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:16:20.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:20.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:20.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:20.545 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:16:20.545 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:16:20.605 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:16:20.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:20.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:20.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:20.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:20.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:21.079 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:16:21.552 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:16:22.024 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:16:22.498 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:16:22.970 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:16:23.442 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:16:23.916 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:16:24.388 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:16:24.861 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:16:25.335 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:16:25.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:25.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:25.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:25.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:16:25.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:25.499 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:25.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:25.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:25.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:25.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:25.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:25.504 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:16:25.504 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:25.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:25.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:25.505 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:25.505 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:25.505 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:25.505 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:25.505 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:25.505 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:30.507 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:30.507 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:16:30.507 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:30.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:30.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:30.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:30.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:30.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:30.515 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:30.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:30.515 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:30.517 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:30.518 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:30.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:30.518 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:30.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:30.519 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:30.519 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:30.519 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:30.521 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:30.521 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:30.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:30.521 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:30.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:30.521 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:30.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:30.521 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:30.524 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:30.524 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:30.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:30.524 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:30.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:30.524 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:30.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:30.524 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:30.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:16:30.529 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:16:30.529 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:30.529 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:30.534 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:16:31.010 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:16:31.060 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:16:31.063 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:16:31.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:16:31.065 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:16:31.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:31.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:16:31.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:16:31.484 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:16:31.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:31.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:31.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:31.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:31.957 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:16:32.429 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:16:32.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:32.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:32.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:32.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:32.899 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:16:33.365 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:16:33.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:33.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:33.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:33.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:33.837 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:16:34.308 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:16:34.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:34.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:34.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:34.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:34.779 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:16:35.255 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:16:35.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:35.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:35.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:35.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:35.730 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:16:36.202 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:16:36.674 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:16:37.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:37.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:37.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:37.104 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:16:37.104 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:16:37.150 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:16:37.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:37.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:37.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:37.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:37.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:37.623 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:16:38.092 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:16:38.563 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:16:39.030 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:16:39.495 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:16:39.967 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:16:40.441 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:16:40.908 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:16:41.379 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:16:41.853 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:16:42.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:42.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:42.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:42.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:16:42.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:42.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:42.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:42.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:42.017 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:42.017 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:42.017 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:16:42.017 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:42.017 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:42.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:42.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:42.017 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:42.017 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:42.017 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:42.017 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:42.017 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:42.017 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:47.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:47.022 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:16:47.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:47.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:47.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:47.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:47.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:47.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:47.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:47.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:16:47.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:16:47.038 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:16:47.039 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:16:47.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:47.039 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:47.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:47.040 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:16:47.040 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:16:47.040 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:16:47.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:16:47.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:16:47.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:47.045 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:47.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:47.045 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:16:47.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:16:47.045 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:16:47.049 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:16:47.049 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:16:47.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:47.049 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:16:47.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:47.049 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:16:47.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:16:47.049 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:16:47.054 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:16:47.054 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:16:47.054 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:16:47.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:16:47.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:16:47.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:16:47.059 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:16:47.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:16:47.583 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:16:47.586 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:16:47.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:16:47.588 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:16:47.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:47.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:16:47.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:16:48.009 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:16:48.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:48.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:48.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:48.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:48.485 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:16:48.957 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:16:49.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:49.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:49.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:49.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:49.432 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:16:49.904 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:16:50.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:50.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:50.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:50.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:50.379 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:16:50.851 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:16:51.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:51.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:51.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:51.063 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:51.327 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:16:51.799 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:16:52.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:52.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:52.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:52.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:52.273 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:16:52.745 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:16:53.220 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:16:53.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:53.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:53.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:53.624 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:16:53.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:16:53.693 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:16:53.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:53.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:16:53.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:16:53.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:53.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:54.166 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:16:54.639 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:16:55.111 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:16:55.580 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:16:56.048 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:16:56.513 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:16:56.980 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:16:57.452 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:16:57.917 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:16:58.382 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:16:58.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:16:58.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:16:58.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:16:58.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:16:58.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:16:58.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:16:58.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:16:58.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:16:58.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:16:58.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:16:58.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:16:58.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:16:58.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:16:58.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:16:58.549 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:16:58.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2486 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:16:58.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2487 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:03.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:03.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:03.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:03.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:03.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:03.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:03.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:03.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:03.560 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:03.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:03.561 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:03.566 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:03.566 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:03.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:03.566 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:03.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:03.566 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:03.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:03.566 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:03.569 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:03.569 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:03.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:03.570 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:03.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:03.570 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:03.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:03.570 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:03.572 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:03.573 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:03.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:03.573 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:03.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:03.573 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:03.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:03.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:03.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:17:03.577 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:17:03.577 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:03.577 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:03.581 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:17:04.060 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:17:04.109 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:17:04.113 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:17:04.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:17:04.114 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:17:04.531 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:17:04.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:04.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:04.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:04.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:05.007 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:17:05.479 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:17:05.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:05.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:05.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:05.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:05.950 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:17:06.425 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:17:06.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:06.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:06.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:06.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:06.897 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:17:07.362 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:17:07.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:07.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:07.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:07.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:07.834 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:17:08.306 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:17:08.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:08.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:08.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:08.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:08.781 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:17:09.253 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:17:09.729 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:17:10.201 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:17:10.676 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:17:11.148 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:17:11.623 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:17:12.087 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:17:12.557 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:17:13.032 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:17:13.504 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:17:13.978 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:17:14.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:14.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:14.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:14.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:14.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:14.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:14.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:14.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:14.128 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:14.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:14.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:19.133 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:19.133 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:19.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:19.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:19.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:19.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:19.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:19.141 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:19.141 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:19.141 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:19.141 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:19.142 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:19.142 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:19.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:19.142 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:19.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:19.142 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:19.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:19.142 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:19.144 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:19.145 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:19.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:19.145 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:19.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:19.145 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:19.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:19.145 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:19.147 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:19.147 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:19.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:19.147 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:19.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:19.147 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:19.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:19.147 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:17:19.149 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:17:19.149 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:19.149 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:19.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:19.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:19.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:19.151 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:19.151 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:19.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:19.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:19.151 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:24.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:24.159 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:24.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:24.159 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:24.159 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:24.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:24.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:24.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:24.167 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:24.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:24.167 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:24.170 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:24.170 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:24.171 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:24.171 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:24.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:24.172 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:24.172 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:24.172 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:24.174 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:24.175 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:24.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:24.175 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:24.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:24.176 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:24.176 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:24.176 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:24.178 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:24.179 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:24.179 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:24.179 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:24.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:24.179 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:24.180 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:24.180 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:24.184 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:24.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:24.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:24.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:24.184 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:24.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:17:24.185 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:17:24.185 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:24.185 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:24.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:24.190 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:17:24.668 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:17:24.717 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:17:24.719 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:17:24.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:17:24.721 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:17:24.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:24.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:17:24.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:17:24.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:17:24.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:17:24.725 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:17:24.725 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:17:24.725 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:17:25.140 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:17:25.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:25.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:25.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:25.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:25.612 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:17:26.085 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:17:26.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:26.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:26.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:26.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:26.557 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:17:27.030 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:17:27.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:27.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:27.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:27.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:27.500 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:17:27.974 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:17:28.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:28.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:28.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:28.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:28.446 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:17:28.918 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:17:29.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:29.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:29.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:29.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:29.389 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:17:29.863 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:17:30.335 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:17:30.807 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:17:31.278 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:17:31.752 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:17:32.224 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:17:32.696 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:17:32.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:32.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:17:32.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:32.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:32.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:32.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:32.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:32.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:32.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:32.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:32.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:32.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:32.773 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:32.773 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:32.773 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:32.773 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:32.773 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:32.773 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:32.773 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:37.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:37.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:37.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:37.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:37.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:37.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:37.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:37.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:37.782 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:37.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:37.782 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:37.785 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:37.785 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:37.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:37.785 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:37.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:37.786 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:37.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:37.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:37.788 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:37.788 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:37.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:37.788 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:37.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:37.788 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:37.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:37.789 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:37.790 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:37.790 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:37.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:37.790 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:37.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:37.790 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:37.791 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:37.791 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:37.793 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:37.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:37.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:37.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:37.793 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:17:37.794 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:17:37.794 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:37.794 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:37.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:37.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:37.796 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:37.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:37.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:42.803 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:42.803 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:42.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:42.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:42.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:42.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:42.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:42.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:42.813 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:42.813 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:42.813 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:42.817 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:42.817 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:42.817 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:42.818 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:42.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:42.818 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:42.819 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:42.819 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:42.821 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:42.821 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:42.821 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:42.821 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:42.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:42.822 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:42.822 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:42.822 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:42.824 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:42.824 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:42.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:42.824 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:42.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:42.825 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:42.825 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:42.825 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.828 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:17:42.828 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:17:42.828 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:42.829 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:42.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:42.833 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:17:43.312 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:17:43.355 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:17:43.356 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:17:43.357 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:17:43.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:17:43.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:43.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:17:43.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:17:43.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:17:43.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:17:43.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:17:43.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:17:43.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:17:43.784 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:17:43.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:43.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:43.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:43.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:44.255 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:17:44.729 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:17:44.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:44.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:44.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:44.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:45.201 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:17:45.673 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:17:45.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:45.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:45.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:45.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:46.144 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:17:46.618 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:17:46.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:46.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:46.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:46.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:47.090 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:17:47.562 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:17:47.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:47.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:47.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:47.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:48.033 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:17:48.506 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:17:48.979 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:17:49.451 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:17:49.922 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:17:50.395 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:17:50.867 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:17:51.339 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:17:51.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:17:51.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:17:51.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:17:51.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:17:51.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:17:51.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:17:51.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:51.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:51.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:51.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:51.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:51.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:51.415 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:51.415 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:51.415 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:51.415 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:51.415 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:17:56.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:56.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:56.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:56.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:56.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:56.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:56.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:56.429 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:56.429 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:56.429 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:17:56.430 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:17:56.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:17:56.434 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:17:56.434 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:56.434 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:56.435 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:17:56.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:56.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:17:56.435 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:17:56.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:17:56.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:17:56.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:56.439 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:56.439 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:17:56.439 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:17:56.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:17:56.439 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:17:56.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:17:56.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:17:56.443 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:56.443 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:17:56.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:17:56.443 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:17:56.443 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:17:56.443 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:56.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:17:56.448 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:17:56.448 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:17:56.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:17:56.451 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:17:56.451 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:17:56.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.457 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:01.457 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:01.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:01.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:01.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:01.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:01.464 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:01.465 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:01.465 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:01.465 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:01.465 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:01.469 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:01.469 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:01.469 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:01.469 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:01.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:01.470 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:01.470 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:01.470 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:01.473 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:01.473 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:01.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:01.473 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:01.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:01.474 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:01.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:01.474 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:01.477 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:01.477 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:01.477 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:01.477 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:01.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:01.477 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:01.478 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:01.478 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:01.482 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:01.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:01.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:01.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:01.482 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:18:01.483 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:18:01.483 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:01.483 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:01.488 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:18:01.965 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:18:02.017 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:18:02.019 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:18:02.020 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:18:02.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:18:02.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:02.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:18:02.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:18:02.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:18:02.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:18:02.023 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:18:02.023 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:18:02.023 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:18:02.437 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:18:02.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:02.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:02.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:02.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:02.908 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:18:03.379 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:18:03.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:03.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:03.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:03.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:03.850 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:18:04.324 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:18:04.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:04.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:04.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:04.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:04.796 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:18:05.268 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:18:05.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:05.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:05.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:05.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:05.739 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:18:06.212 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:18:06.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:06.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:06.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:06.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:06.685 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:18:07.157 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:18:07.627 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:18:08.098 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:18:08.569 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:18:09.043 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:18:09.515 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:18:09.987 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:18:10.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:10.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:18:10.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:10.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:10.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:10.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:10.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:10.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:10.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:10.069 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:10.069 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:10.069 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:10.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:10.070 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:10.070 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:10.070 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:10.070 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:10.070 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:10.070 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:10.070 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:15.072 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:15.072 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:15.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:15.072 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:15.072 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:15.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:15.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:15.076 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:15.076 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:15.076 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:15.076 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:15.077 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:15.077 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:15.077 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:15.077 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:15.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:15.077 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:15.077 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:15.077 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:15.078 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:15.078 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:15.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:15.078 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:15.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:15.078 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:15.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:15.078 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:15.079 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:15.079 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:15.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:15.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:15.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:15.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:15.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:15.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:15.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:18:15.082 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:18:15.082 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:15.082 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:15.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:15.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:15.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:15.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:15.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:15.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:15.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:15.083 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:20.090 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:20.090 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:20.090 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:20.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:20.090 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:20.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:20.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:20.102 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:20.102 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:20.102 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:20.102 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:20.109 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:20.109 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:20.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:20.110 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:20.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:20.111 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:20.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:20.111 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:20.114 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:20.114 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:20.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:20.115 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:20.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:20.115 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:20.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:20.115 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:20.118 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:20.119 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:20.119 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:20.119 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:20.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:20.119 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:20.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:20.120 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:20.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:18:20.126 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:18:20.126 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:20.126 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:20.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:20.131 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:18:20.609 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:18:20.655 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:18:20.657 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:18:20.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:18:20.659 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:18:20.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:20.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:18:20.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:18:20.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:18:20.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:18:20.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:18:20.664 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:18:20.664 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:18:21.081 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:18:21.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:21.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:21.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:21.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:21.552 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:18:22.026 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:18:22.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:22.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:22.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:22.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:22.498 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:18:22.970 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:18:23.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:23.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:23.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:23.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:23.442 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:18:23.915 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:18:24.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:24.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:24.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:24.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:24.387 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:18:24.859 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:18:25.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:25.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:25.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:25.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:25.330 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:18:25.804 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:18:26.276 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:18:26.748 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:18:27.219 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:18:27.692 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:18:28.165 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:18:28.636 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:18:28.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:28.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:18:28.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:28.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:28.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:28.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:28.712 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:28.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:28.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:28.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:28.712 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:28.712 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:28.712 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:28.712 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:28.712 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:28.712 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:28.712 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:28.712 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:28.712 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:33.720 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:33.720 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:33.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:33.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:33.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:33.721 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:33.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:33.731 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:33.731 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:33.731 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:33.731 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:33.732 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:33.732 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:33.733 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:33.733 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:33.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:33.733 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:33.733 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:33.733 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:33.734 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:33.734 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:33.734 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:33.734 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:33.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:33.734 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:33.734 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:33.734 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:33.735 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:33.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:33.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:33.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:33.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:33.736 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:33.736 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:33.736 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:33.737 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:33.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:33.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:33.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:33.737 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:18:33.738 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:18:33.738 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:33.738 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:33.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:33.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:33.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:33.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:33.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:33.739 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:33.739 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:38.746 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:38.746 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:38.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:38.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:38.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:38.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:38.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:38.756 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:38.756 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:38.756 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:38.756 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:38.759 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:38.759 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:38.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:38.760 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:38.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:38.760 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:38.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:38.761 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:38.762 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:38.762 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:38.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:38.762 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:38.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:38.762 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:38.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:38.762 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:38.764 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:38.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:38.765 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:38.765 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:38.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:38.765 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:38.765 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:38.765 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:38.767 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:38.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:38.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:38.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:38.767 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:18:38.768 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:18:38.768 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:38.768 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:38.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:38.773 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:18:39.251 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:18:39.285 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:18:39.285 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:18:39.286 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:18:39.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:18:39.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:39.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:18:39.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:18:39.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:18:39.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:18:39.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:18:39.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:18:39.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:18:39.722 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:18:39.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:39.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:39.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:39.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:40.194 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:18:40.665 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:18:40.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:40.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:40.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:40.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:41.138 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:18:41.610 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:18:41.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:41.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:41.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:41.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:42.082 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:18:42.553 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:18:42.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:42.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:42.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:42.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:43.024 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:18:43.497 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:18:43.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:43.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:43.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:43.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:43.970 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:18:44.442 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:18:44.915 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:18:45.388 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:18:45.860 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:18:46.331 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:18:46.802 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:18:47.275 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:18:47.747 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:18:48.219 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:18:48.690 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:18:49.164 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:18:49.636 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:18:50.108 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:18:50.579 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:18:51.052 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:18:51.525 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:18:51.997 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:18:52.468 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:18:52.941 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:18:53.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:18:53.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:18:53.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:18:53.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:18:53.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:18:53.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:18:53.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:53.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:53.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:53.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:53.306 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:53.306 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:53.306 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:53.306 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:53.306 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:53.306 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:53.306 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:18:58.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:58.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:58.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:58.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:58.311 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:58.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:58.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:58.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:58.319 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:58.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:18:58.319 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:18:58.322 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:18:58.322 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:18:58.323 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:58.323 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:58.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:58.323 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:18:58.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:18:58.324 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:18:58.326 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:18:58.326 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:18:58.326 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:58.326 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:58.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:18:58.326 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:18:58.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:18:58.327 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:18:58.329 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:18:58.329 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:18:58.329 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:58.329 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:18:58.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:18:58.329 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:18:58.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:18:58.330 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:18:58.334 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:18:58.335 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:18:58.335 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:18:58.335 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:18:58.337 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:18:58.337 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:18:58.338 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:18:58.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:18:58.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:03.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:03.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:03.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:03.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:03.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:03.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:03.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:03.354 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:03.354 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:03.354 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:03.355 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:03.358 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:03.358 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:03.359 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:03.359 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:03.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:03.359 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:03.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:03.360 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:03.362 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:03.362 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:03.362 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:03.363 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:03.363 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:03.363 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:03.364 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:03.364 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:03.365 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:03.365 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:03.365 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:03.365 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:03.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:03.365 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:03.366 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:03.366 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.369 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:19:03.369 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:19:03.369 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:03.370 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:03.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:03.374 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:19:03.852 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:19:03.895 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:19:03.896 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:19:03.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:19:03.897 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:19:03.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:03.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:19:03.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:19:03.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:19:03.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:19:03.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:19:03.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:19:03.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:19:04.324 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:19:04.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:04.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:04.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:04.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:04.795 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:19:05.268 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:19:05.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:05.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:05.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:05.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:05.741 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:19:06.213 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:19:06.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:06.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:06.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:06.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:06.684 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:19:07.157 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:19:07.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:07.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:07.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:07.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:07.629 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:19:08.101 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:19:08.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:08.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:08.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:08.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:08.572 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:19:09.043 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:19:09.516 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:19:09.989 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:19:10.461 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:19:10.932 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:19:11.405 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:19:11.878 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:19:11.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:11.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:19:11.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:11.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:11.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:11.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:11.956 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:11.956 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:11.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:11.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:11.956 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:11.956 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:11.956 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.957 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:11.958 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:16.959 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:16.959 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:16.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:16.959 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:16.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:16.959 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:16.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:16.967 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:16.967 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:16.968 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:16.968 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:16.970 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:16.971 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:16.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:16.971 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:16.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:16.972 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:16.972 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:16.972 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:16.973 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:16.973 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:16.974 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:16.974 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:16.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:16.974 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:16.974 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:16.974 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:16.976 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:16.976 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:16.976 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:16.976 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:16.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:16.976 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:16.976 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:16.976 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.979 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:19:16.979 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:19:16.979 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:16.980 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:16.981 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:16.981 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:16.981 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:21.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:21.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:21.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:21.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:21.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:21.990 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:21.995 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:21.997 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:21.997 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:21.997 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:21.997 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:22.000 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:22.001 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:22.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:22.001 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:22.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:22.002 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:22.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:22.002 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:22.004 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:22.004 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:22.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:22.005 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:22.005 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:22.005 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:22.005 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:22.005 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:22.007 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:22.007 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:22.008 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:22.008 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:22.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:22.008 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:22.008 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:22.008 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.012 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:19:22.012 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:19:22.012 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:22.013 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:22.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:22.017 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:19:22.496 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:19:22.536 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:19:22.539 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:19:22.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:19:22.539 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:19:22.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:22.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:19:22.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:19:22.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:19:22.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:19:22.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:19:22.541 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:19:22.541 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:19:22.968 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:19:23.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:23.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:23.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:23.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:23.440 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:19:23.913 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:19:24.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:24.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:24.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:24.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:24.385 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:19:24.857 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:19:25.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:25.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:25.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:25.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:25.328 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:19:25.799 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:19:26.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:26.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:26.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:26.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:26.272 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:19:26.745 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:19:27.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:27.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:27.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:27.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:27.217 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:19:27.688 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:19:28.161 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:19:28.633 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:19:29.105 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:19:29.576 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:19:30.049 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:19:30.522 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:19:30.994 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:19:31.465 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:19:31.936 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:19:32.409 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:19:32.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:32.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:19:32.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:32.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:32.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:32.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:32.600 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:32.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:32.600 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:32.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:32.600 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:32.600 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:32.600 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:32.600 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:32.600 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:32.600 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:32.600 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:32.600 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:32.600 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:37.603 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:37.603 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:37.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:37.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:37.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:37.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:37.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:37.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:37.611 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:37.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:37.611 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:37.614 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:37.614 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:37.614 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:37.614 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:37.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:37.614 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:37.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:37.615 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:37.618 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:37.618 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:37.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:37.618 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:37.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:37.618 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:37.619 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:37.619 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:37.622 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:37.622 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:37.622 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:37.622 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:37.622 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:37.622 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:37.622 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:37.622 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:37.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:19:37.627 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:19:37.627 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:37.627 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:37.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:37.628 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:37.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:42.636 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:42.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:42.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:42.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:42.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:42.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:42.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:42.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:42.640 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:42.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:42.640 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:42.641 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:42.641 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:42.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:42.641 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:42.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:42.641 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:42.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:42.641 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:42.642 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:42.642 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:42.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:42.642 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:42.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:42.642 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:42.642 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:42.642 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:42.643 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:42.643 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:42.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:42.643 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:42.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:42.644 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:42.644 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:42.644 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:42.645 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:42.645 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:42.645 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:42.645 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:42.645 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:19:42.646 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:19:42.646 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:42.646 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:42.650 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:19:43.126 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:19:43.166 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:19:43.167 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:19:43.167 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:19:43.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:19:43.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:43.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:19:43.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:19:43.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:19:43.169 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:19:43.169 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:19:43.169 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:19:43.169 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:19:43.598 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:19:43.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:43.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:43.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:43.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:44.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:19:44.543 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:19:44.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:44.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:44.651 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:44.651 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:45.015 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:19:45.487 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:19:45.652 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:45.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:45.652 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:45.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:45.958 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:19:46.432 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:19:46.653 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:46.653 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:46.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:46.654 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:46.904 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:19:47.376 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:19:47.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:47.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:47.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:47.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:47.847 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:19:48.318 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:19:48.791 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:19:49.264 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:19:49.735 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:19:50.207 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:19:50.678 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:19:51.151 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:19:51.623 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:19:52.095 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:19:52.566 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:19:53.037 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:19:53.510 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:19:53.983 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:19:54.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:19:54.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:19:54.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:19:54.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:19:54.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:19:54.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:19:54.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:54.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:54.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:54.230 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:19:54.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:54.230 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:54.230 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:54.230 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2503 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:54.230 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2503 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:54.230 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2503 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:54.230 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2503 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:54.230 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2503 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:54.230 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2503 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:54.230 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2503 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:19:59.232 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:59.232 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:59.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:59.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:59.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:59.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:59.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:59.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:59.239 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:59.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:19:59.239 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:19:59.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:19:59.243 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:19:59.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:59.244 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:59.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:59.244 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:19:59.245 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:19:59.245 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:19:59.247 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:19:59.247 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:19:59.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:59.247 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:59.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:59.248 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:19:59.248 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:19:59.248 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:19:59.250 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:19:59.251 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:19:59.251 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:59.251 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:19:59.251 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:59.251 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:19:59.251 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:19:59.251 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.255 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:19:59.255 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:19:59.255 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:19:59.255 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:19:59.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:19:59.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:19:59.257 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:04.265 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:04.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:04.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:04.265 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:04.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:04.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:04.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:04.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:04.274 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:04.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:04.274 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:04.280 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:04.281 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:04.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:04.281 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:04.282 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:04.282 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:04.283 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:04.283 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:04.285 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:04.285 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:04.285 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:04.285 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:04.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:04.286 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:04.286 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:04.286 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:04.288 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:04.288 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:04.289 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:04.289 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:04.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:04.289 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:04.289 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:04.289 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:04.292 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:04.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:04.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:04.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:04.292 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:04.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:20:04.293 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:20:04.293 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:04.293 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:04.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:04.298 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:20:04.774 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:20:04.821 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:20:04.823 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:20:04.825 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:20:04.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:20:04.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:20:04.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:20:04.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:20:04.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:20:04.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:20:04.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:20:04.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:20:04.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:20:05.246 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:20:05.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:05.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:05.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:05.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:05.717 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:20:06.191 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:20:06.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:06.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:06.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:06.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:06.663 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:20:07.135 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:20:07.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:07.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:07.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:07.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:07.606 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:20:08.079 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:20:08.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:08.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:08.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:08.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:08.552 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:20:09.024 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:20:09.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:09.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:09.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:09.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:09.495 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:20:09.968 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:20:10.441 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:20:10.913 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:20:11.384 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:20:11.857 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:20:12.330 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:20:12.801 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:20:13.273 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:20:13.746 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:20:14.218 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:20:14.690 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:20:15.161 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:20:15.635 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:20:16.107 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:20:16.579 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:20:17.050 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:20:17.524 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:20:17.996 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:20:18.468 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:20:18.939 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:20:19.413 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:20:19.885 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:20:20.357 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:20:20.828 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:20:21.301 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:20:21.773 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:20:22.246 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:20:22.717 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:20:23.190 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:20:23.662 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:20:24.134 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:20:24.605 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:20:24.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:20:24.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:20:24.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:24.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:24.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:24.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:24.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:24.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:24.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:24.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:24.881 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:24.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:24.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:24.881 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:24.881 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:24.881 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:24.881 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:24.881 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:24.881 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:20:29.888 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:29.888 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:29.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:29.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:29.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:29.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:29.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:29.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:29.896 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:29.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:29.896 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:29.899 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:29.900 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:29.900 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:29.900 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:29.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:29.900 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:29.901 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:29.901 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:29.903 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:29.903 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:29.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:29.904 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:29.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:29.904 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:29.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:29.904 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:29.906 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:29.906 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:29.906 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:29.906 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:29.906 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:29.907 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:29.907 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:29.907 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:29.910 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:20:29.910 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:20:29.910 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:29.910 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:29.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:29.912 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:29.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.920 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:34.920 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:34.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:34.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:34.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:34.921 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:34.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:34.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:34.927 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:34.928 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:34.928 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:34.931 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:34.931 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:34.931 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:34.931 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:34.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:34.932 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:34.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:34.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:34.935 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:34.935 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:34.935 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:34.935 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:34.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:34.935 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:34.935 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:34.935 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:34.938 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:34.938 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:34.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:34.938 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:34.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:34.938 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:34.938 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:34.938 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.942 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:20:34.942 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:20:34.942 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:34.942 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:34.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:34.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:34.947 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:20:35.426 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:20:35.475 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:20:35.477 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:20:35.480 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:20:35.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:20:35.898 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:20:35.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:35.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:35.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:35.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:36.373 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:20:36.845 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:20:36.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:36.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:36.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:36.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:37.320 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:20:37.793 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:20:37.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:37.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:37.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:37.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:38.268 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:20:38.740 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:20:38.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:38.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:38.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:38.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:39.214 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:20:39.683 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:20:39.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:39.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:39.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:39.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:40.150 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:20:40.626 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:20:41.098 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:20:41.572 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:20:42.041 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:20:42.505 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:20:42.977 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:20:43.452 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:20:43.924 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:20:44.394 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:20:44.866 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:20:45.341 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:20:45.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:45.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:45.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:45.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:45.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:45.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:45.491 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:45.491 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:45.491 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:45.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:45.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:50.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:50.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:50.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:50.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:50.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:50.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:50.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:50.508 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:50.508 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.508 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:50.508 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:50.512 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:50.513 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:50.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:50.513 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:50.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:50.514 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:50.516 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:50.516 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:50.517 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:50.517 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:50.517 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.517 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:50.517 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:50.519 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:50.519 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:50.519 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:50.519 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:50.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:50.519 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.519 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:50.519 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:50.522 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:50.522 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:50.522 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:50.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:20:50.523 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:20:50.523 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:50.523 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.523 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:50.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:50.525 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:50.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:55.531 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:20:55.531 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:20:55.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:55.531 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:55.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:55.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:55.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:20:55.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:55.541 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:55.541 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:20:55.541 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:20:55.544 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:20:55.544 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:20:55.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:55.544 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:55.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:20:55.545 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:20:55.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:20:55.545 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:20:55.547 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:20:55.547 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:20:55.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:55.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:55.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:20:55.547 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:20:55.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:20:55.547 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:20:55.549 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:20:55.549 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:20:55.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:55.549 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:20:55.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:20:55.549 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:20:55.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:20:55.549 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.552 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:20:55.552 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:20:55.553 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:20:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:20:55.557 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:20:56.035 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:20:56.082 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:20:56.084 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:20:56.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:20:56.086 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:20:56.500 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:20:56.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:56.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:56.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:56.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:56.963 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:20:57.427 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:20:57.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:57.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:57.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:57.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:57.896 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:20:58.360 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:20:58.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:58.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:58.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:58.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:58.829 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:20:59.301 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:20:59.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:20:59.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:20:59.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:20:59.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:20:59.770 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:21:00.241 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:21:00.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:00.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:00.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:00.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:00.711 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:21:01.184 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:21:01.648 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:21:02.111 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:21:02.580 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:21:03.043 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:21:03.516 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:21:03.988 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:21:04.451 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:21:04.915 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:21:05.378 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:21:05.843 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:21:06.308 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:21:06.772 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:21:07.239 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:21:07.712 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:21:08.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:08.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:08.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:08.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:08.104 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:08.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:08.104 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:08.104 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:08.104 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:08.104 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:08.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:13.109 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:13.109 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:13.109 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:13.109 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:13.109 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:13.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:13.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:13.112 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:13.112 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:13.113 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:13.113 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:13.113 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:13.114 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:13.114 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:13.114 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:13.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:13.114 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:13.114 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:13.114 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:13.115 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:13.115 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:13.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:13.115 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:13.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:13.115 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:13.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:13.115 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:13.116 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:13.116 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:13.116 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:13.116 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:13.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:13.116 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:13.116 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:13.116 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:21:13.119 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:21:13.119 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:13.119 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:13.120 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:13.120 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:13.120 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:18.128 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:18.128 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:18.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:18.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:18.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:18.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:18.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:18.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:18.139 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:18.139 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:18.139 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:18.143 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:18.143 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:18.144 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:18.144 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:18.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:18.144 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:18.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:18.145 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:18.146 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:18.147 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:18.147 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:18.147 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:18.147 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:18.147 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:18.147 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:18.147 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:18.149 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:18.150 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:18.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:18.150 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:18.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:18.150 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:18.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:18.150 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:21:18.153 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:21:18.153 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:18.153 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:18.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:18.158 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:21:18.637 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:21:18.681 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:21:18.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:21:18.684 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:21:18.686 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:21:18.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:18.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:21:18.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:21:18.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:18.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:18.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:18.692 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:21:18.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:21:18.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:18.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:18.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:18.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:19.108 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:21:19.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:19.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:19.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:19.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:19.580 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:21:20.051 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:21:20.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:20.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:20.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:20.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:20.524 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:21:20.996 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:21:21.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:21.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:21.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:21.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:21.468 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:21:21.942 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:21:22.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:22.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:22.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:22.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:22.414 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:21:22.886 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:21:23.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:23.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:23.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:23.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:23.357 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:21:23.830 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:21:24.303 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:21:24.775 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:21:25.246 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:21:25.719 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:21:26.191 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:21:26.663 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:21:26.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:26.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:21:26.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:26.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:26.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:26.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:26.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:26.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:26.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:26.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:26.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:26.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:26.736 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:26.736 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:26.736 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:26.736 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:26.736 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:26.736 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:26.736 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:26.736 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:21:31.743 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:31.743 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:31.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:31.743 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:31.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:31.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:31.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:31.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:31.751 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:31.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:31.752 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:31.754 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:31.754 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:31.754 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:31.755 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:31.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:31.755 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:31.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:31.756 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:31.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:31.758 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:31.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:31.759 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:31.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:31.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:31.760 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:31.760 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:31.763 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:31.763 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:31.763 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:31.763 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:31.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:31.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:31.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:31.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:31.768 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:21:31.769 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:21:31.769 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:31.769 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:31.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:31.771 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:31.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:36.779 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:36.779 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:36.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:36.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:36.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:36.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:36.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:36.788 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:36.788 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:36.789 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:36.789 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:36.791 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:36.791 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:36.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:36.792 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:36.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:36.792 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:36.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:36.793 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:36.794 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:36.794 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:36.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:36.794 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:36.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:36.795 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:36.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:36.795 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:36.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:36.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:36.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:36.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:36.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:36.797 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:36.797 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:36.797 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:21:36.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:21:36.800 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:36.800 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:36.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:36.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:21:37.283 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:21:37.326 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:21:37.328 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:21:37.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:21:37.330 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:21:37.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:37.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:21:37.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:21:37.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:37.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:37.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:37.334 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:21:37.334 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:21:37.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:37.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:37.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:37.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:37.755 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:21:37.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:37.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:37.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:37.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:38.226 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:21:38.697 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:21:38.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:38.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:38.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:38.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:39.170 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:21:39.642 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:21:39.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:39.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:39.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:39.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:40.114 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:21:40.585 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:21:40.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:40.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:40.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:40.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:41.058 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:21:41.531 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:21:41.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:41.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:41.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:41.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:42.003 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:21:42.474 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:21:42.945 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:21:43.416 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:21:43.889 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:21:44.360 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:21:44.832 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:21:45.304 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:21:45.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:45.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:21:45.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:45.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:45.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:45.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:45.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:45.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:45.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:45.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:45.384 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:45.384 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:45.384 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:50.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:50.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:50.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:50.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:50.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:50.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:50.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:50.397 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:50.397 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:50.397 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:50.397 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:50.401 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:50.401 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:50.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:50.401 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:50.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:50.402 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:50.403 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:50.403 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:50.405 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:50.405 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:50.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:50.405 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:50.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:50.406 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:50.406 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:50.406 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:50.408 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:50.408 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:50.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:50.408 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:50.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:50.408 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:50.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:50.408 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:50.411 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:50.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:21:50.412 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:21:50.412 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:50.412 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:50.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:50.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:50.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:50.414 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.420 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:21:55.420 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:21:55.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:55.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:55.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:55.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:55.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:21:55.428 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:55.428 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:55.428 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:21:55.429 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:21:55.431 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:21:55.431 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:21:55.431 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:55.431 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:55.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:21:55.432 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:21:55.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:21:55.432 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:21:55.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:21:55.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:21:55.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:55.434 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:55.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:21:55.434 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:21:55.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:21:55.434 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:21:55.435 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:21:55.436 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:21:55.436 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:55.436 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:21:55.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:21:55.436 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:21:55.436 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:21:55.436 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:21:55.438 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:21:55.439 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:21:55.439 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:21:55.439 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:21:55.443 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:21:55.921 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:21:55.963 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:21:55.966 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:21:55.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:21:55.968 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:21:55.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:21:55.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:21:55.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:21:55.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:55.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:55.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:55.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:21:55.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:21:56.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:21:56.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:21:56.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:56.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:21:56.394 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:21:56.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:56.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:56.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:56.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:56.865 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:21:57.338 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:21:57.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:57.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:57.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:57.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:57.811 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:21:58.282 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:21:58.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:58.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:58.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:58.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:58.754 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:21:59.227 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:21:59.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:21:59.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:21:59.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:21:59.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:21:59.699 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:22:00.171 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:22:00.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:00.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:00.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:00.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:00.642 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:22:01.116 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:22:01.587 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:22:02.059 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:22:02.531 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:22:03.001 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:22:03.472 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:22:03.945 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:22:04.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:04.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:22:04.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:04.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:04.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:04.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:04.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:04.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:04.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:04.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:04.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:04.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:04.027 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:04.027 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:04.027 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:04.027 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:04.027 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:04.028 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:04.028 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:09.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:09.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:09.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:09.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:09.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:09.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:09.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:09.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:09.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:09.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:09.037 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:09.040 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:09.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:09.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:09.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:09.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:09.042 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:09.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:09.043 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:09.046 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:09.046 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:09.046 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:09.047 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:09.047 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:09.048 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:09.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:09.048 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:09.050 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:09.051 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:09.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:09.051 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:09.051 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:09.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:09.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:09.051 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:09.056 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:09.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:09.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:09.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:09.056 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:22:09.057 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:22:09.057 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:09.057 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:09.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:09.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:09.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:09.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:09.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:09.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:09.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:09.061 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:14.069 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:14.069 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:14.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:14.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:14.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:14.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:14.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:14.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:14.073 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:14.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:14.073 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:14.074 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:14.074 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:14.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:14.074 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:14.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:14.074 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:14.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:14.074 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:14.075 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:14.075 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:14.075 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:14.075 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:14.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:14.075 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:14.075 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:14.075 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:14.076 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:14.076 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:14.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:14.076 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:14.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:14.076 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:14.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:14.076 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:14.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:22:14.079 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:22:14.079 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:14.079 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:14.083 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:22:14.562 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:22:14.603 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:22:14.605 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:22:14.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:22:14.607 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:22:14.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:14.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:22:14.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:22:14.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:14.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:14.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:14.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:22:14.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:22:14.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:14.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:14.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:14.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:15.033 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:22:15.082 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:15.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:15.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:15.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:15.505 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:22:15.977 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:22:16.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:16.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:16.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:16.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:16.448 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:22:16.921 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:22:17.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:17.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:17.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:17.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:17.394 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:22:17.866 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:22:18.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:18.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:18.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:18.086 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:18.337 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:22:18.808 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:22:19.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:19.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:19.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:19.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:19.281 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:22:19.754 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:22:20.226 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:22:20.697 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:22:21.170 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:22:21.643 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:22:22.115 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:22:22.586 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:22:22.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:22.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:22:22.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:22.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:22.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:22.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:22.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:22.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:22.660 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:22.660 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:22.660 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:22.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:22.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:27.668 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:27.668 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:27.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:27.668 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:27.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:27.668 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:27.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:27.676 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:27.676 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:27.676 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:27.676 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:27.678 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:27.678 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:27.679 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:27.679 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:27.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:27.679 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:27.679 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:27.679 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:27.680 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:27.681 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:27.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:27.681 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:27.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:27.681 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:27.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:27.681 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:27.683 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:27.683 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:27.683 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:27.683 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:27.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:27.683 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:27.683 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:27.683 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:22:27.686 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:22:27.686 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:27.686 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:27.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:27.687 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:27.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:32.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:32.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:32.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:32.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:32.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:32.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:32.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:32.713 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:32.713 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:32.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:32.714 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:32.718 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:32.718 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:32.718 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:32.719 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:32.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:32.719 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:32.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:32.720 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:32.721 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:32.722 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:32.722 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:32.722 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:32.722 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:32.722 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:32.722 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:32.722 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:32.725 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:32.725 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:32.725 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:32.725 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:32.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:32.725 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:32.725 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:32.725 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:32.728 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:22:32.729 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:22:32.729 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:32.729 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:32.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:32.733 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:22:33.211 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:22:33.254 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:22:33.256 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:22:33.259 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:22:33.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:22:33.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:33.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:22:33.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:22:33.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:33.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:33.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:33.263 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:22:33.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:22:33.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:33.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:33.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:33.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:33.684 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:22:33.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:33.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:33.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:33.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:34.155 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:22:34.628 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:22:34.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:34.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:34.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:34.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:35.100 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:22:35.572 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:22:35.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:35.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:35.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:35.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:36.043 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:22:36.517 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:22:36.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:36.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:36.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:36.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:36.989 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:22:37.460 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:22:37.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:37.736 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:37.736 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:37.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:37.932 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:22:38.405 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:22:38.877 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:22:39.349 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:22:39.820 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:22:40.294 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:22:40.766 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:22:41.238 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:22:41.709 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:22:42.182 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:22:42.655 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:22:43.126 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:22:43.597 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:22:44.071 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:22:44.543 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:22:45.015 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:22:45.487 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:22:45.960 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:22:46.432 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:22:46.904 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:22:47.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:47.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:22:47.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:47.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:47.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:47.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:47.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:47.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:47.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:47.310 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:47.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:47.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:47.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:47.310 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3150 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:47.310 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3150 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:47.310 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3150 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:47.310 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3150 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:47.310 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3150 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:47.310 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3150 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:22:52.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:52.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:52.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:52.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:52.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:52.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:52.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:52.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:52.326 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:52.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:52.326 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:52.330 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:52.331 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:52.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:52.331 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:52.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:52.332 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:52.332 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:52.333 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:52.335 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:52.335 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:52.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:52.336 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:52.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:52.336 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:52.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:52.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:52.338 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:52.339 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:52.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:52.339 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:52.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:52.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:52.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:52.340 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:52.342 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:52.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:52.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:52.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:22:52.343 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:22:52.343 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:52.343 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:52.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:52.345 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:52.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:57.354 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:22:57.354 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:22:57.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:57.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:57.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:57.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:57.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:22:57.371 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:57.372 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:57.372 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:22:57.372 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:22:57.375 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:22:57.376 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:22:57.376 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:57.376 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:57.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:22:57.377 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:22:57.378 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:22:57.378 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:22:57.380 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:22:57.380 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:22:57.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:57.380 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:57.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:22:57.381 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:22:57.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:22:57.381 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:22:57.382 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:22:57.383 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:22:57.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:57.383 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:22:57.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:22:57.383 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:22:57.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:22:57.383 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.386 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:22:57.386 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:22:57.386 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:22:57.387 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:22:57.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:22:57.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:22:57.391 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:22:57.870 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:22:57.917 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:22:57.920 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:22:57.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:22:57.924 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:22:57.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:22:57.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:22:57.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:22:57.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:57.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:57.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:57.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:22:57.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:22:57.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:22:57.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:22:57.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:57.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:22:58.342 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:22:58.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:58.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:58.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:58.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:58.813 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:22:59.287 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:22:59.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:22:59.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:22:59.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:22:59.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:22:59.759 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:23:00.231 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:23:00.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:00.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:00.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:00.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:00.702 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:23:01.175 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:23:01.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:01.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:01.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:01.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:01.647 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:23:02.119 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:23:02.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:02.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:02.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:02.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:02.591 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:23:03.064 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:23:03.536 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:23:04.008 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:23:04.479 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:23:04.950 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:23:05.423 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:23:05.895 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:23:05.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:23:05.965 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:23:05.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:05.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:05.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:05.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:05.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:05.972 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:05.972 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:05.972 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:05.972 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:05.972 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:05.972 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:10.977 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:10.977 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:10.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:10.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:10.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:10.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:10.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:10.985 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:10.985 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:10.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:10.986 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:10.990 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:10.990 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:10.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:10.991 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:10.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:10.992 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:10.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:10.992 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:10.994 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:10.994 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:10.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:10.994 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:10.995 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:10.995 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:10.995 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:10.995 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:10.997 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:10.997 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:10.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:10.998 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:10.998 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:10.998 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:10.998 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:10.998 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:11.001 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:11.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:11.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:11.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:11.001 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:23:11.002 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:23:11.002 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:11.002 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:11.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:11.004 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:11.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:16.011 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:16.011 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:16.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:16.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:16.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:16.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:16.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:16.017 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:16.017 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:16.018 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:16.018 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:16.020 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:16.021 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:16.021 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:16.021 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:16.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:16.022 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:16.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:16.022 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:16.023 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:16.024 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:16.024 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:16.024 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:16.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:16.024 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:16.024 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:16.024 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:16.026 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:16.026 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:16.026 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:16.026 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:16.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:16.026 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:16.026 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:16.026 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:23:16.030 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:23:16.030 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:16.030 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:16.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:16.034 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:23:16.513 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:23:16.557 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:23:16.559 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:23:16.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:23:16.562 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:23:16.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:23:16.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:23:16.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:23:16.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:23:16.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:23:16.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:23:16.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:23:16.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:23:16.985 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:23:17.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:17.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:17.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:17.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:17.456 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:23:17.929 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:23:18.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:18.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:18.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:18.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:18.402 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:23:18.874 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:23:19.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:19.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:19.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:19.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:19.345 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:23:19.816 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:23:20.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:20.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:20.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:20.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:20.286 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:23:20.757 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:23:21.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:21.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:21.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:21.038 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:21.228 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:23:21.699 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:23:22.170 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:23:22.643 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:23:23.115 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:23:23.587 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:23:24.058 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:23:24.532 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:23:25.004 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:23:25.476 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:23:25.947 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:23:26.421 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:23:26.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:23:26.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:23:26.616 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:26.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:26.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:26.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:26.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:26.618 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:26.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:26.618 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:26.618 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:26.618 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:26.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:31.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:31.623 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:31.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:31.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:31.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:31.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:31.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:31.634 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:31.634 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:31.634 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:31.634 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:31.636 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:31.636 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:31.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:31.636 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:31.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:31.636 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:31.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:31.636 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:31.638 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:31.638 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:31.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:31.638 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:31.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:31.638 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:31.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:31.638 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:31.639 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:31.639 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:31.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:31.639 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:31.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:31.639 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:31.639 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:31.639 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.641 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:23:31.641 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:23:31.642 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:31.642 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:31.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:31.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:31.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:31.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:31.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:31.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:31.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:31.643 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:36.650 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:36.650 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:36.650 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:36.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:36.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:36.650 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:36.657 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:36.658 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:36.658 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:36.658 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:36.658 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:36.663 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:36.663 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:36.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:36.663 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:36.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:36.664 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:36.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:36.664 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:36.668 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:36.668 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:36.668 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:36.668 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:36.668 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:36.668 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:36.669 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:36.669 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:36.671 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:36.672 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:36.672 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:36.672 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:36.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:36.672 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:36.672 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:36.672 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:23:36.677 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:23:36.677 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:36.677 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:36.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:36.681 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:23:37.160 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:23:37.203 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:23:37.205 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:23:37.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:23:37.208 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:23:37.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:23:37.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:23:37.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:23:37.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:23:37.213 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:23:37.213 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:23:37.214 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:23:37.214 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:23:37.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:23:37.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:23:37.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:23:37.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:23:37.632 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:23:37.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:37.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:37.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:37.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:38.103 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:23:38.576 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:23:38.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:38.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:38.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:38.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:39.049 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:23:39.520 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:23:39.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:39.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:39.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:39.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:39.992 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:23:40.465 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:23:40.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:40.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:40.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:40.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:40.937 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:23:41.409 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:23:41.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:41.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:41.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:41.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:41.880 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:23:42.354 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:23:42.826 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:23:43.298 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:23:43.772 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:23:44.244 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:23:44.716 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:23:45.187 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:23:45.660 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:23:46.133 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:23:46.605 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:23:47.076 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:23:47.547 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:23:48.020 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:23:48.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:23:48.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:23:48.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:48.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:48.259 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:48.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:53.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:53.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:53.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:53.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:53.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:53.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:53.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:53.272 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:53.272 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:53.272 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:53.272 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:53.274 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:53.275 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:53.275 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:53.275 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:53.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:53.276 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:53.277 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:53.277 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:53.279 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:53.279 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:53.279 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:53.280 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:53.280 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:53.281 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:53.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:53.281 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:53.283 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:53.284 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:53.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:53.284 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:53.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:53.284 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:53.284 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:53.284 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.289 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:23:53.289 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:23:53.289 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:53.289 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:53.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:53.292 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:53.292 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:53.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:58.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:23:58.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:23:58.299 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:58.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:58.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:58.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:58.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:23:58.307 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:58.308 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:58.308 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:23:58.308 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:23:58.310 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:23:58.311 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:23:58.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:58.311 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:58.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:23:58.312 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:23:58.312 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:23:58.312 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:23:58.314 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:23:58.314 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:23:58.315 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:58.315 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:58.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:23:58.315 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:23:58.315 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:23:58.315 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:23:58.317 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:23:58.317 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:23:58.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:58.317 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:23:58.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:23:58.317 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:23:58.318 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:23:58.318 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.320 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:23:58.320 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:23:58.320 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:23:58.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:23:58.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:23:58.325 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:23:58.803 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:23:58.850 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:23:58.852 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:23:58.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:23:58.854 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:23:59.275 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:23:59.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:23:59.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:23:59.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:23:59.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:23:59.748 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:24:00.221 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:24:00.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:00.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:00.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:00.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:00.693 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:24:01.164 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:24:01.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:01.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:01.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:01.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:01.638 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:24:02.110 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:24:02.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:02.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:02.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:02.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:02.582 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:24:03.057 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:24:03.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:03.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:03.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:03.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:03.532 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:24:04.004 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:24:04.476 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:24:04.950 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:24:05.422 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:24:05.894 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:24:06.368 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:24:06.840 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:24:07.312 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:24:07.786 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:24:08.258 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:24:08.730 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:24:08.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:08.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:08.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:08.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:08.864 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:08.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:08.864 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:08.864 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:08.864 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:08.864 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:08.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:13.871 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:13.871 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:13.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:13.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:13.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:13.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:13.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:13.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:13.883 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:13.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:13.883 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:13.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:13.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:13.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:13.885 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:13.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:13.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:13.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:13.886 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:13.887 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:13.887 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:13.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:13.887 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:13.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:13.887 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:13.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:13.887 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:13.888 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:13.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:13.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:13.888 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:13.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:13.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:13.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:13.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:24:13.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:24:13.891 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:13.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:13.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:13.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:13.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:13.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:13.892 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:13.892 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:13.892 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:13.892 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:18.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:18.901 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:18.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:18.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:18.901 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:18.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:18.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:18.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:18.911 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:18.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:18.911 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:18.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:18.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:18.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:18.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:18.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:18.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:18.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:18.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:18.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:18.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:18.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:18.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:18.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:18.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:18.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:18.920 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:18.924 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:18.924 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:18.924 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:18.924 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:18.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:18.924 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:18.924 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:18.924 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:18.930 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:24:18.931 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:24:18.931 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:18.931 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:18.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:18.936 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:19.415 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:19.466 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:19.468 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:19.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:19.471 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:19.879 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:24:19.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:19.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:19.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:19.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:20.353 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:24:20.825 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:24:20.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:20.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:20.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:20.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:21.298 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:24:21.771 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:24:21.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:21.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:21.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:21.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:22.246 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:24:22.718 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:24:22.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:22.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:22.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:22.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:23.190 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:24:23.654 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:24:23.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:23.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:23.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:23.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:24.123 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:24:24.593 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:24:25.068 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:24:25.540 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:24:26.015 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:24:26.487 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:24:26.963 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:24:27.435 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:24:27.910 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:24:28.382 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:24:28.857 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:24:29.330 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:24:29.805 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:24:30.281 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:24:30.753 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:24:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:24:31.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:31.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:31.488 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:31.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:31.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:31.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:31.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:31.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:31.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:31.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:31.492 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2710 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2710 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2710 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2710 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.493 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:31.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2711 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:24:36.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:36.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:36.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:36.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:36.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:36.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:36.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:36.503 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:36.504 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:36.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:36.504 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:36.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:36.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:36.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:36.507 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:36.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:36.508 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:36.508 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:36.508 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:36.510 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:36.510 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:36.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:36.510 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:36.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:36.510 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:36.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:36.510 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:36.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:36.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:36.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:36.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:36.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:36.512 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:36.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:36.512 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.515 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:24:36.515 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:24:36.516 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:36.516 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:36.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:36.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:36.520 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:36.999 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:37.035 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:37.036 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:37.037 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:37.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:37.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:37.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:24:37.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:24:37.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:37.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:37.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:37.039 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:24:37.039 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:24:37.470 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:24:37.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:37.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:37.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:37.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:37.942 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:24:38.415 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:24:38.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:38.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:38.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:38.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:38.888 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:24:39.360 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:24:39.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:39.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:39.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:39.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:39.831 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:24:40.304 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:24:40.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:40.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:40.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:40.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:40.776 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:24:41.248 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:24:41.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:41.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:41.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:41.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:41.720 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:24:42.193 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:24:42.665 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:24:43.137 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:24:43.608 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:24:44.082 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:24:44.554 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:24:45.026 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:24:45.497 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:24:45.971 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:24:46.443 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:24:46.915 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:24:47.386 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:24:47.859 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:24:48.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:48.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:24:48.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:48.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:48.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:48.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:48.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:48.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:48.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:48.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:48.053 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:24:48.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:48.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:53.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:24:53.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:24:53.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:53.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:53.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:53.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:53.067 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:24:53.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:53.069 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:53.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:24:53.069 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:24:53.074 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:24:53.074 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:24:53.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:53.074 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:53.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:24:53.074 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:24:53.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:24:53.075 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:24:53.078 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:24:53.078 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:24:53.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:53.078 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:53.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:24:53.079 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:24:53.079 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:24:53.079 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:24:53.082 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:24:53.082 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:24:53.082 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:53.082 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:24:53.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:24:53.082 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:24:53.083 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:24:53.083 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:24:53.089 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:24:53.089 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:24:53.089 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:24:53.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:24:53.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:24:53.093 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:24:53.572 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:24:53.619 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:24:53.621 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:24:53.623 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:24:53.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:24:53.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:24:53.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:24:53.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:24:53.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:24:53.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:24:53.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:24:53.628 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:24:53.628 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:24:54.044 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:24:54.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:54.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:54.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:54.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:54.515 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:24:54.989 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:24:55.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:55.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:55.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:55.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:55.461 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:24:55.933 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:24:56.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:56.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:56.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:56.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:56.413 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:24:56.885 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:24:57.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:57.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:57.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:57.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:57.358 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:24:57.830 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:24:58.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:24:58.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:24:58.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:24:58.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:24:58.302 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:24:58.776 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:24:59.248 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:24:59.720 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:25:00.191 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:25:00.665 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:25:01.137 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:25:01.609 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:25:02.080 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:25:02.554 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:25:03.026 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:25:03.498 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:25:03.969 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:25:04.440 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:25:04.913 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:25:05.385 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:25:05.857 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:25:06.328 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:25:06.801 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:25:07.274 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:25:07.746 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:25:08.217 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:25:08.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:08.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:08.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:08.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:08.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:08.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:08.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:08.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:08.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:08.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:08.676 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:08.676 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:08.676 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:25:13.681 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:13.681 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:13.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:13.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:13.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:13.681 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:13.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:13.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:13.692 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:13.693 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:13.693 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:25:13.697 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:25:13.697 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:25:13.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:13.698 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:13.698 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:25:13.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:13.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:13.698 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:25:13.703 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:25:13.703 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:25:13.703 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:13.703 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:13.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:13.703 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:25:13.703 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:13.703 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:25:13.706 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:25:13.706 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:25:13.706 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:13.706 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:13.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:13.706 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:25:13.707 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:13.707 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.710 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:25:13.710 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:25:13.710 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:25:13.711 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:13.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:13.715 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:25:14.193 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:25:14.239 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:25:14.241 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:25:14.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:14.243 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:25:14.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:14.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:14.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:14.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:14.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:14.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:14.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:14.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:14.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:14.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:14.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:14.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:14.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:14.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:14.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:14.298 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:14.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:14.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:14.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:14.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:14.298 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:25:14.299 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:14.299 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:14.299 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:14.299 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:14.299 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:14.299 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:19.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:19.300 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:19.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:19.301 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:19.301 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:19.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:19.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:19.310 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:19.310 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:19.311 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:19.311 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:25:19.314 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:25:19.315 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:25:19.315 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:19.315 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:19.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:19.316 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:25:19.316 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:19.316 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:25:19.318 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:25:19.318 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:25:19.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:19.319 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:19.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:19.319 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:25:19.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:19.320 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:25:19.321 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:25:19.321 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:25:19.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:19.322 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:19.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:19.322 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:25:19.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:19.322 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:25:19.326 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:25:19.326 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:25:19.326 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:19.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:19.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:19.330 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:25:19.809 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:25:19.855 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:25:19.858 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:25:19.860 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:25:19.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:19.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:19.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:19.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:19.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:19.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:19.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:19.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:19.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:19.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:19.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:19.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:19.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:19.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:19.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:19.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:19.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:20.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:20.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:20.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:20.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:20.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:20.098 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:20.098 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:20.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:20.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:20.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.281 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:25:20.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:20.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:20.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:20.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:20.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:20.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:20.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:20.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:20.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:20.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:20.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:20.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:20.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:20.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:20.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:20.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:20.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:20.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:20.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:20.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:20.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:20.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:20.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:20.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:20.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:20.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:20.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:20.752 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:25:21.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:21.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:21.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:21.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:21.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:21.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:21.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:21.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:21.088 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:21.088 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:21.088 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:21.088 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:25:21.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:21.088 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:21.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:21.088 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=381 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:21.088 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=381 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:21.088 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=381 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:21.088 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:21.088 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:21.088 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:21.088 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:26.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:26.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:26.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:26.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:26.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:26.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:26.103 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:26.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:26.104 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:26.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:26.104 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:25:26.107 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:25:26.107 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:25:26.108 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:26.108 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:26.108 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:26.109 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:25:26.109 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:26.109 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:25:26.111 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:25:26.111 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:25:26.111 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:26.111 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:26.111 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:26.111 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:25:26.111 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:26.111 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:25:26.113 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:25:26.113 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:25:26.114 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:26.114 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:26.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:26.114 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:25:26.114 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:26.114 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:25:26.117 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:25:26.117 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:25:26.117 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:26.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:26.122 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:25:26.601 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:25:26.643 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:25:26.644 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:25:26.645 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:25:26.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:26.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:26.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:26.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:26.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:26.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:26.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:26.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:26.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:26.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:26.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:26.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:26.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:26.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:26.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:26.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:26.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:27.073 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:25:27.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:27.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:27.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:27.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:27.545 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:25:28.018 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:25:28.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:28.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:28.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:28.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:28.491 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:25:28.963 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:25:29.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:29.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:29.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:29.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:29.436 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:25:29.909 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:25:30.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:30.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:30.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:30.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:30.381 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:25:30.855 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:25:31.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:31.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:31.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:31.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:31.327 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:25:31.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:31.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:31.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:31.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:31.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:31.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:31.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:31.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:31.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:31.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:31.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:31.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:31.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:31.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:31.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:31.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:31.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:31.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:31.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:31.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:31.799 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:25:32.270 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:25:32.741 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:25:33.212 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:25:33.685 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:25:34.157 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:25:34.630 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:25:35.103 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:25:35.576 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:25:36.048 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:25:36.519 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:25:36.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:36.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:36.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:36.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:36.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:36.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:36.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:36.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:36.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:36.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:36.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:36.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:36.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:36.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:36.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:36.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:36.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:36.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:36.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:36.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:36.989 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:25:37.460 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:25:37.934 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:25:38.406 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:25:38.878 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:25:39.349 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:25:39.820 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:25:40.293 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:25:40.765 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:25:41.237 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:25:41.708 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:25:41.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:41.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:41.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:41.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:41.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:41.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:41.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:41.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:41.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:41.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:41.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:41.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:41.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:41.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:41.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:41.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:41.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:41.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:41.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:41.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:42.179 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:25:42.650 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:25:43.124 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:25:43.596 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:25:44.068 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:25:44.539 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:25:45.012 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:25:45.485 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:25:45.956 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:25:46.428 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:25:46.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:46.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:46.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:46.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:46.901 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:25:46.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:46.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:46.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:46.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:46.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:46.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:46.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:46.912 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:25:46.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:46.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:46.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:46.913 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:46.913 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:46.913 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:46.913 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:46.913 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:46.913 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:25:51.917 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:25:51.917 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:25:51.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:51.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:51.917 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:51.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:51.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:25:51.924 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:51.924 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:51.924 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:25:51.924 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:25:51.929 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:25:51.929 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:25:51.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:51.930 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:51.930 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:25:51.930 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:25:51.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:25:51.930 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:25:51.938 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:25:51.938 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:25:51.938 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:51.938 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:51.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:25:51.939 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:25:51.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:25:51.939 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:25:51.945 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:25:51.945 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:25:51.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:51.945 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:25:51.946 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:25:51.946 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:25:51.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:25:51.946 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.955 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:25:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.956 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:25:51.956 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:25:51.956 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:25:51.956 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:25:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:25:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:25:51.961 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:25:52.439 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:25:52.486 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:25:52.487 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:25:52.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:52.489 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:25:52.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:52.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:52.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:52.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:52.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:52.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:52.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:52.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:52.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:52.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:52.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:52.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:52.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:52.577 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:52.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:52.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:52.910 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:25:52.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:52.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:52.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:52.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:53.382 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:25:53.853 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:25:53.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:53.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:53.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:53.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:54.326 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:25:54.799 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:25:54.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:54.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:54.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:54.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:55.272 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:25:55.745 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:25:55.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:55.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:55.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:55.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:56.217 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:25:56.690 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:25:56.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:25:56.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:25:56.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:25:56.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:25:57.163 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:25:57.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:57.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:57.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:57.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:57.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:57.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:57.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:57.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:25:57.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:25:57.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:25:57.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:25:57.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:57.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:57.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:57.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:25:57.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:25:57.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:25:57.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:25:57.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:57.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:25:57.635 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:25:58.108 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:25:58.579 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:25:59.049 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:25:59.523 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:25:59.996 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:26:00.468 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:26:00.939 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:26:01.412 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:26:01.885 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:26:02.357 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:26:02.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:02.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:02.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:02.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:02.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:02.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:02.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:02.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:02.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:02.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:02.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:02.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:02.662 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:02.662 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:02.662 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:02.662 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:02.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:02.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:02.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:02.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:02.827 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:26:03.299 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:26:03.769 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:26:04.240 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:26:04.713 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:26:05.186 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:26:05.658 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:26:06.129 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:26:06.602 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:26:07.075 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:26:07.547 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:26:07.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:07.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:07.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:07.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:07.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:07.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:07.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:07.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:07.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:07.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:07.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:07.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:07.708 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:07.708 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:07.708 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:07.708 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:07.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:07.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:07.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:07.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:08.018 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:26:08.489 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:26:08.962 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:26:09.434 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:26:09.907 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:26:10.377 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:26:10.851 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:26:11.323 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:26:11.795 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:26:12.267 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:26:12.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:12.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:12.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:12.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:12.740 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:26:12.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:12.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:12.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:12.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:12.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:12.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:12.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:12.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:12.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:12.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:26:12.756 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:26:12.756 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4494 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:12.756 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4494 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:12.756 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4494 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:12.756 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4494 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:12.757 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4494 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:12.757 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4494 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:17.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:17.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:26:17.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:17.757 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:17.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:17.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:17.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:17.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:17.770 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:17.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:17.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:26:17.772 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:26:17.772 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:26:17.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:17.773 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:17.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:17.773 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:26:17.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:17.773 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:26:17.774 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:26:17.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:26:17.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:17.775 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:17.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:17.775 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:26:17.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:17.775 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:26:17.776 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:26:17.776 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:26:17.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:17.776 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:17.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:17.776 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:26:17.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:17.776 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.778 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:26:17.778 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:26:17.779 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:26:17.779 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:17.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:17.783 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:26:18.261 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:26:18.295 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:26:18.296 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:26:18.297 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:26:18.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:18.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:18.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:18.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:18.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:18.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:18.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:18.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:18.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:18.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:18.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:18.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:18.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:18.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:18.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:18.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:18.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:18.733 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:26:18.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:18.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:18.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:18.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:19.205 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:26:19.676 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:26:19.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:19.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:19.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:19.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:20.149 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:26:20.622 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:26:20.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:20.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:20.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:20.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:21.094 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:26:21.568 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:26:21.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:21.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:21.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:21.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:22.040 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:26:22.513 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:26:22.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:22.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:22.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:22.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:22.984 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:26:23.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:23.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:23.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:23.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:23.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:23.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:23.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:23.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:23.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:23.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:23.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:23.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:23.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:23.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:23.433 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:23.433 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:23.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:23.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:23.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:23.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:23.456 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:26:23.929 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:26:24.401 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:26:24.872 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:26:25.345 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:26:25.817 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:26:26.290 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:26:26.761 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:26:27.234 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:26:27.706 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:26:28.178 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:26:28.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:28.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:28.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:28.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:28.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:28.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:28.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:28.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:28.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:28.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:28.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:28.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:28.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:28.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:28.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:28.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:28.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:28.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:28.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:28.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:28.649 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:26:29.120 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:26:29.591 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:26:30.062 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:26:30.532 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:26:31.006 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:26:31.478 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:26:31.950 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:26:32.421 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:26:32.894 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:26:33.367 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:26:33.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:33.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:33.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:33.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:33.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:33.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:33.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:33.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:33.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:33.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:33.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:33.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:33.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:33.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:33.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:33.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:33.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:33.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:33.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:33.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:33.838 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:26:34.309 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:26:34.781 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:26:35.254 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:26:35.726 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:26:36.198 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:26:36.669 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:26:37.143 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:26:37.615 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:26:38.087 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:26:38.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:38.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:38.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:38.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:38.558 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:26:38.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:38.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:38.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:38.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:38.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:38.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:38.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:26:38.568 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:26:38.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4492 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:26:43.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:26:43.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:26:43.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:43.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:43.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:43.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:43.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:26:43.577 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:43.577 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:43.577 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:26:43.577 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:26:43.578 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:26:43.578 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:26:43.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:43.578 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:43.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:26:43.578 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:26:43.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:26:43.578 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:26:43.579 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:26:43.579 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:26:43.579 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:43.579 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:43.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:26:43.580 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:26:43.580 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:26:43.580 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:26:43.581 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:26:43.581 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:26:43.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:43.581 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:26:43.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:26:43.581 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:26:43.581 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:26:43.581 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:26:43.583 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:26:43.583 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:26:43.583 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:26:43.588 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:26:44.065 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:26:44.109 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:26:44.111 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:26:44.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:44.114 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:26:44.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:44.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:44.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:44.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:44.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:44.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:44.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:44.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:44.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:44.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:44.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:44.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:44.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:44.204 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:44.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:44.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:44.537 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:26:44.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:44.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:44.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:44.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:45.009 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:26:45.482 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:26:45.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:45.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:45.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:45.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:45.952 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:26:46.425 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:26:46.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:46.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:46.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:46.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:46.897 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:26:47.371 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:26:47.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:47.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:47.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:47.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:47.843 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:26:48.316 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:26:48.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:26:48.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:26:48.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:26:48.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:26:48.789 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:26:49.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:49.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:49.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:49.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:49.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:49.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:49.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:49.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:49.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:49.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:49.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:49.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:49.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:49.239 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:49.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:49.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:49.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:49.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:49.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:49.261 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:26:49.733 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:26:50.204 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:26:50.678 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:26:51.150 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:26:51.622 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:26:52.093 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:26:52.567 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:26:53.039 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:26:53.511 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:26:53.982 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:26:54.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:54.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:54.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:54.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:54.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:54.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:54.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:54.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:54.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:54.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:54.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:54.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:54.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:54.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:54.287 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:54.287 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:54.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:54.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:54.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:54.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:54.451 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:26:54.919 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:26:55.390 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:26:55.860 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:26:56.331 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:26:56.805 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:26:57.277 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:26:57.749 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:26:58.220 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:26:58.693 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:26:59.166 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:26:59.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:59.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:59.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:59.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:59.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:59.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:59.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:59.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:26:59.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:26:59.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:26:59.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:26:59.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:59.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:59.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:59.334 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:26:59.334 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:26:59.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:26:59.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:26:59.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:59.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:26:59.638 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:27:00.109 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:27:00.583 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:27:01.055 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:27:01.527 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:27:01.998 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:27:02.471 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:27:02.944 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:27:03.416 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:27:03.887 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:27:04.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:04.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:04.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:04.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:04.358 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:27:04.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:04.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:04.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:04.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:04.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:27:04.371 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:27:04.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:27:04.371 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:27:04.371 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:27:04.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:27:04.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:27:04.371 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:04.371 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:04.371 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:04.371 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:04.371 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:04.371 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:09.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:27:09.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:27:09.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:27:09.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:27:09.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:27:09.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:27:09.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:27:09.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:27:09.384 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:09.384 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:27:09.384 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:27:09.386 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:27:09.386 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:27:09.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:27:09.387 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:09.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:27:09.387 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:27:09.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:27:09.387 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:27:09.389 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:27:09.389 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:27:09.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:27:09.389 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:09.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:27:09.389 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:27:09.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:27:09.389 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:27:09.391 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:27:09.391 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:27:09.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:27:09.391 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:09.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:27:09.391 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:27:09.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:27:09.391 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:27:09.393 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:27:09.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:27:09.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:27:09.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:27:09.393 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:27:09.394 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:27:09.394 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:27:09.394 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:09.398 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:27:09.876 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:27:09.918 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:27:09.920 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:27:09.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:09.923 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:27:09.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:09.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:09.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:09.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:09.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:09.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:09.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:09.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:09.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:09.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:09.978 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:27:09.978 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:27:10.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:10.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:10.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:10.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:10.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:10.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:10.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:10.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:10.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:10.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:10.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:10.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:27:10.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:27:10.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:10.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:10.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.348 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:27:10.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:10.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:10.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:10.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:10.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:10.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:10.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:10.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:10.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:10.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:10.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:10.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:10.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:10.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:10.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:27:10.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:27:10.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:10.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:10.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:10.819 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:27:11.290 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:27:11.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:11.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:11.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:11.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:11.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:11.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:11.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:11.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:11.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:11.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:11.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:11.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:11.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:11.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:11.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:11.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:11.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:11.473 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:27:11.473 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:27:11.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:11.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:11.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:11.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:11.761 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:27:12.232 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:27:12.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:12.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:12.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:12.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:12.320 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=633 tn=3 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:12.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:12.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:12.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:12.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:12.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:27:12.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:27:12.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:27:12.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:27:12.335 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:27:12.335 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:27:12.335 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:27:12.336 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=636 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:12.336 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=636 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:12.336 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=636 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:12.336 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=636 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:12.336 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=636 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:12.336 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=636 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:27:17.337 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:27:17.337 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:27:17.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:27:17.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:27:17.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:27:17.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:27:17.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:27:17.346 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:27:17.346 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:17.347 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:27:17.347 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:27:17.351 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:27:17.351 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:27:17.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:27:17.352 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:17.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:27:17.352 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:27:17.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:27:17.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:27:17.356 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:27:17.356 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:27:17.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:27:17.356 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:17.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:27:17.357 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:27:17.357 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:27:17.357 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:27:17.359 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:27:17.359 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:27:17.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:27:17.359 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:27:17.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:27:17.360 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:27:17.360 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:27:17.360 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:27:17.363 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:27:17.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:27:17.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:27:17.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:27:17.363 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:27:17.364 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:27:17.364 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:27:17.364 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:27:17.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:27:17.369 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:27:17.847 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:27:17.895 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:27:17.897 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:27:17.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:17.899 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:27:17.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:17.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:17.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:17.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:17.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:17.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:17.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:17.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:17.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:17.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:17.953 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:27:17.953 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:27:17.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:17.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:17.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:17.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:18.319 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:27:18.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:18.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:18.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:18.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:18.790 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:27:19.261 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:27:19.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:19.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:19.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:19.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:19.735 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:27:20.207 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:27:20.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:20.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:20.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:20.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:20.680 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:27:21.151 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:27:21.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:21.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:21.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:21.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:21.621 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:27:22.095 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:27:22.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:27:22.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:27:22.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:27:22.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:27:22.567 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:27:23.040 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:27:23.511 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:27:23.984 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:27:24.457 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:27:24.929 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:27:25.400 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:27:25.873 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:27:26.346 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:27:26.818 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:27:27.289 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:27:27.760 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:27:28.234 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:27:28.706 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:27:29.178 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:27:29.652 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:27:30.124 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:27:30.597 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:27:31.070 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:27:31.543 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:27:32.015 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:27:32.489 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:27:32.961 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:27:33.433 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:27:33.904 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:27:34.378 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:27:34.850 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:27:35.323 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:27:35.794 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:27:36.267 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:27:36.740 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:27:37.212 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:27:37.685 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:27:37.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:37.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:37.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:37.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:38.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:38.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:38.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:38.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:38.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:38.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:38.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:38.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:38.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:38.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:38.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:27:38.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:27:38.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:38.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:38.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:38.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:38.158 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:27:38.630 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:27:39.103 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:27:39.576 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:27:40.048 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:27:40.519 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:27:40.992 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:27:41.465 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:27:41.937 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:27:42.408 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:27:42.881 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:27:43.354 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:27:43.826 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:27:44.297 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:27:44.768 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:27:45.241 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:27:45.714 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:27:46.185 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:27:46.657 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:27:47.127 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:27:47.598 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:27:48.069 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:27:48.540 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:27:49.011 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:27:49.484 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:27:49.956 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:27:50.429 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:27:50.902 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:27:51.374 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:27:51.846 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:27:52.317 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:27:52.788 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:27:53.259 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:27:53.730 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:27:54.201 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:27:54.674 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:27:55.146 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:27:55.619 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:27:56.092 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:27:56.564 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:27:57.036 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:27:57.507 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:27:57.981 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:27:58.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:58.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:58.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:58.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:58.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:58.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:58.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:58.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:27:58.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:27:58.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:27:58.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:27:58.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:58.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:58.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:58.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:27:58.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:27:58.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:27:58.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:27:58.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:58.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:27:58.453 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:27:58.925 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:27:59.398 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:27:59.870 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:28:00.343 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:28:00.813 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:28:01.284 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:28:01.758 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:28:02.230 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:28:02.695 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:28:03.158 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:28:03.623 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:28:04.087 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:28:04.551 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:28:05.013 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:28:05.478 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:28:05.942 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:28:06.412 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:28:06.884 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:28:07.353 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:28:07.820 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:28:08.291 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:28:08.760 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:28:09.233 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:28:09.705 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:28:10.176 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:28:10.649 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:28:11.121 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:28:11.594 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:28:12.067 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:28:12.540 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:28:13.011 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:28:13.483 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:28:13.953 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:28:14.424 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:28:14.897 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:28:15.370 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:28:15.842 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:28:16.313 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:28:16.783 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:28:17.257 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:28:17.729 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:28:18.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:18.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:18.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:18.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:18.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:18.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:18.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:18.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:18.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:18.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:18.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:18.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:18.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:18.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:18.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:18.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:18.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:18.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:18.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:18.201 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:28:18.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:18.672 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:28:19.143 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:28:19.617 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:28:20.089 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:28:20.561 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:28:21.034 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:28:21.507 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:28:21.979 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:28:22.450 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:28:22.923 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:28:23.396 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:28:23.867 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:28:24.339 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:28:24.812 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:28:25.284 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:28:25.756 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:28:26.227 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:28:26.701 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:28:27.173 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:28:27.645 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:28:28.116 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:28:28.589 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:28:29.062 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:28:29.534 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:28:30.005 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:28:30.478 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:28:30.950 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:28:31.423 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:28:31.896 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:28:32.368 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:28:32.840 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:28:33.311 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:28:33.784 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:28:34.257 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:28:34.729 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:28:35.200 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:28:35.673 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:28:36.145 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:28:36.617 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:28:37.088 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:28:37.562 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:28:38.034 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:28:38.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:38.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:38.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:38.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:38.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:38.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:38.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:38.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:38.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:38.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:38.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:28:38.230 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:28:38.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:38.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:38.231 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:38.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17486 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:38.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17486 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:38.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17486 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:38.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17486 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:38.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17486 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:38.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17486 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:38.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17486 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:28:43.232 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:43.232 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:28:43.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:43.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:43.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:43.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:43.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:43.240 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:43.240 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.241 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:43.241 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:28:43.242 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:28:43.242 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:28:43.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:43.243 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:43.243 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:43.243 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:28:43.245 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:28:43.245 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:28:43.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:43.245 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:43.245 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:43.245 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:28:43.247 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:28:43.247 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:28:43.247 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:43.247 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:43.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:43.247 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.247 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:43.247 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:28:43.251 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:28:43.251 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:28:43.251 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:43.252 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:43.253 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:28:43.253 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:28:43.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:43.253 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:48.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:28:48.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:28:48.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:48.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:48.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:48.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:48.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:28:48.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:48.268 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:48.269 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:28:48.269 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:28:48.272 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:28:48.273 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:28:48.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:48.273 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:48.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:28:48.274 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:28:48.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:28:48.274 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:28:48.276 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:28:48.277 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:28:48.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:48.277 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:48.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:28:48.277 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:28:48.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:28:48.277 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:28:48.279 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:28:48.279 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:28:48.279 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:48.279 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:28:48.280 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:28:48.280 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:28:48.280 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:28:48.280 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:28:48.283 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:28:48.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:28:48.283 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:28:48.283 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:28:48.283 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:28:48.283 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:28:48.284 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:28:48.284 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:28:48.284 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.284 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:28:48.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:28:48.289 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:28:48.765 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:28:48.812 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:28:48.814 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:28:48.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:48.815 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:28:48.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:48.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:48.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:48.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:48.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:48.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:48.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:48.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:48.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:48.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:48.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:48.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:48.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:48.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:48.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:48.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:49.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:49.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:49.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.236 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:28:49.288 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:49.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:49.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:49.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:49.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:49.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.355 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:49.355 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:49.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:49.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:49.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.607 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:49.607 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:49.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.708 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:28:49.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:49.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:49.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:49.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:49.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:49.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:49.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:49.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:49.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:49.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.180 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:28:50.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:50.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:50.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:50.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:50.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:50.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:50.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:50.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:50.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:50.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:50.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:50.305 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:50.305 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:50.314 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:50.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:50.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:50.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:50.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:50.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:50.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:50.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:50.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:50.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:50.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:50.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:50.634 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:50.634 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:50.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:50.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:50.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:50.650 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:28:51.122 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:28:51.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:51.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:51.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:51.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:51.593 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:28:52.066 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:28:52.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:52.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:52.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:52.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:52.539 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:28:53.010 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:28:53.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:53.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:53.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:53.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:53.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:53.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:53.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:53.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:53.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:53.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:53.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:53.188 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:53.188 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:53.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:53.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:53.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:53.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:53.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:28:53.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:28:53.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:28:53.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:28:53.481 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:28:53.952 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:28:54.425 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:28:54.898 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:28:55.370 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:28:55.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:55.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:55.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:55.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:55.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:55.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:55.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:55.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:55.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:55.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:55.784 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:55.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:55.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:55.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:55.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:55.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:55.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:55.843 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:28:56.316 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:28:56.788 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:28:57.259 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:28:57.733 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:28:58.205 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:28:58.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:58.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:58.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:58.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:58.381 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:58.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:58.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:58.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:28:58.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:28:58.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:28:58.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:28:58.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:58.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:58.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:58.389 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:28:58.389 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:28:58.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:28:58.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:28:58.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:58.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:28:58.677 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:28:59.149 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:28:59.622 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:29:00.095 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:29:00.566 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:29:00.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:00.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:00.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:00.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:00.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:00.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:00.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:00.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:00.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:00.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:00.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:00.905 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:00.905 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:00.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:00.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:00.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:00.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:01.037 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:29:01.511 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:29:01.983 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:29:02.454 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:29:02.927 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:29:03.399 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:29:03.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:03.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:03.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:03.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:03.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:03.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:03.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:03.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:03.495 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:03.495 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:03.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:03.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:03.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:03.871 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:29:04.342 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:29:04.813 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:29:05.286 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:29:05.759 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:29:06.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:06.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:06.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:06.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:06.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:06.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:06.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:06.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:06.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:06.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:06.097 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:06.097 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:29:06.097 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:29:06.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:06.097 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:06.097 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3849 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:06.097 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3849 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:06.097 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3849 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:06.097 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3849 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:06.097 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3849 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:06.098 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3849 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:29:11.101 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:11.101 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:29:11.101 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:11.101 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:11.101 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:11.101 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:11.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:11.107 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:11.107 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:11.107 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:11.107 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:29:11.110 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:29:11.111 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:29:11.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:11.111 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:11.111 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:11.111 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:29:11.111 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:11.112 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:29:11.115 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:29:11.116 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:29:11.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:11.116 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:11.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:11.116 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:29:11.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:11.116 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:29:11.120 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:29:11.120 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:29:11.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:11.120 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:11.120 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:11.120 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:29:11.121 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:11.121 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:29:11.126 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:29:11.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:29:11.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:29:11.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:29:11.126 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:29:11.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:29:11.127 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:29:11.127 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:29:11.127 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:29:11.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:11.132 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:29:11.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:29:11.657 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:29:11.658 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:29:11.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:11.659 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:29:11.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:11.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:11.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:11.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:11.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:11.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:11.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:11.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:11.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:11.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:11.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:11.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:11.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:11.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:11.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:11.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:12.082 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:29:12.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:12.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:12.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:12.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:12.548 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:29:13.020 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:29:13.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:13.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:13.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:13.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:13.492 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:29:13.966 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:29:14.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:14.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:14.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:14.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:14.438 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:29:14.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:14.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:14.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:14.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:14.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:14.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:14.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:14.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:14.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:14.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:14.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:14.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:14.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:14.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:14.891 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:14.891 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:14.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:14.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:14.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:14.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:14.910 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:29:15.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:15.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:15.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:15.136 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:15.381 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:29:15.852 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:29:16.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:16.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:16.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:16.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:16.325 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:29:16.798 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:29:17.270 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:29:17.741 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:29:18.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:18.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:18.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:18.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:18.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:18.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:18.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:18.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:18.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:18.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:18.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:18.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:18.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:18.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:18.136 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:18.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:18.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:18.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:18.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:18.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:18.212 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:29:18.683 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:29:19.153 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:29:19.624 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:29:20.095 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:29:20.568 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:29:21.041 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:29:21.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:21.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:21.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:21.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:21.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:21.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:21.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:21.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:21.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:21.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:21.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:21.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:21.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:21.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:21.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:21.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:21.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:21.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:21.512 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:29:21.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:21.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:21.984 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:29:22.457 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:29:22.930 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:29:23.402 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:29:23.873 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:29:24.346 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:29:24.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:24.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:24.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:24.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:24.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:24.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:24.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:24.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:24.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:24.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:24.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:24.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:29:24.697 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:29:24.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:24.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:29.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:29.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:29:29.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:29.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:29.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:29.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:29.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:29.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:29.722 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:29.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:29.723 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:29:29.728 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:29:29.729 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:29:29.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:29.730 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:29.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:29.731 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:29:29.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:29.731 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:29:29.735 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:29:29.735 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:29:29.736 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:29.736 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:29.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:29.736 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:29:29.736 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:29.736 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:29:29.741 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:29:29.741 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:29:29.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:29.741 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:29.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:29.742 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:29:29.742 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:29.742 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:29:29.750 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:29:29.750 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:29:29.750 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:29.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:29.754 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:29:30.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:29:30.283 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:29:30.286 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:29:30.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:30.287 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:29:30.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:30.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:30.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:30.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:30.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:30.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:30.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:30.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:30.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:30.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:30.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:30.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:30.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:30.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:30.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:30.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:30.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:30.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:30.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:30.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:30.704 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:29:30.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:30.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:30.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:30.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:30.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:30.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:30.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:30.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:30.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:30.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:30.718 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:30.718 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:30.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:30.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:30.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:30.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:30.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:30.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:30.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:30.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:31.176 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:29:31.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:31.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:31.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:31.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:31.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:31.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:31.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:31.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:31.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:31.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:31.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:31.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:31.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:31.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:31.254 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:31.254 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:31.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:31.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:31.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:31.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:31.648 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:29:31.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:31.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:31.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:31.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:32.119 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:29:32.592 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:29:32.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:32.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:32.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:32.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:33.065 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:29:33.537 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:29:33.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:33.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:33.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:33.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:34.008 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:29:34.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:34.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:34.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:34.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:34.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:34.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:34.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:34.192 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:34.192 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:34.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:34.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:34.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:34.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:34.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:34.194 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:34.194 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:34.241 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:34.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:34.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:34.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:34.479 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:29:34.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:34.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:34.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:34.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:34.950 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:29:35.423 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:29:35.895 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:29:36.368 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:29:36.839 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:29:37.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:37.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:37.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:37.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:37.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:37.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:37.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:37.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:37.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:37.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:37.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:37.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:37.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:37.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:29:37.173 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:29:42.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:42.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:29:42.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:42.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:42.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:42.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:42.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:42.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:42.186 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:42.186 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:29:42.186 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:29:42.188 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:29:42.188 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:29:42.188 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:42.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:42.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:42.189 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:29:42.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:29:42.189 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:29:42.191 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:29:42.191 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:29:42.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:42.191 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:42.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:42.191 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:29:42.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:29:42.191 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:29:42.193 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:29:42.193 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:29:42.193 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:42.193 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:29:42.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:42.193 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:29:42.193 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:29:42.193 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:29:42.195 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:29:42.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:29:42.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:29:42.196 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:29:42.196 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:29:42.196 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:29:42.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:29:42.201 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:29:42.679 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:29:42.717 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:29:42.718 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:29:42.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:42.719 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:29:42.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:42.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:42.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:42.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:42.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:42.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:42.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:42.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:42.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:42.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:42.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:42.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:42.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:42.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:42.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:42.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:43.151 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:29:43.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:43.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:43.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:43.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:43.623 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:29:44.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:44.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:44.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:44.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:44.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:44.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:44.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:44.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:44.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:44.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:44.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:44.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:44.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:44.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:44.093 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:29:44.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:44.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:44.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:44.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:44.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:44.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:44.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:44.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:44.564 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:29:45.038 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:29:45.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:45.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:45.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:45.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:45.510 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:29:45.983 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:29:46.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:46.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:46.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:46.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:46.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:46.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:46.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:46.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:46.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:46.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:46.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:46.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:46.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:46.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:46.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:46.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:46.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:46.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:46.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:46.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:46.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:46.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:46.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:46.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:46.453 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:29:46.924 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:29:47.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:47.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:47.203 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:47.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:47.398 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:29:47.870 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:29:48.342 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:29:48.813 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:29:49.284 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:29:49.755 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:29:50.226 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:29:50.696 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:29:51.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:51.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:51.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:51.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:51.167 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:29:51.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:51.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:51.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:51.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:51.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:51.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:29:51.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:51.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:51.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:51.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:51.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:29:51.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:29:51.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:29:51.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:29:51.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:51.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:51.638 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:29:52.109 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:29:52.582 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:29:53.054 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:29:53.527 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:29:53.999 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:29:54.472 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:29:54.944 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:29:55.415 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:29:55.889 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:29:56.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:29:56.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:29:56.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:29:56.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:29:56.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:29:56.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:29:56.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:29:56.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:29:56.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:29:56.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:29:56.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:29:56.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:29:56.059 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:29:56.059 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:29:56.059 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:30:01.064 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:01.064 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:30:01.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:01.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:01.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:01.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:01.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:01.079 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:01.079 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:01.079 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:01.079 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:30:01.081 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:30:01.082 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:30:01.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:01.082 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:01.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:01.082 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:30:01.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:01.082 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:30:01.083 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:30:01.084 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:30:01.084 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:01.084 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:01.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:01.084 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:30:01.084 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:01.084 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:30:01.085 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:30:01.085 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:30:01.085 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:01.085 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:01.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:01.085 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:30:01.085 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:01.085 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.087 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:30:01.088 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:30:01.088 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:30:01.088 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:01.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:01.092 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:30:01.571 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:30:01.609 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:30:01.611 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:30:01.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:01.612 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:30:01.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:01.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:01.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:01.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:01.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:01.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:01.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:01.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:01.659 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:01.659 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:01.659 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:01.659 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:01.662 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:01.662 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:01.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:01.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:02.042 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:30:02.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:02.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:02.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:02.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:02.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:02.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:02.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:02.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:02.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:02.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:02.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:02.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:02.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:02.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:02.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:02.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:02.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:02.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:02.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:02.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:02.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:02.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:02.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:02.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:02.514 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:30:02.985 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:30:03.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:03.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:03.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:03.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:03.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:03.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:03.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:03.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:03.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:03.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:03.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:03.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:03.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:03.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:03.272 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:03.272 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:03.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:03.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:03.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:03.456 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:30:03.929 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:30:04.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:04.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:04.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:04.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:04.401 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:30:04.874 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:30:05.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:05.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:05.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:05.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:05.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:05.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:05.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:05.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:05.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:05.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:05.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:05.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:05.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:05.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:05.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:05.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:05.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:05.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:05.296 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:05.296 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:05.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:05.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:05.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:05.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:05.344 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:30:05.815 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:30:06.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:06.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:06.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:06.097 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:06.289 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:30:06.761 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:30:07.233 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:30:07.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:07.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:07.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:07.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:07.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:07.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:07.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:07.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:07.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:07.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:07.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:07.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:07.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:07.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:30:07.327 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:30:12.333 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:12.333 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:30:12.333 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:12.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:12.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:12.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:12.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:12.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:12.344 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:12.344 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:12.344 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:30:12.349 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:30:12.350 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:30:12.350 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:12.350 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:12.350 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:12.350 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:30:12.350 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:12.350 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:30:12.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:30:12.355 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:30:12.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:12.355 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:12.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:12.355 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:30:12.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:12.355 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:30:12.359 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:30:12.359 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:30:12.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:12.360 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:12.360 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:12.360 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:30:12.360 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:12.360 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:30:12.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:30:12.367 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:30:12.367 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:12.371 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:30:12.850 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:30:12.899 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:30:12.900 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:30:12.901 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:30:12.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:12.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:12.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:12.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:12.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:12.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:12.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:12.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:12.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:12.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:12.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:12.943 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:12.943 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:12.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:12.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:12.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:12.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:13.322 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:30:13.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:13.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:13.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:13.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:13.793 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:30:14.264 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:30:14.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:14.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:14.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:14.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:14.737 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:30:15.210 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:30:15.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:15.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:15.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:15.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:15.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:15.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:15.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:15.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:15.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:15.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:15.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:15.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:15.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:15.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:15.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:15.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:15.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:15.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:15.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:15.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:15.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:15.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:15.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:15.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:15.682 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:30:16.153 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:30:16.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:16.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:16.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:16.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:16.624 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:30:17.097 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:30:17.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:17.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:17.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:17.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:17.569 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:30:18.042 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:30:18.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:18.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:18.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:18.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:18.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:18.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:18.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:18.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:18.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:18.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:18.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:18.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:18.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:18.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:18.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:18.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:18.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:18.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:18.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:18.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:18.513 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:30:18.986 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:30:19.458 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:30:19.931 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:30:20.401 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:30:20.872 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:30:21.346 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:30:21.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:21.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:21.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:21.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:21.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:21.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:21.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:21.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:21.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:21.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:21.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:21.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:21.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:21.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:21.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:21.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:21.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:21.577 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:21.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:21.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:21.818 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:30:22.290 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:30:22.761 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:30:23.235 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:30:23.707 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:30:24.179 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:30:24.650 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:30:24.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:24.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:24.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:24.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:24.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:24.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:24.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:24.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:24.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:24.987 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:24.987 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:30:24.987 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:30:24.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:24.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:24.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:24.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2727 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:24.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2727 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:24.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2727 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:24.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2727 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:24.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2727 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:24.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2727 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:24.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2727 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:30:29.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:29.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:30:29.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:29.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:29.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:29.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:30.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:30.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:30.003 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:30.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:30.003 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:30:30.008 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:30:30.009 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:30:30.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:30.009 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:30.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:30.010 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:30:30.011 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:30.011 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:30:30.014 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:30:30.014 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:30:30.014 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:30.014 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:30.015 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:30.015 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:30:30.016 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:30.016 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:30:30.018 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:30:30.018 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:30:30.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:30.018 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:30.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:30.019 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:30:30.019 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:30.019 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:30:30.022 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:30:30.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:30:30.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:30:30.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:30:30.022 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:30:30.023 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:30:30.023 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:30:30.023 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:30.028 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:30:30.506 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:30:30.551 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:30:30.553 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:30:30.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:30.555 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:30:30.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:30.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:30.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:30.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:30.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:30.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:30.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:30.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:30.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:30.603 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:30.603 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:30.603 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:30.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:30.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:30.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:30.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:30.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:30.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:30.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:30.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:30.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:30.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:30.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:30.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:30.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:30.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:30.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:30.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:30.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:30.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:30.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:30.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:30.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:30.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:30.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:30.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:30.976 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:30:31.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:31.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:31.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:31.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:31.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:31.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:31.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:31.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:31.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:31.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:31.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:31.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:31.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:31.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:31.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:31.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:31.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:31.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:31.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:31.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:31.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:31.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:31.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:31.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:31.448 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:30:31.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:31.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:31.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:31.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:31.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:31.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:31.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:31.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:31.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:31.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:31.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:31.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:31.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:31.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:31.871 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:31.871 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:31.920 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:30:31.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:31.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:31.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:31.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:32.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:32.391 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:30:32.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:32.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:32.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:32.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:32.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:32.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:32.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:32.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:32.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:32.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:32.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:32.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:32.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:32.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:30:32.486 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:30:37.493 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:30:37.493 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:30:37.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:37.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:37.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:37.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:37.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:30:37.500 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:37.501 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:37.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:30:37.501 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:30:37.505 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:30:37.505 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:30:37.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:37.505 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:37.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:30:37.506 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:30:37.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:30:37.507 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:30:37.509 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:30:37.509 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:30:37.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:37.509 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:37.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:30:37.510 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:30:37.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:30:37.510 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:30:37.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:30:37.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:30:37.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:37.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:30:37.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:30:37.512 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:30:37.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:30:37.513 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:30:37.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:30:37.516 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:30:37.516 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:30:37.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:30:37.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:30:37.521 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:30:37.999 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:30:38.045 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:30:38.046 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:30:38.048 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:30:38.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:38.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:38.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:38.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:38.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:30:38.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:30:38.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:30:38.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:30:38.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:38.096 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:38.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:38.096 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:30:38.096 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:30:38.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:30:38.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:30:38.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:38.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:30:38.472 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:30:38.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:38.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:38.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:38.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:38.943 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:30:39.414 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:30:39.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:39.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:39.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:39.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:39.887 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:30:40.360 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:30:40.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:40.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:40.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:40.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:40.832 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:30:41.303 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:30:41.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:41.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:41.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:41.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:41.774 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:30:42.247 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:30:42.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:30:42.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:30:42.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:30:42.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:30:42.720 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:30:43.192 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:30:43.663 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:30:44.136 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:30:44.609 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:30:45.081 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:30:45.552 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:30:46.026 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:30:46.498 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:30:46.971 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:30:47.444 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:30:47.917 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:30:48.389 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:30:48.863 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:30:49.336 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:30:49.808 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:30:50.279 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:30:50.750 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:30:51.223 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:30:51.696 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:30:52.168 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:30:52.639 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:30:53.112 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:30:53.585 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:30:54.057 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:30:54.531 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:30:55.003 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:30:55.476 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:30:55.947 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:30:56.420 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:30:56.893 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:30:57.365 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:30:57.836 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:30:58.307 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:30:58.778 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:30:59.251 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:30:59.724 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:31:00.196 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:31:00.667 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:31:01.140 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:31:01.613 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:31:02.085 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:31:02.556 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:31:03.030 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:31:03.502 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:31:03.974 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:31:04.445 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:31:04.919 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:31:05.391 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:31:05.864 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:31:06.335 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:31:06.805 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:31:07.279 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:31:07.751 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:31:08.224 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:31:08.697 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:31:09.170 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:31:09.642 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:31:10.113 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:31:10.586 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:31:11.059 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:31:11.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:11.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:11.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:11.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:31:11.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:11.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:31:11.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:31:11.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:11.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:31:11.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:31:11.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:11.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:11.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:11.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:11.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:31:11.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:31:11.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:11.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:11.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:11.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:11.530 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:31:12.002 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:31:12.473 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:31:12.944 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:31:13.414 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:31:13.885 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:31:14.356 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:31:14.827 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:31:15.298 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:31:15.771 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:31:16.243 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:31:16.715 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:31:17.186 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:31:17.660 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:31:18.132 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:31:18.604 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:31:19.078 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:31:19.550 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:31:20.023 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:31:20.493 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:31:20.964 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:31:21.435 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:31:21.908 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:31:22.381 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:31:22.853 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:31:23.324 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:31:23.797 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:31:24.270 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:31:24.742 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:31:25.213 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:31:25.684 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:31:26.154 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:31:26.626 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:31:27.099 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:31:27.572 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:31:28.044 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:31:28.515 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:31:28.988 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:31:29.460 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:31:29.933 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:31:30.407 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:31:30.879 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:31:31.350 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:31:31.821 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:31:32.292 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:31:32.762 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:31:33.233 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:31:33.704 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:31:34.177 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:31:34.650 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:31:35.122 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:31:35.593 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:31:36.067 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:31:36.539 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:31:37.011 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:31:37.482 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:31:37.953 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:31:38.424 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:31:38.894 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:31:39.368 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:31:39.840 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:31:40.313 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:31:40.786 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:31:41.259 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:31:41.731 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:31:42.205 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:31:42.677 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:31:43.149 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:31:43.620 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:31:44.091 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:31:44.561 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:31:44.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:44.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:44.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:44.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:31:44.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:44.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:31:44.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:31:44.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:31:44.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:31:44.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:31:44.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:31:44.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:44.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:44.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:44.733 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:31:44.733 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:31:44.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:31:44.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:31:44.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:44.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:31:45.032 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:31:45.506 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:31:45.978 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:31:46.450 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:31:46.921 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:31:47.394 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:31:47.867 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:31:48.339 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:31:48.812 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:31:49.285 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:31:49.757 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:31:50.228 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:31:50.699 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:31:51.170 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:31:51.643 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:31:52.115 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:31:52.588 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:31:53.061 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:31:53.534 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:31:54.006 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:31:54.477 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:31:54.950 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:31:55.422 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:31:55.894 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:31:56.365 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:31:56.836 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:31:57.310 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:31:57.782 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:31:58.254 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:31:58.725 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:31:59.198 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:31:59.670 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:32:00.142 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:32:00.613 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:32:01.084 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:32:01.557 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:32:02.030 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:32:02.502 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:32:02.973 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:32:03.446 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 02:32:03.919 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 02:32:04.390 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 02:32:04.862 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 02:32:05.335 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 02:32:05.807 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 02:32:06.280 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 02:32:06.751 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 02:32:07.221 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 02:32:07.692 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 02:32:08.165 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-01-29 02:32:08.638 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-01-29 02:32:09.110 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-01-29 02:32:09.581 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-01-29 02:32:10.054 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-01-29 02:32:10.527 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-01-29 02:32:10.999 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-01-29 02:32:11.470 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-01-29 02:32:11.943 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-01-29 02:32:12.416 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-01-29 02:32:12.888 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-01-29 02:32:13.359 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-01-29 02:32:13.829 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-01-29 02:32:14.302 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-01-29 02:32:14.775 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-01-29 02:32:15.247 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-01-29 02:32:15.718 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-01-29 02:32:16.189 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-01-29 02:32:16.663 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-01-29 02:32:17.135 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-01-29 02:32:17.607 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-01-29 02:32:18.078 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-01-29 02:32:18.548 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-01-29 02:32:19.019 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-01-29 02:32:19.490 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-01-29 02:32:19.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:19.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:19.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:19.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:32:19.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:19.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:32:19.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:32:19.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:19.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:32:19.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:32:19.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:19.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:19.869 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:19.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:19.869 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:32:19.869 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:32:19.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:32:19.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:32:19.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:19.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:19.960 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-01-29 02:32:20.432 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-01-29 02:32:20.905 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-01-29 02:32:21.377 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-01-29 02:32:21.849 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-01-29 02:32:22.322 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-01-29 02:32:22.795 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-01-29 02:32:23.267 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-01-29 02:32:23.738 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-01-29 02:32:24.212 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-01-29 02:32:24.684 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-01-29 02:32:25.156 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-01-29 02:32:25.627 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-01-29 02:32:26.100 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-01-29 02:32:26.573 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-01-29 02:32:27.044 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-01-29 02:32:27.516 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-01-29 02:32:27.989 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-01-29 02:32:28.461 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-01-29 02:32:28.933 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-01-29 02:32:29.404 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-01-29 02:32:29.878 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-01-29 02:32:30.350 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-01-29 02:32:30.822 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-01-29 02:32:31.293 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-01-29 02:32:31.764 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-01-29 02:32:32.237 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-01-29 02:32:32.710 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-01-29 02:32:33.182 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-01-29 02:32:33.653 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-01-29 02:32:34.126 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-01-29 02:32:34.599 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-01-29 02:32:35.070 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-01-29 02:32:35.542 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-01-29 02:32:36.015 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-01-29 02:32:36.487 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-01-29 02:32:36.959 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-01-29 02:32:37.430 [DEBUG] clck_gen.py:113 IND CLOCK 25908
2026-01-29 02:32:37.903 [DEBUG] clck_gen.py:113 IND CLOCK 26010
2026-01-29 02:32:38.376 [DEBUG] clck_gen.py:113 IND CLOCK 26112
2026-01-29 02:32:38.848 [DEBUG] clck_gen.py:113 IND CLOCK 26214
2026-01-29 02:32:39.319 [DEBUG] clck_gen.py:113 IND CLOCK 26316
2026-01-29 02:32:39.793 [DEBUG] clck_gen.py:113 IND CLOCK 26418
2026-01-29 02:32:40.265 [DEBUG] clck_gen.py:113 IND CLOCK 26520
2026-01-29 02:32:40.737 [DEBUG] clck_gen.py:113 IND CLOCK 26622
2026-01-29 02:32:41.208 [DEBUG] clck_gen.py:113 IND CLOCK 26724
2026-01-29 02:32:41.681 [DEBUG] clck_gen.py:113 IND CLOCK 26826
2026-01-29 02:32:42.154 [DEBUG] clck_gen.py:113 IND CLOCK 26928
2026-01-29 02:32:42.626 [DEBUG] clck_gen.py:113 IND CLOCK 27030
2026-01-29 02:32:43.097 [DEBUG] clck_gen.py:113 IND CLOCK 27132
2026-01-29 02:32:43.568 [DEBUG] clck_gen.py:113 IND CLOCK 27234
2026-01-29 02:32:44.041 [DEBUG] clck_gen.py:113 IND CLOCK 27336
2026-01-29 02:32:44.514 [DEBUG] clck_gen.py:113 IND CLOCK 27438
2026-01-29 02:32:44.985 [DEBUG] clck_gen.py:113 IND CLOCK 27540
2026-01-29 02:32:45.457 [DEBUG] clck_gen.py:113 IND CLOCK 27642
2026-01-29 02:32:45.930 [DEBUG] clck_gen.py:113 IND CLOCK 27744
2026-01-29 02:32:46.402 [DEBUG] clck_gen.py:113 IND CLOCK 27846
2026-01-29 02:32:46.875 [DEBUG] clck_gen.py:113 IND CLOCK 27948
2026-01-29 02:32:47.346 [DEBUG] clck_gen.py:113 IND CLOCK 28050
2026-01-29 02:32:47.819 [DEBUG] clck_gen.py:113 IND CLOCK 28152
2026-01-29 02:32:48.291 [DEBUG] clck_gen.py:113 IND CLOCK 28254
2026-01-29 02:32:48.763 [DEBUG] clck_gen.py:113 IND CLOCK 28356
2026-01-29 02:32:49.234 [DEBUG] clck_gen.py:113 IND CLOCK 28458
2026-01-29 02:32:49.705 [DEBUG] clck_gen.py:113 IND CLOCK 28560
2026-01-29 02:32:50.179 [DEBUG] clck_gen.py:113 IND CLOCK 28662
2026-01-29 02:32:50.651 [DEBUG] clck_gen.py:113 IND CLOCK 28764
2026-01-29 02:32:51.123 [DEBUG] clck_gen.py:113 IND CLOCK 28866
2026-01-29 02:32:51.594 [DEBUG] clck_gen.py:113 IND CLOCK 28968
2026-01-29 02:32:52.068 [DEBUG] clck_gen.py:113 IND CLOCK 29070
2026-01-29 02:32:52.540 [DEBUG] clck_gen.py:113 IND CLOCK 29172
2026-01-29 02:32:53.012 [DEBUG] clck_gen.py:113 IND CLOCK 29274
2026-01-29 02:32:53.483 [DEBUG] clck_gen.py:113 IND CLOCK 29376
2026-01-29 02:32:53.956 [DEBUG] clck_gen.py:113 IND CLOCK 29478
2026-01-29 02:32:54.429 [DEBUG] clck_gen.py:113 IND CLOCK 29580
2026-01-29 02:32:54.901 [DEBUG] clck_gen.py:113 IND CLOCK 29682
2026-01-29 02:32:55.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:32:55.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:32:55.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:32:55.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:32:55.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:32:55.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:32:55.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:32:55.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:32:55.199 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:32:55.199 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:32:55.199 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:32:55.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:32:55.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:32:55.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:32:55.200 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:32:55.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=29749 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:55.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=29749 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:55.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=29749 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:55.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=29749 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:55.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=29749 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:55.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=29749 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:32:55.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=29749 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:33:00.204 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:33:00.204 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:33:00.204 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:00.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:00.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:00.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:00.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:00.214 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:33:00.215 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:00.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:33:00.215 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:33:00.220 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:33:00.221 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:33:00.221 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:33:00.221 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:00.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:00.222 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:33:00.222 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:33:00.222 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:33:00.225 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:33:00.226 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:33:00.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:33:00.226 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:00.226 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:00.226 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:33:00.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:33:00.226 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:33:00.230 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:33:00.230 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:33:00.231 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:33:00.231 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:00.231 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:00.231 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:33:00.231 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:33:00.231 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:33:00.236 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:33:00.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:33:00.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:33:00.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:33:00.236 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.237 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:33:00.237 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:33:00.237 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:33:00.237 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:00.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:00.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:00.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:33:00.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:33:00.241 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:33:00.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:00.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:05.248 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:33:05.248 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:33:05.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:05.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:05.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:05.248 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:05.256 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:05.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:33:05.257 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:05.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:33:05.257 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:33:05.259 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:33:05.259 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:33:05.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:33:05.260 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:05.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:05.260 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:33:05.261 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:33:05.261 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:33:05.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:33:05.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:33:05.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:33:05.262 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:05.262 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:05.262 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:33:05.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:33:05.262 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:33:05.264 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:33:05.264 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:33:05.264 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:33:05.264 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:05.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:05.264 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:33:05.264 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:33:05.264 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.267 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:33:05.267 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:33:05.267 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:33:05.268 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:05.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:05.272 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:33:05.750 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:33:05.790 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:33:05.792 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:33:05.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:05.794 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:33:05.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:05.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:05.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:05.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:05.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:05.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:05.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:05.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:05.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:05.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:05.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:33:05.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:33:05.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:05.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:05.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:05.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:06.222 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:33:06.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:06.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:06.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:06.271 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:06.694 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:33:07.167 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:33:07.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:07.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:07.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:07.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:07.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:07.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:07.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:07.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:07.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:07.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:07.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:07.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:07.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:07.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:07.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:07.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:07.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:07.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:07.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:33:07.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:33:07.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:07.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:07.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:07.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:07.639 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:33:08.112 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:33:08.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:08.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:08.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:08.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:08.583 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:33:09.056 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:33:09.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:09.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:09.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:09.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:09.529 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:33:09.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:09.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:09.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:09.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:09.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:09.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:09.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:09.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:09.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:09.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:09.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:09.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:09.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:09.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:09.671 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:33:09.671 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:33:09.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:09.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:09.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:09.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:10.001 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:33:10.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:10.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:10.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:10.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:10.472 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:33:10.943 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:33:11.413 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:33:11.884 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:33:12.358 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:33:12.830 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:33:12.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:12.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:12.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:12.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:13.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:13.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:13.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:13.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:13.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:13.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:13.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:13.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:13.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:13.016 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:13.017 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:33:13.017 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:33:13.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:13.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:13.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:13.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:13.301 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:33:13.773 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:33:14.244 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:33:14.717 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:33:15.189 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:33:15.662 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:33:16.132 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:33:16.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:16.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:16.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:16.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:16.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:16.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:16.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:16.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:16.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:16.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:16.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:16.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:33:16.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:33:16.461 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:33:16.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:21.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:33:21.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:33:21.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:21.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:21.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:21.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:21.475 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:33:21.476 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:33:21.476 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:21.476 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:33:21.476 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:33:21.479 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:33:21.479 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:33:21.479 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:33:21.479 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:21.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:33:21.480 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:33:21.480 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:33:21.480 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:33:21.481 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:33:21.482 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:33:21.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:33:21.482 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:21.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:33:21.482 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:33:21.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:33:21.482 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:33:21.483 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:33:21.484 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:33:21.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:33:21.484 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:33:21.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:33:21.484 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:33:21.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:33:21.484 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:33:21.486 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:33:21.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:33:21.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:33:21.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:33:21.486 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:33:21.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:33:21.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:33:21.487 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:33:21.487 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:33:21.487 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:33:21.491 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:33:21.969 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:33:22.009 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:33:22.010 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:33:22.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:22.012 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:33:22.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:22.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:22.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:22.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:22.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:22.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:22.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:22.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:22.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:22.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:22.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:33:22.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:33:22.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:22.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:22.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:22.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:22.442 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:33:22.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:22.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:22.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:22.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:22.913 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:33:23.386 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:33:23.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:23.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:23.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:23.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:23.859 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:33:24.331 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:33:24.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:24.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:24.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:24.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:24.802 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:33:25.272 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:33:25.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:25.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:25.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:25.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:25.743 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:33:26.216 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:33:26.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:33:26.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:33:26.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:33:26.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:33:26.689 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:33:27.162 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:33:27.633 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:33:28.106 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:33:28.579 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:33:29.051 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:33:29.522 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:33:29.996 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:33:30.468 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:33:30.940 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:33:31.411 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:33:31.882 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:33:32.356 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:33:32.829 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:33:33.302 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:33:33.775 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:33:34.247 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:33:34.718 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:33:35.190 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:33:35.664 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:33:36.136 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:33:36.607 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:33:36.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:36.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:36.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:36.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:36.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:36.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:36.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:36.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:36.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:36.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:36.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:36.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:36.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:36.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:36.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:33:36.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:33:36.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:36.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:36.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:36.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:37.077 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:33:37.548 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:33:38.022 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:33:38.494 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:33:38.966 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:33:39.437 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:33:39.908 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:33:40.378 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:33:40.849 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:33:41.323 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:33:41.795 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:33:42.267 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:33:42.738 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:33:43.212 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:33:43.684 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:33:44.156 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:33:44.628 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:33:45.101 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:33:45.574 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:33:46.045 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:33:46.517 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:33:46.987 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:33:47.461 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:33:47.933 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:33:48.406 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:33:48.879 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:33:49.352 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:33:49.824 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:33:50.295 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:33:50.765 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:33:51.239 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:33:51.711 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:33:52.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:52.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:52.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:52.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:52.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:52.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:52.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:52.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:33:52.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:33:52.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:33:52.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:33:52.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:52.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:52.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:52.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:33:52.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:33:52.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:33:52.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:33:52.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:52.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:33:52.183 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:33:52.655 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:33:53.125 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:33:53.596 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:33:54.070 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:33:54.542 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:33:55.014 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:33:55.485 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:33:55.956 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:33:56.429 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:33:56.901 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:33:57.374 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:33:57.844 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:33:58.315 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:33:58.789 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:33:59.261 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:33:59.733 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:34:00.204 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:34:00.678 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:34:01.150 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:34:01.622 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:34:02.093 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:34:02.564 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:34:03.038 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:34:03.510 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:34:03.981 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:34:04.453 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:34:04.923 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:34:05.397 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:34:05.869 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:34:06.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:06.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:06.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:06.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:06.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:06.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:06.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:06.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:06.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:06.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:06.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:06.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:06.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:06.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:06.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:34:06.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:34:06.341 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:34:06.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:06.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:06.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:06.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:06.812 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:34:07.283 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:34:07.757 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:34:08.229 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:34:08.701 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:34:09.172 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:34:09.645 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:34:10.118 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:34:10.590 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:34:11.061 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:34:11.534 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:34:12.006 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:34:12.478 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:34:12.949 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:34:13.423 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:34:13.895 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:34:14.367 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:34:14.838 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:34:15.312 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:34:15.784 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:34:16.256 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:34:16.729 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:34:17.202 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:34:17.674 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:34:18.145 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:34:18.618 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:34:19.091 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:34:19.563 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:34:20.034 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:34:20.507 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:34:20.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:20.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:20.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:20.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:20.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:20.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:20.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:20.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:20.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:20.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:20.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:20.917 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:20.917 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:20.917 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:34:20.917 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:34:25.922 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:34:25.922 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:34:25.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:25.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:25.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:25.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:25.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:34:25.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:25.926 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:25.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:34:25.926 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:34:25.927 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:34:25.927 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:34:25.927 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:25.927 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:25.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:34:25.927 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:34:25.927 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:34:25.927 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:34:25.929 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:34:25.929 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:34:25.929 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:25.929 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:25.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:34:25.929 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:34:25.929 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:34:25.930 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:34:25.931 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:34:25.931 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:34:25.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:25.931 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:34:25.931 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:34:25.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:34:25.932 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:34:25.932 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:34:25.934 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:34:25.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:34:25.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:34:25.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:34:25.934 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:34:25.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:34:25.935 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:34:25.935 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:34:25.935 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:34:25.939 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:34:26.416 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:34:26.461 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:34:26.463 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:34:26.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:26.465 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:34:26.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:26.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:26.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:26.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:26.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:26.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:26.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:26.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:26.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:26.510 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:34:26.510 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:34:26.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:26.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:26.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:26.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:26.888 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:34:26.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:26.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:27.360 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:34:27.833 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:34:27.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:27.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:27.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:27.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:28.306 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:34:28.778 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:34:28.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:28.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:28.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:28.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:29.249 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:34:29.720 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:34:29.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:29.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:29.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:29.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:30.191 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:34:30.664 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:34:30.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:34:30.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:34:30.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:34:30.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:34:31.137 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:34:31.609 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:34:32.080 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:34:32.553 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:34:33.026 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:34:33.498 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:34:33.969 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:34:34.440 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:34:34.913 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:34:35.386 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:34:35.858 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:34:36.329 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:34:36.803 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:34:37.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:37.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:37.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:37.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:37.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:37.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:37.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:37.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:37.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:37.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:37.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:37.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:37.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:37.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:37.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:34:37.037 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:34:37.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:37.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:37.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:37.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:37.274 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:34:37.746 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:34:38.217 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:34:38.688 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:34:39.161 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:34:39.634 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:34:40.106 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:34:40.577 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:34:41.051 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:34:41.523 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:34:41.994 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:34:42.465 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:34:42.936 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:34:43.406 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:34:43.877 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:34:44.348 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:34:44.821 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:34:45.294 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:34:45.766 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:34:46.237 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:34:46.708 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:34:47.181 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:34:47.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:47.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:47.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:47.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:47.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:47.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:47.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:47.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:47.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:47.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:47.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:34:47.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:34:47.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:47.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:47.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:47.652 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:34:48.125 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:34:48.598 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:34:49.071 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:34:49.543 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:34:50.014 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:34:50.487 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:34:50.959 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:34:51.431 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:34:51.902 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:34:52.376 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:34:52.848 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:34:53.320 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:34:53.794 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:34:54.266 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:34:54.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:54.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:54.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:54.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:54.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:54.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:54.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:54.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:34:54.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:34:54.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:34:54.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:34:54.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:54.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:54.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:54.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:34:54.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:34:54.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:34:54.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:34:54.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:54.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:34:54.738 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:34:55.209 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:34:55.683 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:34:56.155 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:34:56.627 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:34:57.098 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:34:57.571 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:34:58.044 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:34:58.516 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:34:58.987 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:34:59.460 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:34:59.932 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:35:00.404 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:35:00.875 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:35:01.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:01.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:01.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:01.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:01.346 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:35:01.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:01.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:01.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:01.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:01.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:01.358 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:01.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:01.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:01.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:01.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:01.358 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:35:06.363 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:06.363 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:06.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:06.363 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:06.363 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:06.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:06.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:06.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:06.366 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:06.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:06.366 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:35:06.367 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:35:06.367 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:35:06.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:06.368 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:06.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:06.368 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:35:06.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:06.368 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:35:06.369 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:35:06.369 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:35:06.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:06.369 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:06.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:06.369 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:35:06.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:06.369 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:35:06.370 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:35:06.370 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:35:06.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:06.370 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:06.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:06.370 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:35:06.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:06.370 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:35:06.372 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:35:06.372 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:35:06.372 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:35:06.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:06.377 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:35:06.855 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:35:06.895 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:35:06.897 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:35:06.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:06.899 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:35:06.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:06.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:06.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:06.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:06.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:06.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:06.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:06.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:06.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:06.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:06.953 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:06.953 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:06.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:06.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:06.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:06.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:07.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:07.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:07.325 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:35:07.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:07.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:07.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:07.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:07.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:07.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:07.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:07.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:07.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:07.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:07.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:07.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:07.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:07.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:07.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:07.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:07.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:07.796 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:35:07.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:07.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:07.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:07.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:07.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:07.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:07.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:07.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:07.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:07.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:07.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:07.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:07.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:07.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:07.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:07.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:07.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:07.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:08.268 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:35:08.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:08.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:08.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:08.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:08.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:08.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:08.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:08.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:08.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:08.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:08.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:08.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:08.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:08.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:08.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:08.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:08.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:08.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:08.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:08.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:08.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:08.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:08.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:08.740 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:35:08.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:09.211 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:35:09.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:09.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:09.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:09.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:09.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:09.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:09.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:09.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:09.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:09.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:09.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:09.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:09.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:09.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:09.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:09.544 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:09.544 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:09.544 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:35:09.544 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=686 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.544 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=686 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.544 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=686 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.544 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=686 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:09.544 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=686 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:14.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:14.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:14.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:14.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:14.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:14.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:14.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:14.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:14.565 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:14.566 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:35:14.570 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:35:14.570 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:35:14.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:14.570 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:14.571 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:14.571 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:35:14.574 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:35:14.574 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:35:14.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:14.574 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:14.575 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.575 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:14.575 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:35:14.577 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:35:14.577 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:35:14.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:14.577 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:14.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:14.577 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:14.577 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:35:14.581 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:35:14.581 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:35:14.581 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:14.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:14.586 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:35:15.065 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:35:15.110 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:35:15.112 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:35:15.113 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:35:15.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:15.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:15.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:15.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:15.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:15.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:15.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:15.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:15.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:15.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:15.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:15.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:15.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:15.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:15.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:15.536 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:35:15.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:15.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:15.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:15.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:16.008 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:35:16.482 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:35:16.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:16.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:16.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:16.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:16.954 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:35:17.427 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:35:17.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:17.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:17.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:17.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:17.897 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:35:18.371 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:35:18.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:18.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:18.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:18.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:18.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:18.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:18.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:18.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:18.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:18.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:18.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:18.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:18.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:18.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:18.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:18.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:18.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:18.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:18.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:18.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:18.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:18.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:18.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:18.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:18.843 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:35:19.315 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:35:19.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:19.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:19.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:19.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:19.786 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:35:20.257 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:35:20.728 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:35:21.201 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:35:21.674 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:35:21.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:21.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:21.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:21.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:21.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:21.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:21.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:21.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:21.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:21.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:21.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:21.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:21.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:21.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:21.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:21.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:21.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:21.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:21.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:21.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:22.146 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:35:22.617 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:35:23.090 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:35:23.563 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:35:24.034 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:35:24.506 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:35:24.979 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:35:25.451 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:35:25.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:25.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:25.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:25.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:25.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:25.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:25.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:25.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:25.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:25.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:25.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:25.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:25.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:25.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:25.638 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:25.638 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:25.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:25.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:25.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:25.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:25.923 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:35:26.394 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:35:26.865 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:35:27.338 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:35:27.810 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:35:28.282 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:35:28.753 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:35:29.226 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:35:29.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:29.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:29.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:29.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:29.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:29.312 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:29.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:29.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:29.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:29.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:29.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:29.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:29.313 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:35:29.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:29.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:34.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:34.319 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:34.319 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:34.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:34.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:34.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:34.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:34.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:34.328 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:34.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:34.328 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:35:34.332 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:35:34.332 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:35:34.332 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:34.332 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:34.333 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:34.333 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:35:34.333 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:34.333 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:35:34.336 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:35:34.336 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:35:34.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:34.336 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:34.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:34.336 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:35:34.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:34.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:35:34.339 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:35:34.339 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:35:34.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:34.339 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:34.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:35:34.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:34.340 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:34.340 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.343 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:35:34.343 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:35:34.343 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:35:34.344 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:34.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:34.348 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:35:34.826 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:35:34.869 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:35:34.871 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:35:34.873 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:35:34.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:34.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:34.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:34.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:34.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:34.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:34.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:34.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:34.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:34.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:34.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:34.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:34.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:34.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:34.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:34.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:34.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:35.299 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:35:35.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:35.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:35.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:35.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:35.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:35.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:35.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:35.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:35.362 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:35.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:35.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:35.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:35.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:35.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:35.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:35.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:35.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:35.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:35.369 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:35.369 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:35.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:35.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:35.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:35.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:35.770 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:35:35.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:35.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:35.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:35.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:35.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:35.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:35.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:35.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:35.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:35.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:35.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:35.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:35.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:35.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:35.969 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:35.969 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:36.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:36.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:36.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:36.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:36.241 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:35:36.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:36.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:36.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:36.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:36.714 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:35:37.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:37.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:37.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:37.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:37.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:37.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:37.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:37.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:37.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:37.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:37.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:37.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:37.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:37.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:37.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:37.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:37.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:37.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:37.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:37.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:37.186 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:35:37.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:37.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:37.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:37.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:37.658 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:35:38.129 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:35:38.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:38.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:38.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:38.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:38.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:38.224 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:38.224 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:38.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:38.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:38.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:38.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:38.227 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:35:38.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:38.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:38.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:38.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:38.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:38.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:38.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:38.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:38.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:38.227 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:35:43.232 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:35:43.232 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:35:43.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:43.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:43.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:43.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:43.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:35:43.244 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:43.244 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:43.245 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:35:43.245 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:35:43.249 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:35:43.249 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:35:43.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:43.249 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:43.249 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:35:43.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:35:43.250 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:35:43.250 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:35:43.253 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:35:43.254 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:35:43.254 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:43.254 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:43.254 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:35:43.254 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:35:43.254 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:35:43.254 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:35:43.258 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:35:43.258 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:35:43.258 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:43.258 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:35:43.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:35:43.259 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:35:43.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:35:43.259 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:35:43.264 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:35:43.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:35:43.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:35:43.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:35:43.264 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:35:43.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:35:43.265 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:35:43.265 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:35:43.265 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:35:43.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:35:43.270 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:35:43.749 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:35:43.798 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:35:43.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:43.801 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:35:43.802 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:35:43.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:43.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:43.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:43.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:43.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:43.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:43.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:43.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:43.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:43.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:43.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:43.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:43.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:43.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:43.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:43.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:44.222 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:35:44.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:44.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:44.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:44.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:44.693 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:35:45.166 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:35:45.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:45.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:45.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:45.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:45.639 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:35:46.111 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:35:46.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:46.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:46.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:46.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:46.582 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:35:46.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:46.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:46.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:46.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:46.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:46.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:46.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:46.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:46.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:46.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:46.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:46.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:46.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:46.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:46.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:46.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:46.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:46.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:46.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:46.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:47.053 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:35:47.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:47.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:47.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:47.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:47.526 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:35:47.999 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:35:48.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:35:48.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:35:48.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:35:48.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:35:48.471 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:35:48.942 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:35:49.413 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:35:49.883 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:35:50.354 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:35:50.825 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:35:51.299 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:35:51.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:51.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:51.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:51.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:51.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:51.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:51.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:51.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:51.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:51.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:51.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:51.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:51.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:51.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:51.354 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:51.354 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:51.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:51.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:51.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:51.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:51.771 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:35:52.242 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:35:52.713 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:35:53.184 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:35:53.657 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:35:54.129 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:35:54.601 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:35:55.072 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:35:55.546 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:35:56.023 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:35:56.495 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:35:56.966 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:35:57.439 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:35:57.912 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:35:58.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:58.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:58.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:58.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:58.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:58.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:58.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:58.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:35:58.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:35:58.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:35:58.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:35:58.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:58.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:58.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:58.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:35:58.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:35:58.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:35:58.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:35:58.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:58.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:35:58.384 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:35:58.855 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:35:59.328 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:35:59.800 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:36:00.272 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:36:00.743 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:36:01.214 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:36:01.685 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:36:02.158 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:36:02.631 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:36:03.103 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:36:03.574 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:36:04.047 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:36:04.519 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:36:04.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:04.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:04.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:04.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:04.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:04.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:04.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:04.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:04.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:04.856 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:04.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:04.856 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:04.856 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:04.856 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:04.856 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:09.861 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:09.861 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:09.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:09.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:09.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:09.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:09.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:09.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:09.872 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:09.873 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:09.877 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:09.878 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:09.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:09.878 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:09.879 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:09.880 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:09.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:09.882 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:09.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:09.882 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:09.882 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:09.882 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:09.885 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:09.885 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:09.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:09.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:09.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:09.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:09.886 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:36:09.889 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:36:09.889 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:09.889 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:09.894 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:10.371 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:10.415 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:10.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.419 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:10.422 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:10.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:10.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:10.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:10.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:10.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:10.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:10.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:10.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:10.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:10.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:10.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:36:10.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:36:10.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:10.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:10.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:10.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:10.842 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:10.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:10.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:10.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:10.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:11.314 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:11.785 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:36:11.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:11.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:11.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:11.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:12.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:12.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:12.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:12.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:12.258 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:36:12.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:12.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:12.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:12.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:12.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:12.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:12.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:12.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:12.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:12.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:12.280 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:36:12.280 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:36:12.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:12.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:12.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:12.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:12.730 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:36:12.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:12.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:12.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:12.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:13.202 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:36:13.676 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:36:13.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:13.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:13.897 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:13.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:14.148 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:36:14.620 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:36:14.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:14.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:14.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:14.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:15.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:15.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:15.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:15.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:15.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:15.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:15.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:15.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:15.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:15.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:15.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:15.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:15.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:15.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:15.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:36:15.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:36:15.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:15.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:15.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:15.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:15.091 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:36:15.562 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:36:16.033 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:36:16.506 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:36:16.978 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:36:17.451 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:36:17.922 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:36:18.395 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:36:18.868 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:36:19.340 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:36:19.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:19.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:19.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:19.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:19.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:19.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:19.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:19.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:19.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:19.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:36:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:19.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:19.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:19.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:19.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:36:19.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:36:19.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:36:19.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:36:19.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:19.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:19.810 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:36:20.281 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:36:20.755 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:36:21.227 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:36:21.699 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:36:22.170 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:36:22.643 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:36:23.116 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:36:23.588 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:36:23.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:36:23.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:23.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:36:23.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:36:23.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:23.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:23.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:23.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:23.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:23.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:23.922 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:23.922 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:23.922 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:23.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:23.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:28.929 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:28.930 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:28.930 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:28.930 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:28.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:28.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:28.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:28.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:28.943 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:28.944 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:28.944 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:28.946 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:28.946 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:28.946 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:28.946 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:28.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:28.947 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:28.947 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:28.947 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:28.948 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:28.949 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:28.949 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:28.949 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:28.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:28.949 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:28.949 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:28.949 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:28.951 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:28.951 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:28.951 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:28.951 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:28.951 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:28.951 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:28.952 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:28.952 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.955 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:36:28.955 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:36:28.955 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:28.955 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:28.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:28.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:28.960 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:29.438 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:29.477 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:29.478 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:29.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:29.480 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:29.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:29.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:29.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:29.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:29.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:29.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:29.904 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:29.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:29.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:29.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:29.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:30.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.376 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:30.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:30.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:30.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:30.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:30.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:30.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:30.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:30.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:30.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:30.807 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:30.807 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:30.807 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:35.814 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:35.814 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:35.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:35.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:35.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:35.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:35.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:35.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:35.823 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:35.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:35.823 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:35.824 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:35.824 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:35.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:35.824 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:35.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:35.824 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:35.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:35.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:35.826 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:35.826 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:35.826 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:35.826 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:35.826 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:35.826 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:35.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:35.827 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:35.828 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:35.828 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:35.828 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:35.828 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:35.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:35.828 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:35.828 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:35.828 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:36:35.830 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:36:35.830 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:35.830 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:35.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:35.835 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:36.314 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:36.351 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:36.352 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:36.353 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:36.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:36.781 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:36.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:36.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:36.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:36.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:37.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.252 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:37.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:37.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:37.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:37.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:37.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:37.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:37.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:37.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:37.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:37.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:37.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:37.697 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:42.704 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:42.704 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:42.704 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:42.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:42.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:42.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:42.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:42.716 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:42.716 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:42.716 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:42.716 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:42.720 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:42.720 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:42.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:42.720 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:42.720 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:42.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:42.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:42.720 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:42.723 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:42.723 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:42.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:42.723 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:42.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:42.723 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:42.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:42.723 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:42.725 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:42.725 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:42.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:42.726 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:42.726 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:42.726 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:42.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:42.726 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:36:42.729 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:36:42.729 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:42.729 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:42.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:42.734 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:43.212 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:43.252 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:43.254 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:43.256 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:43.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.683 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:43.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:43.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:43.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:43.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:43.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:43.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.155 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:44.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:44.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:44.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:44.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:44.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:44.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:44.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:44.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:44.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:44.569 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:44.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:44.569 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:49.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:49.576 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:49.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:49.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:49.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:49.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:49.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:49.585 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:49.585 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:49.585 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:49.585 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:49.588 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:49.588 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:49.588 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:49.588 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:49.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:49.589 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:49.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:49.589 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:49.591 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:49.591 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:49.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:49.591 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:49.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:49.591 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:49.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:49.591 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:49.593 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:49.593 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:49.593 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:49.593 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:49.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:49.594 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:49.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:49.594 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:36:49.596 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:36:49.596 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:49.601 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:50.080 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:50.116 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:50.117 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:50.119 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:50.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.546 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:50.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:50.599 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:50.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:50.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:50.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:50.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.018 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:51.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:51.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:51.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:51.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:51.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:51.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:51.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:51.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:51.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:51.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:51.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:51.468 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:56.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:56.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:56.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:56.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:56.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:56.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:56.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:56.480 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:56.480 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:56.480 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:36:56.481 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:36:56.485 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:36:56.485 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:36:56.485 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:56.485 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:56.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:56.486 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:36:56.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:36:56.487 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:36:56.488 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:36:56.489 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:36:56.489 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:56.489 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:56.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:56.489 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:36:56.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:36:56.490 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:36:56.492 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:36:56.492 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:36:56.492 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:56.492 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:36:56.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:56.492 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:36:56.492 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:36:56.492 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:36:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:36:56.497 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:36:56.497 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:36:56.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:56.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:36:56.501 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:36:56.980 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:36:57.027 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:36:57.029 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:36:57.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.030 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:36:57.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:36:57.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.451 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:36:57.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:57.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:57.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:57.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:57.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:57.919 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:36:58.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:36:58.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:36:58.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:36:58.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:36:58.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:36:58.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:36:58.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:36:58.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:36:58.347 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:36:58.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:36:58.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:36:58.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:36:58.347 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.347 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.347 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.347 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.347 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:36:58.347 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:03.354 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:03.354 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:03.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:03.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:03.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:03.354 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:03.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:03.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:03.363 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:03.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:03.367 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:03.367 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:03.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:03.367 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:03.368 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:03.368 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:03.371 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:03.371 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:03.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:03.371 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:03.371 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:03.372 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:03.375 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:03.375 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:03.375 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:03.375 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:03.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:03.376 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:03.376 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:03.381 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:03.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:03.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:03.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:03.381 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.382 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:03.382 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:03.382 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:03.382 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.387 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:03.864 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:03.917 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:03.920 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:03.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:03.922 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:03.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:03.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:03.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:03.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:03.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.335 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:37:04.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:04.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:04.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:04.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:04.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.807 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:37:04.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:04.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:05.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:05.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:05.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:05.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:05.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:05.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:05.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:05.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:05.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:05.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:05.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:05.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:05.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:05.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:05.261 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:10.269 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:10.269 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:10.269 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:10.269 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:10.269 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:10.269 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:10.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:10.282 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:10.282 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:10.282 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:10.282 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:10.284 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:10.284 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:10.285 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:10.285 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:10.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:10.285 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:10.285 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:10.285 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:10.286 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:10.286 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:10.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:10.287 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:10.287 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:10.287 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:10.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:10.287 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:10.288 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:10.288 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:10.288 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:10.288 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:10.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:10.288 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:10.288 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:10.288 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.290 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:10.290 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:10.290 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:10.291 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:10.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:10.295 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:10.773 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:10.813 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:10.813 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:10.814 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:10.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:10.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:10.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.245 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:37:11.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:11.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:11.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:11.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:11.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.716 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:37:11.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:11.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:12.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:12.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:12.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:12.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:12.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:12.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:12.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:12.158 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:12.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:12.158 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:12.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:12.158 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:12.158 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:12.158 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:17.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:17.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:17.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:17.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:17.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:17.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:17.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:17.180 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:17.180 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:17.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:17.181 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:17.183 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:17.183 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:17.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:17.183 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:17.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:17.183 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:17.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:17.183 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:17.185 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:17.185 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:17.186 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:17.186 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:17.186 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:17.186 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:17.186 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:17.186 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:17.187 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:17.187 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:17.187 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:17.187 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:17.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:17.187 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:17.187 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:17.187 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:17.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:17.190 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:17.190 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:17.190 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:17.194 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:17.673 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:17.712 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:17.714 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:17.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.717 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:17.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:17.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:17.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:17.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:17.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:17.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:17.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:17.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:17.817 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:17.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:17.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:17.818 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:17.818 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:17.818 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:17.818 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:17.818 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:17.818 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:17.818 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:37:22.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:22.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:22.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:22.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:22.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:22.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:22.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:22.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:22.833 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:22.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:22.833 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:22.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:22.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:22.837 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:22.837 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:22.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:22.837 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:22.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:22.838 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:22.839 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:22.839 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:22.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:22.839 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:22.839 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:22.839 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:22.840 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:22.840 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:22.842 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:22.842 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:22.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:22.842 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:22.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:22.842 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:22.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:22.842 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:22.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:22.846 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:22.846 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:22.846 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:22.850 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:23.328 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:23.368 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:23.370 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:23.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.372 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:23.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:23.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:23.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:23.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:23.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:23.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:23.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:23.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:23.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:23.493 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:23.493 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:23.493 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:28.500 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:28.500 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:28.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:28.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:28.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:28.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:28.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:28.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:28.509 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:28.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:28.509 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:28.513 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:28.513 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:28.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:28.514 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:28.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:28.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:28.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:28.514 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:28.518 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:28.519 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:28.519 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:28.519 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:28.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:28.519 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:28.519 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:28.519 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:28.523 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:28.523 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:28.523 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:28.523 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:28.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:28.524 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:28.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:28.524 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:28.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:28.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:28.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:28.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:28.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:28.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:28.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:28.530 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:28.530 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:28.530 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:28.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:28.535 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:29.012 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:29.059 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:29.061 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:29.061 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:29.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:29.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:29.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:29.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:29.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:29.160 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:29.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:29.160 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:29.160 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:29.160 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:29.160 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:29.160 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:34.166 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:34.166 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:34.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:34.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:34.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:34.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:34.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:34.178 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:34.178 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:34.179 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:34.179 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:34.181 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:34.181 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:34.181 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:34.181 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:34.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:34.181 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:34.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:34.182 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:34.183 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:34.183 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:34.183 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:34.183 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:34.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:34.183 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:34.183 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:34.183 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:34.184 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:34.184 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:34.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:34.184 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:34.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:34.184 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:34.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:34.184 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:34.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:34.187 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:34.187 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:34.187 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:34.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:34.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:34.671 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:34.710 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:34.711 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:34.713 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:34.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:34.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:34.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:34.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:34.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:34.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:34.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:34.821 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:34.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:34.821 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:34.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:34.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:39.830 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:39.830 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:39.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:39.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:39.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:39.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:39.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:39.841 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:39.841 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:39.841 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:39.841 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:39.845 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:39.845 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:39.845 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:39.845 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:39.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:39.846 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:39.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:39.846 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:39.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:39.849 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:39.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:39.849 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:39.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:39.850 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:39.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:39.850 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:39.852 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:39.852 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:39.852 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:39.852 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:39.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:39.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:39.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:39.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:39.856 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:39.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:39.857 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:39.857 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:39.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:39.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:39.861 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:40.339 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:40.387 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:40.389 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:40.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.391 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:40.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:40.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:40.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:40.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:40.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:40.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:40.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:40.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:40.481 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:40.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:40.481 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:40.481 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:40.481 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:45.487 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:45.487 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:45.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:45.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:45.487 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:45.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:45.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:45.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:45.490 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:45.491 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:45.491 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:45.492 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:45.492 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:45.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:45.492 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:45.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:45.492 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:45.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:45.492 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:45.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:45.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:45.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:45.493 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:45.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:45.493 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:45.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:45.493 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:45.494 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:45.494 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:45.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:45.494 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:45.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:45.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:45.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:45.494 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:45.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:45.497 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:45.497 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:45.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:45.501 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:45.979 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:46.018 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:46.018 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:46.019 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:46.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:46.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:46.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:46.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:46.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:46.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:46.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:46.120 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:46.120 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:46.120 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:46.120 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:46.120 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:46.120 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:51.126 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:51.126 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:51.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:51.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:51.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:51.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:51.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:51.137 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:51.137 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:51.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:51.138 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:51.140 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:51.141 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:51.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:51.141 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:51.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:51.142 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:51.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:51.142 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:51.144 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:51.144 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:51.144 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:51.144 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:51.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:51.145 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:51.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:51.145 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:51.147 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:51.147 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:51.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:51.147 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:51.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:51.147 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:51.148 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:51.148 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:51.151 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:51.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:51.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:51.152 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:51.152 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:51.152 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:51.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:51.157 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:51.635 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:51.682 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:51.684 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:51.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.686 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:51.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:51.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:51.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:51.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:51.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:51.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:51.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:51.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:51.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:51.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:51.773 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:37:51.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:51.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:56.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:37:56.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:37:56.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:56.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:56.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:56.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:56.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:37:56.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:56.790 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:56.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:37:56.790 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:37:56.797 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:37:56.798 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:37:56.798 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:56.798 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:56.798 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:37:56.798 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:37:56.799 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:37:56.799 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:37:56.804 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:37:56.805 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:37:56.805 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:56.805 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:56.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:37:56.805 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:37:56.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:37:56.806 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:37:56.811 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:37:56.811 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:37:56.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:56.811 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:37:56.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:37:56.812 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:37:56.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:37:56.812 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:37:56.818 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:37:56.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:37:56.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:37:56.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:37:56.818 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:37:56.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:37:56.819 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:37:56.819 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:37:56.819 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:37:56.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:37:56.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:37:56.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:37:56.824 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:37:57.302 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:37:57.350 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:37:57.351 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:37:57.353 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:37:57.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:37:57.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:37:57.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:37:57.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:37:57.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:37:57.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:37:57.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:37:57.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:37:57.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:37:57.774 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:37:57.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:57.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:57.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:57.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:58.245 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:37:58.718 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:37:58.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:58.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:58.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:58.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:37:59.191 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:37:59.663 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:37:59.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:37:59.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:37:59.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:37:59.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:00.134 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:38:00.607 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:38:00.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:00.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:00.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:00.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:00.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:00.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:00.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:00.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:00.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:00.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:00.821 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:00.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:00.822 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:00.822 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:00.822 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:00.822 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:00.822 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:00.822 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:00.822 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:05.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:05.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:05.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:05.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:05.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:05.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:05.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:05.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:05.833 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:05.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:05.833 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:05.834 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:05.834 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:05.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:05.834 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:05.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:05.834 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:05.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:05.834 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:05.837 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:05.838 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:05.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:05.838 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:05.839 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:05.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:05.839 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:05.841 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:05.842 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:05.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:05.842 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:05.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:05.842 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:05.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:05.842 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:05.849 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:05.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:05.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:05.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:05.849 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.850 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:38:05.850 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:38:05.850 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:05.850 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:05.855 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:38:06.331 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:38:06.380 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:38:06.381 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:38:06.382 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:38:06.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:06.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:06.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:06.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:06.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:06.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:06.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:06.397 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:06.397 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:06.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:06.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:06.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:06.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:06.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:06.803 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:38:06.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:06.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:06.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:06.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:06.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:06.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:06.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:06.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:06.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:06.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:06.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:06.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:06.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:06.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:06.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:06.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:06.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:06.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:06.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:06.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:06.950 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:06.950 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:06.950 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:06.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:06.951 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:06.951 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:06.951 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:06.951 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:06.951 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:06.951 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:06.951 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:06.951 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:11.957 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:11.957 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:11.957 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:11.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:11.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:11.957 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:11.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:11.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:11.964 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:11.965 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:11.965 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:11.968 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:11.968 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:11.969 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:11.969 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:11.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:11.970 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:11.970 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:11.970 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:11.972 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:11.972 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:11.972 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:11.972 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:11.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:11.973 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:11.973 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:11.973 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:11.974 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:11.974 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:11.974 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:11.974 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:11.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:11.975 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:11.975 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:11.975 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:11.977 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:11.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:11.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:11.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:11.977 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:38:11.978 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:38:11.978 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:11.978 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:11.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:11.983 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:38:12.460 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:38:12.505 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:38:12.508 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:38:12.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:12.510 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:38:12.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:12.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:12.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:12.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:12.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:12.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:12.534 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:12.534 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:12.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:12.562 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:12.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:12.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:12.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:12.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:12.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:12.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:12.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:12.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:12.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:12.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:12.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:12.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:12.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:12.932 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:38:12.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:12.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:12.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:12.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:13.404 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:38:13.874 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:38:13.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:13.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:13.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:13.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:14.345 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:38:14.819 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:38:14.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:14.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:14.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:14.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:15.291 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:38:15.763 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:38:15.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:15.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:15.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:15.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:16.237 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:38:16.709 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:38:16.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:16.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:16.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:16.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:17.181 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:38:17.652 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:38:18.123 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:38:18.597 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:38:19.069 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:38:19.541 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:38:20.012 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:38:20.485 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:38:20.958 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:38:21.430 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:38:21.901 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:38:22.372 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:38:22.846 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:38:23.318 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:38:23.790 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:38:24.261 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:38:24.732 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:38:25.205 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:38:25.678 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:38:26.150 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:38:26.624 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:38:27.096 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:38:27.568 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:38:27.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:27.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:27.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:27.864 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=3432 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.864 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=3432 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:27.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:27.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:27.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:27.884 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:27.884 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:27.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:27.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:27.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:27.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:27.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:27.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:27.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:27.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:27.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:27.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:27.901 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:27.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:27.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:27.902 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:27.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:27.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:32.904 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:32.904 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:32.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:32.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:32.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:32.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:32.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:32.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:32.914 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:32.914 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:32.917 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:32.917 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:32.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:32.918 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:32.918 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:32.919 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:32.920 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:32.920 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:32.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:32.921 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:32.921 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:32.921 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:32.923 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:32.923 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:32.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:32.923 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:32.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:32.923 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:32.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.926 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:38:32.926 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:38:32.926 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:32.927 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:32.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:32.931 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:38:33.410 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:38:33.456 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:38:33.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:33.459 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:38:33.460 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:38:33.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:33.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:33.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:33.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:33.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:33.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:33.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:33.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:33.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:33.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:33.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:33.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:33.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:33.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:33.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:33.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:33.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:33.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:33.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:33.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:33.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:33.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:33.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:33.806 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:33.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:33.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:33.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:33.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:33.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:33.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:33.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:33.845 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:33.845 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:33.845 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:33.845 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:33.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:33.846 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:33.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:33.846 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:33.846 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:33.846 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:33.846 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:33.846 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:33.847 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:38.848 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:38.849 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:38.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:38.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:38.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:38.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:38.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:38.857 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:38.857 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:38.857 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:38.857 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:38.859 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:38.860 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:38.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:38.860 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:38.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:38.861 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:38.861 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:38.861 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:38.862 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:38.862 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:38.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:38.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:38.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:38.862 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:38.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:38.862 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:38.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:38.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:38.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:38.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:38.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:38.864 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:38.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:38.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:38:38.867 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:38:38.867 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:38.867 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:38.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:38.872 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:38:39.351 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:38:39.393 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:38:39.394 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:38:39.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:39.397 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:38:39.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:39.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:39.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:39.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:39.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:39.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:39.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:39.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:39.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:38:39.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:39.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:39.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:39.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:39.823 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:38:39.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:39.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:39.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:39.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:40.294 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:38:40.765 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:38:40.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:40.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:40.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:40.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:41.236 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:38:41.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:41.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:41.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:41.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:38:41.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:38:41.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:38:41.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:38:41.478 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:38:41.478 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:38:41.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:38:41.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:38:41.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:38:41.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:38:41.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:38:41.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:38:41.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:38:41.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:41.548 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:41.548 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:41.548 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:41.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:41.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:41.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:41.548 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=576 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=576 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=576 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=576 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=576 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=576 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=577 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=578 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=579 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:41.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=580 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:38:46.541 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:46.541 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:46.541 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:46.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:46.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:46.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:46.545 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:46.546 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:46.546 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:46.546 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:46.546 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:46.547 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:46.547 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:46.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:46.548 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:46.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:46.548 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:46.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:46.548 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:46.549 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:46.549 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:46.549 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:46.549 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:46.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:46.549 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:46.549 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:46.549 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:46.551 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:46.551 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:46.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:46.551 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:46.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:46.551 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:46.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:46.551 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:46.553 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:46.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:46.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:46.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:46.553 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:46.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:38:46.554 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:38:46.554 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:46.554 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:46.555 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:46.555 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:46.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:51.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:51.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:51.557 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:51.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:51.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:51.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:51.560 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:51.561 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:51.561 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:51.561 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:38:51.561 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:38:51.562 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:38:51.562 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:38:51.562 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:51.562 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:51.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:51.562 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:38:51.562 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:38:51.562 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:38:51.563 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:38:51.563 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:38:51.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:51.563 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:51.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:51.563 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:38:51.564 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:38:51.564 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:38:51.564 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:38:51.564 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:38:51.564 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:51.565 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:38:51.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:51.565 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:38:51.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:38:51.565 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.566 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:38:51.566 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:38:51.566 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:38:51.567 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.567 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:51.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:51.568 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:38:51.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:56.282 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.128.20:5700'
2026-01-29 02:38:56.282 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.128.20:5802)
2026-01-29 02:38:56.282 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.128.20:5801)
2026-01-29 02:38:56.282 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.128.22:6700'
2026-01-29 02:38:56.283 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.128.22:6802)
2026-01-29 02:38:56.283 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.128.22:6801)
2026-01-29 02:38:56.283 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.128.20:5700/1'
2026-01-29 02:38:56.283 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.128.20:5804)
2026-01-29 02:38:56.283 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.128.20:5803)
2026-01-29 02:38:56.283 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.128.20:5700/2'
2026-01-29 02:38:56.283 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.128.20:5806)
2026-01-29 02:38:56.283 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.128.20:5805)
2026-01-29 02:38:56.283 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.128.20:5700/3'
2026-01-29 02:38:56.283 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.128.20:5808)
2026-01-29 02:38:56.283 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.128.20:5807)
2026-01-29 02:38:56.283 [INFO] fake_trx.py:429 Init complete
2026-01-29 02:38:56.283 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-01-29 02:38:56.803 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:38:56.803 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:38:56.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:38:56.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:38:56.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:38:56.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:13.887 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:13.887 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:13.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:13.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:13.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:13.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:18.942 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:18.942 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:18.942 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:18.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:18.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:18.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:23.984 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:23.984 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:23.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:23.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:23.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:23.984 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:29.035 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:29.035 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:29.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:29.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:29.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:29.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:34.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:34.058 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:34.058 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:34.058 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:34.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:34.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:39.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:39.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:39.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:39.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:39.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:39.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:44.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:44.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:44.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:44.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:44.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:44.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:49.223 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:49.223 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:49.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:49.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:49.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:49.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:54.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:54.274 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:54.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:54.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:54.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:54.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:59.329 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:39:59.329 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:39:59.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:39:59.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:39:59.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:39:59.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:39:59.349 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:39:59.349 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:59.349 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:39:59.349 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:59.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:39:59.350 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:39:59.350 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:39:59.350 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 0 -> 1
2026-01-29 02:39:59.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:39:59.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:39:59.350 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 0 -> 1
2026-01-29 02:39:59.350 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:39:59.350 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 0 -> 1
2026-01-29 02:39:59.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:39:59.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:39:59.350 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 0 -> 1
2026-01-29 02:40:04.385 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:04.385 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:04.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:04.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:04.385 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:04.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:09.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:09.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:09.440 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:09.440 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:09.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:09.440 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:09.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:09.440 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:09.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:09.440 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:40:14.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:14.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:14.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:14.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:14.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:14.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:19.553 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:19.553 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:19.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:19.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:19.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:19.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:24.611 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:24.612 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:24.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:24.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:24.612 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:24.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:29.715 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:29.715 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:29.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:29.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:29.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:29.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:35.856 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.128.20:5700'
2026-01-29 02:40:35.857 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.128.20:5802)
2026-01-29 02:40:35.857 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.128.20:5801)
2026-01-29 02:40:35.857 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.128.22:6700'
2026-01-29 02:40:35.857 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.128.22:6802)
2026-01-29 02:40:35.857 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.128.22:6801)
2026-01-29 02:40:35.857 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.128.20:5700/1'
2026-01-29 02:40:35.857 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.128.20:5804)
2026-01-29 02:40:35.857 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.128.20:5803)
2026-01-29 02:40:35.857 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.128.20:5700/2'
2026-01-29 02:40:35.857 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.128.20:5806)
2026-01-29 02:40:35.857 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.128.20:5805)
2026-01-29 02:40:35.857 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.128.20:5700/3'
2026-01-29 02:40:35.857 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.128.20:5808)
2026-01-29 02:40:35.857 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.128.20:5807)
2026-01-29 02:40:35.857 [INFO] fake_trx.py:429 Init complete
2026-01-29 02:40:35.857 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-01-29 02:40:36.423 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:36.423 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:36.424 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:36.424 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:36.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:36.424 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:40.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:40.418 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:40.418 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:40.418 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:40.419 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 0 -> 1
2026-01-29 02:40:40.427 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:40:40.428 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:40:40.428 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:40.429 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:40.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:40.429 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:40:40.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:40.430 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 0 -> 1
2026-01-29 02:40:40.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:40:40.434 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:40:40.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:40.434 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:40.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:40.434 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:40:40.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:40.434 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 0 -> 1
2026-01-29 02:40:40.438 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:40:40.438 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:40:40.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:40.438 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:40.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:40.439 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:40:40.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:40.439 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 0 -> 1
2026-01-29 02:40:40.442 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:40:40.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:40:40.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:40:40.443 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:40:40.443 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:40:40.443 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:40:40.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:40.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:40.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:40.448 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:40:40.925 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:40:40.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:40.983 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:40:40.985 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:40:40.987 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:40:41.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:41.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:41.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:41.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:41.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:41.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:41.011 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:41.011 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:41.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:41.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:41.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:41.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:41.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:41.397 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:40:41.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:41.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:41.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:41.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:41.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:41.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:41.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:41.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:41.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:41.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:41.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:41.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:41.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:41.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:41.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:41.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:41.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:41.696 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:41.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:41.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:41.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:41.869 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:40:42.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:42.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:42.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:42.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:42.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:42.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:42.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:42.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:42.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:42.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:42.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:42.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:42.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:42.340 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:40:42.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:42.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:42.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:42.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:42.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:42.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:42.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:42.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:42.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:42.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:42.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:42.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:42.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:42.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:42.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:42.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:42.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:42.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:42.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:42.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:42.813 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:40:42.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:42.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:42.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:42.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:42.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:43.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:43.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:43.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:43.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:43.285 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:40:43.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:43.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:43.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:43.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:43.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:43.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:43.289 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:43.289 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:43.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:43.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:43.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:43.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:43.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:43.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:43.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:43.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:43.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:43.758 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:40:44.231 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:40:44.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:44.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:44.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:44.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:44.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:44.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:44.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:44.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:44.314 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:44.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:44.314 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:44.314 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:44.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:44.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:44.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:44.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:44.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:44.499 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:44.499 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:40:44.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:44.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:44.704 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:40:45.177 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:40:45.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:45.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:45.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:45.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:45.321 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:45.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:45.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:45.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:45.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:45.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:45.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:45.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:45.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:45.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:45.447 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:45.448 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:40:45.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:45.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:45.648 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:40:45.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:45.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:45.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:45.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:45.861 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:45.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:45.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:45.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:45.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:45.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:45.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:45.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:45.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:45.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:45.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:46.121 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:40:46.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:46.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:46.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:46.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:46.593 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:40:46.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:46.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:46.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:46.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:46.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:46.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:46.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:46.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:46.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:46.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:46.905 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:46.905 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:46.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:47.065 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:40:47.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:47.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:47.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:47.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:47.537 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:40:47.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:47.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:47.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:47.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:47.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:47.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:47.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:47.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:47.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:47.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:47.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:47.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:47.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:47.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:48.008 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:40:48.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:48.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:48.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:48.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:48.481 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:40:48.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:48.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:48.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:48.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:48.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:48.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:48.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:48.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:48.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:48.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:48.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:48.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:48.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:48.953 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:40:48.990 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:48.990 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:40:48.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:48.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:49.426 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:40:49.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:49.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:49.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:49.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:49.773 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:49.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:49.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:49.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:49.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:49.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:49.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:49.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:49.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:49.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:49.898 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:40:49.931 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:49.932 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:40:49.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:49.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:50.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:50.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:50.313 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:50.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:50.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:50.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:50.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:50.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:50.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:50.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:50.371 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:40:50.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:50.435 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:50.435 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:50.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:50.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:50.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:50.530 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:50.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:50.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:50.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:50.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:50.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:50.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:50.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:50.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:50.643 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:50.643 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:50.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:50.842 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:40:51.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:51.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:51.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:51.020 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:51.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:51.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:51.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:51.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:51.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:51.042 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:51.042 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:51.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:51.141 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:51.141 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:51.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.314 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:40:51.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:51.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:51.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:51.509 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:51.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:51.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:51.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:51.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:51.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:51.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:51.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:51.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:51.611 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:51.611 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:51.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.784 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:40:51.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:51.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:51.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:51.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:51.999 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:52.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:52.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:52.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:52.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:52.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:52.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:52.018 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:52.018 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:52.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:52.255 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:40:52.290 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:52.290 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:52.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:52.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:52.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:52.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:52.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:52.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:52.649 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:52.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:52.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:52.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:52.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:52.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:52.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:52.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:52.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:52.728 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:40:52.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:52.788 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:52.789 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:52.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:52.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:53.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:53.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:53.139 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:53.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:53.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:53.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:53.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:53.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:53.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:53.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:53.201 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:40:53.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:53.265 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:53.265 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:53.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:53.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:53.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:53.634 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:53.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:53.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:53.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:53.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:40:53.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:40:53.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:40:53.656 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:40:53.673 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:40:53.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:53.735 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:40:53.735 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:40:53.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:53.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:54.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:40:54.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:54.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:54.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:54.122 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:40:54.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:40:54.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:40:54.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:40:54.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:40:54.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:54.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:54.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:54.138 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:54.138 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:54.138 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:54.138 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2957 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2957 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2957 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2958 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:54.139 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:40:59.141 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:40:59.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:40:59.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:59.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:59.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:59.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:59.149 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:40:59.151 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:59.151 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:59.151 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:40:59.151 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:40:59.156 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:40:59.157 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:40:59.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:59.157 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:59.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:40:59.157 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:40:59.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:40:59.157 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:40:59.160 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:40:59.160 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:40:59.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:59.161 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:59.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:40:59.161 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:40:59.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:40:59.161 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:40:59.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:40:59.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:40:59.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:59.164 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:40:59.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:40:59.164 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:40:59.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:40:59.164 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:40:59.168 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:40:59.168 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:40:59.168 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:40:59.173 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:40:59.651 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:40:59.693 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:40:59.695 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:40:59.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.697 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:40:59.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:40:59.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:40:59.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:40:59.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:40:59.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.116 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:41:00.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:00.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:00.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:00.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:00.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:00.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:00.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:00.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:00.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:00.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:00.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:00.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:00.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:00.483 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:41:00.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:00.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:00.483 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=286 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:00.483 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=286 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:00.483 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=286 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:00.483 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=286 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:00.483 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=286 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:00.484 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=286 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:05.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:05.488 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:05.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:05.488 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:05.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:05.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:05.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:05.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:05.498 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:05.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:05.499 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:41:05.503 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:41:05.503 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:41:05.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:05.504 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:05.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:05.505 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:41:05.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:05.505 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:41:05.507 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:41:05.508 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:41:05.508 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:05.508 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:05.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:05.508 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:41:05.508 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:05.508 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:41:05.510 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:41:05.510 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:41:05.511 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:05.511 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:05.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:05.511 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:41:05.511 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:05.511 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:41:05.513 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:41:05.513 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:41:05.513 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:05.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:05.518 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:41:05.996 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:41:06.034 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:41:06.034 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:41:06.034 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:41:06.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:06.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:06.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:06.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:06.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:06.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:06.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:06.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:06.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:06.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:06.076 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:06.076 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:06.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:06.076 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:41:06.076 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:06.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:06.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:06.076 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:06.076 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:06.076 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:06.076 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:06.076 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:06.076 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:11.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:11.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:11.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:11.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:11.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:11.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:11.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:11.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:11.088 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:11.088 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:11.088 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:41:11.092 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:41:11.093 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:41:11.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:11.093 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:11.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:11.093 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:41:11.094 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:11.094 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:41:11.098 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:41:11.098 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:41:11.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:11.098 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:11.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:11.098 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:41:11.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:11.098 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:41:11.101 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:41:11.102 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:41:11.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:11.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:11.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:11.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:41:11.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:11.102 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.106 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:41:11.106 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:41:11.106 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:41:11.107 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:11.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:11.111 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:41:11.590 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:41:11.633 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:41:11.636 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:41:11.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:11.638 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:41:11.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:11.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:11.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:11.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:11.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:11.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:11.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:11.681 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:11.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:11.682 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:11.682 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:11.682 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:41:11.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:11.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:11.683 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:11.683 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:11.683 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:11.683 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:11.683 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:11.683 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:16.685 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:16.685 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:16.685 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:16.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:16.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:16.685 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:16.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:16.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:16.699 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:16.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:16.699 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:41:16.701 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:41:16.701 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:41:16.702 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:16.702 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:16.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:16.702 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:41:16.702 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:16.702 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:41:16.703 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:41:16.703 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:41:16.704 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:16.704 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:16.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:16.704 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:41:16.704 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:16.704 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:41:16.705 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:41:16.705 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:41:16.705 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:16.705 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:16.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:16.705 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:41:16.705 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:16.705 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:41:16.707 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:41:16.707 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:41:16.707 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:16.712 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:41:17.190 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:41:17.231 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:41:17.233 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:41:17.235 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:41:17.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:17.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:17.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:17.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:17.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:17.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:17.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:17.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:17.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:17.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:17.390 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:17.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:17.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:17.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:17.390 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:41:22.398 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:41:22.398 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:41:22.398 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:22.398 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:22.398 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:22.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:22.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:41:22.410 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:22.410 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:22.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:41:22.411 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:41:22.413 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:41:22.413 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:41:22.413 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:22.413 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:22.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:41:22.414 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:41:22.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:41:22.414 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:41:22.415 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:41:22.415 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:41:22.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:22.415 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:22.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:41:22.415 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:41:22.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:41:22.415 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:41:22.416 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:41:22.416 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:41:22.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:22.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:41:22.417 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:41:22.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:41:22.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:41:22.417 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:41:22.420 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:41:22.420 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:41:22.420 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:22.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:41:22.424 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:41:22.903 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:41:22.943 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:41:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:22.946 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:41:22.948 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:41:22.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:22.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:22.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:22.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:22.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:22.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:22.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:22.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:22.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:23.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:23.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:23.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:23.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:23.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:23.374 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:41:23.421 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:23.422 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:23.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:23.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:23.846 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:41:24.319 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:41:24.422 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:24.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:24.423 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:24.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:24.792 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:41:25.264 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:41:25.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:25.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:25.424 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:25.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:25.735 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:41:26.209 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:41:26.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:26.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:26.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:26.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:26.681 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:41:27.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:27.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:27.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:27.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:27.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:27.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:27.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:27.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:27.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:27.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:27.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:27.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:27.153 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:41:27.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:27.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:27.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:27.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:27.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:27.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:27.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:41:27.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:41:27.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:41:27.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:41:27.624 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:41:28.098 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:41:28.570 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:41:29.042 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:41:29.513 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:41:29.987 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:41:30.459 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:41:30.931 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:41:31.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:31.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:31.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:31.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:31.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:31.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:31.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:31.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:31.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:31.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:31.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:31.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:31.402 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:41:31.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:31.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:31.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:31.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:31.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:31.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:31.873 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:41:32.344 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:41:32.817 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:41:33.290 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:41:33.780 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:41:34.253 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:41:34.724 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:41:35.197 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:41:35.670 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:41:35.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:35.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:35.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:35.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:35.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:35.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:35.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:35.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:35.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:35.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:35.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:35.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:35.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:35.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:35.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:35.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:35.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:36.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:36.142 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:41:36.613 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:41:37.087 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:41:37.559 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:41:38.030 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:41:38.504 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:41:38.976 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:41:39.448 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:41:39.919 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:41:40.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:40.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:40.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:40.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:40.131 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=3822 tn=3 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:40.132 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=3822 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:41:40.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:40.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:40.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:40.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:40.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:40.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:40.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:40.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:40.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:40.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:40.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:40.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:40.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:40.392 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:41:40.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:40.865 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:41:41.337 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:41:41.808 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:41:42.282 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:41:42.755 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:41:43.228 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:41:43.701 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:41:44.174 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:41:44.647 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:41:44.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:44.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:44.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:44.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:44.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:44.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:44.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:44.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:44.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:44.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:44.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:44.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:44.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:44.789 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:41:44.789 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:41:44.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:44.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:45.120 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:41:45.594 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:41:45.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:46.067 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:41:46.540 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:41:47.013 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:41:47.485 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:41:47.959 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:41:48.432 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:41:48.904 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:41:49.376 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:41:49.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:49.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:49.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:49.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:49.623 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:41:49.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:49.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:49.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:49.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:49.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:49.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:49.642 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:49.642 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:49.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:49.654 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:41:49.654 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:41:49.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:49.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:49.850 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:41:50.322 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:41:50.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:50.795 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:41:51.268 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:41:51.740 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:41:52.213 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:41:52.686 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:41:53.158 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:41:53.629 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:41:54.101 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:41:54.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:54.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:54.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:54.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:54.502 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:41:54.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:54.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:54.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:54.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:54.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:54.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:54.523 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:54.523 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:54.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:41:54.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:54.574 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:41:54.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:54.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:54.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:54.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:55.047 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:41:55.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:55.518 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:41:55.988 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:41:56.459 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:41:56.932 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:41:57.405 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:41:57.878 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:41:58.351 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:41:58.824 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:41:59.295 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:41:59.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:59.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:59.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:59.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:59.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:41:59.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:41:59.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:41:59.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:59.399 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:59.399 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:59.399 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:41:59.399 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:41:59.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:41:59.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:41:59.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:41:59.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:59.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:41:59.768 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:42:00.241 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:42:00.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:00.713 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:42:01.185 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:42:01.658 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:42:02.131 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:42:02.603 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:42:03.077 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:42:03.549 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:42:04.022 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:42:04.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:04.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:04.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:04.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:04.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:04.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:04.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:04.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:04.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:04.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:04.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:04.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:04.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:04.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:04.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:04.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:04.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:04.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:04.493 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:42:04.966 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:42:05.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:05.439 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:42:05.913 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:42:06.385 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:42:06.858 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:42:07.332 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:42:07.804 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:42:08.276 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:42:08.748 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:42:09.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:09.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:09.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:09.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:09.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:09.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:09.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:09.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:09.035 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:09.035 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:09.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:09.085 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:09.085 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:42:09.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:09.220 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:42:09.693 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:42:09.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:10.165 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:42:10.638 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:42:11.112 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:42:11.584 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:42:12.058 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:42:12.530 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:42:13.003 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:42:13.477 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:42:13.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:13.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:13.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:13.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:13.831 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:13.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:13.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:13.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:13.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:13.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:13.850 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:13.850 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:13.850 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:13.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:13.906 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:13.906 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:42:13.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:13.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:13.949 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:42:14.422 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:42:14.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:14.895 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:42:15.367 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:42:15.839 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:42:16.313 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:42:16.786 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:42:17.259 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:42:17.731 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:42:18.204 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:42:18.677 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:42:18.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:18.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:18.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:18.710 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:18.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:18.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:18.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:18.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:18.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:18.735 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:18.735 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:18.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:18.772 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:18.773 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:18.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:18.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:19.149 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:42:19.621 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:42:20.092 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:42:20.566 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:42:21.038 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:42:21.510 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:42:21.983 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:42:22.456 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:42:22.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:22.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:22.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:22.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:22.834 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:22.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:22.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:22.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:22.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:22.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:22.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:22.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:22.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:22.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:22.880 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:22.880 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:22.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:22.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:22.928 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:42:23.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:23.402 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:42:23.874 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:42:24.346 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:42:24.818 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:42:25.291 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:42:25.764 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:42:26.236 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:42:26.709 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:42:27.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:27.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:27.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:27.105 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:27.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:27.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:27.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:27.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:27.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:27.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:27.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:27.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:27.181 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:42:27.185 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:27.186 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:27.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:27.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:27.654 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:42:28.127 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:42:28.600 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:42:29.071 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:42:29.544 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:42:30.017 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:42:30.489 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:42:30.962 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:42:31.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:31.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:31.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:31.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:31.380 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:31.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:31.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:31.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:31.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:31.399 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:31.399 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:31.399 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:31.399 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:31.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:31.435 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:42:31.437 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:31.437 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:31.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:31.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:31.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:31.907 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:42:32.380 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:42:32.853 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:42:33.325 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:42:33.796 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:42:34.270 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:42:34.742 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:42:35.213 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:42:35.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:35.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:35.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:35.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:35.652 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:35.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:35.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:35.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:35.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:35.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:35.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:35.672 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:35.672 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:35.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:35.682 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:35.682 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:35.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:35.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:35.685 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:42:36.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:36.157 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:42:36.630 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:42:37.102 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:42:37.576 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:42:38.048 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:42:38.520 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:42:38.994 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:42:39.466 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:42:39.939 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:42:40.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:40.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:40.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:40.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:40.081 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:40.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:40.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:40.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:40.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:40.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:40.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:40.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:40.100 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:40.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:40.125 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:40.125 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:40.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:40.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:40.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:40.412 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:42:40.884 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:42:41.357 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:42:41.830 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:42:42.302 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:42:42.775 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:42:43.248 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:42:43.721 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:42:44.192 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:42:44.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:44.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:44.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:44.352 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:44.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:44.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:44.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:44.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:44.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:44.361 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:44.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:44.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:44.377 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:44.377 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:44.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:44.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:44.664 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:42:45.138 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:42:45.610 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:42:46.083 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:42:46.556 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:42:47.029 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:42:47.501 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:42:47.975 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:42:48.447 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 02:42:48.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:48.625 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:48.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:48.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:48.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:42:48.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:42:48.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:42:48.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:42:48.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:42:48.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.691 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:42:48.692 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:42:48.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:48.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:48.918 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 02:42:49.392 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 02:42:49.864 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 02:42:50.337 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 02:42:50.810 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 02:42:51.283 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 02:42:51.756 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 02:42:52.229 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 02:42:52.701 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 02:42:52.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:42:52.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:42:52.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:42:52.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:42:52.898 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:42:52.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:42:52.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:42:52.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:42:52.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:42:52.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:52.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:52.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:52.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:52.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:52.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:42:52.916 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:42:57.921 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:57.921 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:42:57.921 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:57.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:57.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:57.921 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:57.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:57.928 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:57.928 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:57.928 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:42:57.929 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:42:57.932 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:42:57.933 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:42:57.933 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:57.933 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:57.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:57.934 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:42:57.935 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:42:57.935 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:42:57.938 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:42:57.938 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:42:57.938 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:57.939 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:57.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:42:57.939 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:42:57.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:42:57.940 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:42:57.942 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:42:57.942 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:42:57.942 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:57.943 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:42:57.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:42:57.943 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:42:57.943 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:42:57.943 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:42:57.946 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:42:57.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:42:57.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:42:57.947 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:42:57.947 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:42:57.947 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:42:57.949 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:42:57.949 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:42:57.949 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:02.955 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:43:02.955 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:43:02.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:02.955 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:02.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:02.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:02.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:02.968 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:02.968 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:02.968 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:02.969 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:43:02.971 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:43:02.972 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:43:02.972 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:02.972 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:02.972 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:02.973 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:43:02.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:02.973 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:43:02.975 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:43:02.976 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:43:02.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:02.976 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:02.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:02.977 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:43:02.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:02.978 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:43:02.980 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:43:02.981 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:43:02.981 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:02.981 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:02.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:02.982 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:43:02.982 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:02.982 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:43:02.987 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:43:02.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:43:02.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:43:02.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:43:02.987 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:43:02.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:43:02.988 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:43:02.988 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:43:02.988 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:02.993 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:43:03.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:43:03.524 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:43:03.526 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:43:03.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.527 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:43:03.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:03.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:03.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:03.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:03.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:03.547 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:03.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:03.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:03.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:03.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:03.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:03.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:03.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:03.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:03.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:03.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:03.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:03.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:03.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:03.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:03.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:03.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:03.943 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:43:03.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:03.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:03.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:03.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:04.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:04.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:04.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:04.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:04.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:04.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:04.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:04.184 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:04.184 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:04.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:04.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:04.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:04.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:04.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:04.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:04.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:04.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:04.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:04.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:04.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:04.415 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:43:04.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:04.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:04.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:04.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:04.886 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:43:04.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:04.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:04.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:04.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:04.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:04.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:04.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:04.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:04.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:04.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:04.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:04.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:04.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:04.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:04.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:05.357 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:43:05.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:05.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:05.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:05.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:05.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:05.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:05.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:05.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:05.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:05.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:05.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:05.466 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:05.466 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:43:05.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.830 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:43:05.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:05.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:05.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:05.935 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:05.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:05.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:05.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:05.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:05.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:05.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:05.953 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:05.953 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:05.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:05.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:05.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:05.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:06.000 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:06.000 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:43:06.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.302 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:43:06.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:06.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:06.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:06.480 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:06.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:06.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:06.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:06.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:06.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:06.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:06.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:06.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:06.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:06.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:06.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:06.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:06.775 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:43:06.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:06.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:06.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:06.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:07.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:07.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:07.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:07.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:07.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:07.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:07.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:07.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:07.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:07.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:07.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:07.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:07.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:07.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.248 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:43:07.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:07.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:07.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:07.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:07.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:07.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:07.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:07.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:07.581 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:07.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:07.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:07.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:07.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:07.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:07.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:07.720 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:43:07.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:07.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:07.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:07.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:08.193 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:43:08.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:08.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:08.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:08.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:08.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:08.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:08.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:08.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:08.478 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:08.478 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:08.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:08.530 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:08.530 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:43:08.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.664 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:43:08.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:08.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:08.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:08.945 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:08.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:08.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:08.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:08.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:08.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:08.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:08.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:08.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:08.998 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:08.999 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:43:08.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:08.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.137 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:43:09.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:09.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:09.486 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:09.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:09.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:09.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:09.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:09.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:09.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:09.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:09.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.558 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:09.559 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:09.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.609 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:43:09.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:09.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:09.768 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:09.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:09.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:09.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:09.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:09.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:09.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:09.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:09.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:09.825 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:09.825 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:09.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:09.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.080 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:43:10.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:10.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:10.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:10.257 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:10.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:10.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:10.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:10.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:10.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:10.277 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:10.277 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:10.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:10.328 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:10.329 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:10.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.552 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:43:10.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:10.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:10.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:10.747 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:10.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:10.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:10.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:10.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:10.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:10.769 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:10.769 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:10.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:10.817 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:10.817 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:10.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:10.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.022 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:43:11.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:11.235 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:11.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:11.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:11.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:11.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:11.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:11.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:11.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.308 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:11.308 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:11.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:11.416 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:11.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:11.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:11.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:11.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:11.438 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:11.438 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:11.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.495 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:43:11.500 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:11.500 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:11.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:11.906 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:11.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:11.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:11.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:11.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:11.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:11.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:11.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:11.967 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:43:11.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:11.973 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:11.973 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:11.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:11.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:12.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:12.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:12.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:12.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:12.394 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:12.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:12.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:12.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:12.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:12.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:12.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:12.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:12.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:12.438 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:43:12.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:12.452 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:12.453 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:12.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:12.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:12.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:12.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:12.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:12.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:12.888 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:12.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:12.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:12.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:12.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:12.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:12.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:43:12.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:43:12.895 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:43:12.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:12.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:12.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:12.895 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:12.895 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:12.895 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:12.895 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:12.895 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:12.895 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:17.902 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:43:17.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:43:17.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:17.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:17.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:17.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:17.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:17.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:17.914 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:17.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:17.915 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:43:17.921 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:43:17.921 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:43:17.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:17.922 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:17.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:17.923 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:43:17.924 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:17.924 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:43:17.926 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:43:17.926 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:43:17.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:17.927 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:17.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:17.927 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:43:17.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:17.927 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:43:17.929 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:43:17.930 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:43:17.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:17.930 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:17.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:17.930 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:43:17.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:17.930 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:43:17.933 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:43:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:43:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:43:17.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:43:17.933 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:43:17.934 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:43:17.934 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:43:17.934 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:43:17.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:17.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:17.939 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:43:18.417 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:43:18.460 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:43:18.462 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:43:18.464 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:43:18.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:18.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:18.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:18.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:18.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:18.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:18.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:18.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:18.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:18.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:18.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:18.518 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:18.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:18.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:18.889 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:43:18.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:18.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:18.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:18.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:19.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:19.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:19.360 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:43:19.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:19.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:19.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:19.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:19.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:19.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:19.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:19.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:19.583 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:19.583 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:19.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:19.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:19.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:19.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:19.831 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:43:19.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:19.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:19.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:19.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:20.304 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:43:20.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:20.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:20.777 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:43:20.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:20.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:20.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:20.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:20.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:21.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:21.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:21.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:21.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:21.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:21.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:21.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:21.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:21.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:21.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:21.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:21.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:21.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:21.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:21.249 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:43:21.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:21.720 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:43:21.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:21.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:21.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:21.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:22.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:22.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:22.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:22.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:22.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:22.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:22.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:22.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:22.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:22.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:22.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:22.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:22.193 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:43:22.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:22.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:22.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:22.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:22.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:22.666 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:43:22.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:22.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:22.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:22.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:23.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:23.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:23.138 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:43:23.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:23.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:23.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:23.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:23.611 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:43:23.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:23.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:23.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:23.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:23.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:23.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:23.617 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:23.617 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:23.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:23.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:23.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:23.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:23.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:24.084 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:43:24.556 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:43:24.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:24.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:25.027 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:43:25.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:25.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:25.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:25.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:25.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:25.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:25.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:25.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:25.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:25.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:25.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:25.177 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:25.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:25.225 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:25.225 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:43:25.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:25.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:25.500 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:43:25.974 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:43:26.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:26.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:26.446 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:43:26.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:26.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:26.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:26.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:26.664 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:26.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:26.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:26.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:26.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:26.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:26.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:26.684 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:26.684 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:26.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:26.736 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:26.736 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:43:26.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:26.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:26.917 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:43:27.391 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:43:27.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:27.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:27.862 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:43:28.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:28.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:28.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:28.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:28.170 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:28.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:28.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:28.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:28.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:28.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:28.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:28.190 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:28.190 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:28.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:28.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:28.243 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:28.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:28.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:28.334 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:43:28.806 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:43:29.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:29.280 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:43:29.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:29.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:29.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:29.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:29.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:29.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:29.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:29.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:29.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:29.690 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:29.690 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:29.690 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:29.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:29.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:29.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:29.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:29.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:29.752 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:43:30.224 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:43:30.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:30.695 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:43:30.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:31.166 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:43:31.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:31.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:31.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:31.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:31.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:31.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:31.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:31.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:31.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:31.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:31.197 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:31.197 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:31.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:31.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:31.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:31.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:31.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:31.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:31.639 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:43:32.112 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:43:32.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:32.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:32.584 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:43:33.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:33.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:33.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:33.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:33.042 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=3263 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:33.055 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:43:33.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:33.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:33.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:33.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:33.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:33.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:33.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:33.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:33.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:33.109 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:33.109 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:43:33.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:33.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:33.528 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:43:33.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:34.000 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:43:34.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:34.473 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:43:34.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:34.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:34.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:34.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:34.487 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:34.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:34.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:34.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:34.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:34.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:34.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:34.508 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:34.508 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:34.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:34.557 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:34.557 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:43:34.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:34.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:34.945 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:43:35.418 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:43:35.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:35.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:35.890 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:43:35.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:35.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:35.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:35.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:35.993 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:36.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:36.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:36.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:36.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:36.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:36.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:36.015 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:36.015 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:36.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:36.061 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:36.061 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:36.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:36.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:36.362 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:43:36.835 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:43:36.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:36.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:37.307 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:43:37.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:37.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:37.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:37.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:37.465 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:37.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:37.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:37.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:37.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:37.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:37.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:37.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:37.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:37.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:37.525 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:37.525 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:37.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:37.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:37.778 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:43:38.251 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:43:38.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:38.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:38.724 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:43:38.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:38.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:38.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:38.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:38.902 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:38.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:38.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:38.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:38.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:38.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:38.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:38.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:38.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:38.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:38.966 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:38.966 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:38.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:38.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:39.196 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:43:39.668 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:43:39.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:39.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:40.141 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:43:40.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:40.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:40.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:40.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:40.337 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:40.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:40.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:40.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:40.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:40.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:40.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:40.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:40.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:40.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:40.397 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:40.397 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:40.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:40.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:40.613 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:43:41.085 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:43:41.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:41.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:41.558 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:43:41.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:41.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:41.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:41.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:41.767 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:41.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:41.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:41.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:41.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:41.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:41.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:41.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:41.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:41.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:41.841 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:41.841 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:41.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:41.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:42.030 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:43:42.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:42.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:42.503 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:43:42.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:42.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:42.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:42.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:42.896 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:42.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:42.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:42.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:42.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:42.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:42.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:42.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:42.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:42.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:42.975 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:43:42.979 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:42.979 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:42.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:42.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:43.448 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:43:43.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:43.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:43.920 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:43:44.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:44.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:44.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:44.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:44.333 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:44.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:44.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:44.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:44.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:44.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:44.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:44.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:44.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:44.393 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:43:44.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:44.406 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:44.406 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:44.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:44.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:44.866 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:43:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:45.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:45.338 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:43:45.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:45.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:45.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:45.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:45.768 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:45.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:45.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:45.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:45.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:45.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:45.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:45.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:45.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:45.809 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:43:45.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:45.838 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:43:45.838 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:43:45.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:45.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:46.283 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:43:46.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:46.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:46.756 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:43:47.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:47.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:47.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:47.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:47.206 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:43:47.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:47.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:47.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:47.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:47.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:47.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:43:47.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:43:47.214 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:43:47.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:47.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:47.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:47.214 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:47.214 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:47.214 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:47.214 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:47.214 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:47.214 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:43:52.220 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:43:52.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:43:52.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:52.220 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:52.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:52.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:52.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:43:52.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:52.227 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:52.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:43:52.228 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:43:52.230 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:43:52.230 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:43:52.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:52.231 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:52.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:43:52.231 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:43:52.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:43:52.231 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:43:52.233 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:43:52.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:43:52.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:52.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:52.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:43:52.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:43:52.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:43:52.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:43:52.235 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:43:52.235 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:43:52.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:52.235 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:43:52.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:43:52.235 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:43:52.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:43:52.235 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:43:52.238 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:43:52.238 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:43:52.238 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:43:52.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:43:52.243 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:43:52.721 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:43:52.763 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:43:52.766 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:43:52.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:52.768 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:43:52.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:52.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:52.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:52.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:52.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:52.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:52.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:52.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:52.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:52.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:52.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:52.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:52.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:53.192 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:43:53.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:53.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:53.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:53.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:53.664 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:43:54.135 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:43:54.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:54.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:54.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:54.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:54.609 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:43:55.081 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:43:55.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:55.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:55.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:55.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:55.553 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:43:56.024 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:43:56.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:56.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:56.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:56.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:56.497 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:43:56.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:56.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:56.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:56.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:56.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:43:56.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:43:56.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:43:56.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:56.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:56.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:56.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:43:56.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:43:56.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:43:56.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:43:56.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:43:56.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:56.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:43:56.968 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:43:57.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:43:57.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:43:57.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:43:57.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:43:57.441 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:43:57.913 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:43:58.384 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:43:58.858 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:43:59.330 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:43:59.802 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:44:00.273 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:44:00.747 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:44:00.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:00.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:00.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:00.965 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:00.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:00.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:00.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:00.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:00.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:00.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:00.986 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:00.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:01.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:01.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:01.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:01.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:01.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:01.218 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:44:01.690 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:44:02.161 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:44:02.634 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:44:03.107 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:44:03.579 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:44:04.050 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:44:04.521 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:44:04.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:04.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:04.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:04.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:04.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:04.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:04.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:04.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:04.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:04.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:04.981 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:04.981 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:04.994 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:44:05.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:05.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:05.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:05.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:05.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:05.467 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:44:05.939 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:44:06.412 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:44:06.885 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:44:07.357 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:44:07.828 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:44:08.301 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:44:08.774 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:44:09.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:09.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:09.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:09.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:09.246 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:44:09.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:09.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:09.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:09.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:09.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:09.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:09.254 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:09.254 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:09.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:09.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:09.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:09.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:09.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:09.717 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:44:10.188 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:44:10.662 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:44:11.134 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:44:11.608 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:44:12.081 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:44:12.553 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:44:13.019 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:44:13.490 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:44:13.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:13.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:13.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:13.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:13.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:13.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:13.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:13.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:13.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:13.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:13.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:13.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:13.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:13.962 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:44:13.966 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:13.966 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:44:13.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:13.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:14.435 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:44:14.908 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:44:15.382 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:44:15.854 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:44:16.326 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:44:16.800 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:44:17.272 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:44:17.745 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:44:18.219 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:44:18.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:18.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:18.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:18.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:18.299 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:44:18.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:18.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:18.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:18.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:18.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:18.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:18.319 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:18.319 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:18.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:18.365 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:18.365 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:44:18.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:18.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:18.690 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:44:19.164 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:44:19.637 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:44:20.109 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:44:20.582 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:44:21.055 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:44:21.527 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:44:21.999 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:44:22.473 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:44:22.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:22.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:22.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:22.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:22.699 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:44:22.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:22.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:22.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:22.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:22.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:22.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:22.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:22.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:22.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:44:22.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:22.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:22.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:22.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:22.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:22.946 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:44:23.416 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:44:23.890 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:44:24.363 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:44:24.834 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:44:25.304 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:44:25.778 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:44:26.251 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:44:26.723 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:44:27.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:27.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:27.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:27.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:27.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:27.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:27.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:27.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:27.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:27.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:27.109 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:27.109 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:27.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:27.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:27.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:27.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:27.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:27.196 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:44:27.669 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:44:28.141 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:44:28.612 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:44:29.085 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:44:29.558 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:44:30.030 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:44:30.504 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:44:30.976 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:44:31.449 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:44:31.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:31.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:31.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:31.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:31.486 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=8476 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:44:31.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:31.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:31.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:31.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:31.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:31.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:31.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:31.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:31.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:44:31.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:31.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:31.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:31.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:31.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:31.922 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:44:32.395 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:44:32.867 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:44:33.338 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:44:33.812 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:44:34.285 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:44:34.757 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:44:35.228 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:44:35.702 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:44:35.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:35.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:35.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:35.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:35.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:35.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:35.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:35.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:35.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:35.784 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:35.784 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:35.784 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:35.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:35.833 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:35.833 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:44:35.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:35.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:36.174 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:44:36.646 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:44:37.120 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:44:37.594 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:44:38.068 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:44:38.541 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:44:39.015 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:44:39.488 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:44:39.962 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:44:40.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:40.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:40.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:40.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:40.107 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:44:40.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:40.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:40.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:40.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:40.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:40.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:40.115 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:40.115 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:40.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:40.165 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:40.165 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:44:40.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:40.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:40.434 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:44:40.908 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:44:41.381 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:44:41.853 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:44:42.326 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:44:42.799 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:44:43.272 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:44:43.745 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:44:44.218 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:44:44.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:44.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:44.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:44.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:44.507 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:44:44.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:44.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:44.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:44.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:44.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:44.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:44.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:44.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:44.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:44.578 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:44.578 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:44.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:44.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:44.690 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:44:45.163 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:44:45.636 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:44:46.108 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:44:46.582 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:44:47.055 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:44:47.527 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:44:48.001 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:44:48.473 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:44:48.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:48.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:48.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:48.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:48.634 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:44:48.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:48.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:48.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:48.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:48.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:48.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:48.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:48.656 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:48.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:48.716 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:48.716 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:48.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:48.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:48.945 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:44:49.417 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:44:49.891 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:44:50.364 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:44:50.837 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:44:51.309 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:44:51.781 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:44:52.253 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:44:52.727 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:44:52.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:52.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:52.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:52.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:52.905 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:44:52.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:52.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:52.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:52.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:52.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:52.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:52.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:52.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:52.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:52.998 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:52.998 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:52.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:52.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:53.199 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:44:53.673 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:44:54.145 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:44:54.618 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:44:55.091 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:44:55.564 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:44:56.036 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:44:56.510 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:44:56.983 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:44:57.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:57.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:57.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:57.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:57.180 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:44:57.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:44:57.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:44:57.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:44:57.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:57.201 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:44:57.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:44:57.202 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:44:57.202 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:44:57.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:44:57.250 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:44:57.250 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:44:57.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:57.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:44:57.455 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:44:57.928 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:44:58.401 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:44:58.873 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:44:59.344 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:44:59.818 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:45:00.290 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:45:00.762 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:45:01.236 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:45:01.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:01.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:01.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:01.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:01.447 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:45:01.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:01.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:01.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:01.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:01.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:01.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:01.468 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:01.468 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:01.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:01.519 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:45:01.519 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:45:01.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:01.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:01.707 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:45:02.180 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:45:02.654 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:45:03.126 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:45:03.598 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:45:04.071 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:45:04.544 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:45:05.018 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:45:05.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:05.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:05.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:05.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:05.413 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:45:05.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:05.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:05.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:05.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:05.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:05.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:05.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:05.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:05.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:05.490 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:45:05.495 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:45:05.495 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:45:05.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:05.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:05.964 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:45:06.436 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:45:06.910 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:45:07.383 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:45:07.855 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:45:08.328 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:45:08.801 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:45:09.273 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:45:09.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:09.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:09.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:09.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:09.686 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:45:09.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:09.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:09.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:09.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:09.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:09.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:09.702 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:09.702 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:09.743 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:45:09.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:09.749 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:45:09.749 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:45:09.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:09.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:10.215 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:45:10.688 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:45:11.160 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:45:11.632 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:45:12.105 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:45:12.578 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:45:13.050 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:45:13.523 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:45:13.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:13.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:13.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:13.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:13.951 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:45:13.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:13.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:13.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:13.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:13.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:13.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:13.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:13.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:13.995 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:45:14.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:14.021 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:45:14.021 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:45:14.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:14.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:14.468 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:45:14.939 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:45:15.412 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:45:15.884 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:45:16.356 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:45:16.828 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:45:17.301 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:45:17.773 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:45:18.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:18.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:18.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:18.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:18.224 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:45:18.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:18.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:18.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:18.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:18.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:18.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:18.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:18.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:18.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:45:18.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:45:18.233 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:45:23.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:45:23.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:45:23.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:23.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:23.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:23.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:23.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:23.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:23.247 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:23.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:23.248 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:45:23.250 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:45:23.250 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:45:23.250 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:23.251 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:23.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:23.251 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:45:23.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:23.251 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:45:23.253 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:45:23.253 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:45:23.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:23.253 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:23.253 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:23.253 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:45:23.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:23.253 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:45:23.255 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:45:23.255 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:45:23.255 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:23.255 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:23.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:23.255 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:45:23.255 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:23.255 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:23.258 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:45:23.258 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:45:23.258 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:45:23.258 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:45:23.260 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:45:23.260 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:23.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:45:28.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:45:28.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:28.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:28.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:28.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:28.280 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:45:28.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:28.281 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:28.282 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:45:28.282 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:45:28.284 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:45:28.285 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:45:28.285 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:28.285 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:28.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:45:28.285 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:45:28.286 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:45:28.286 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:45:28.287 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:45:28.287 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:45:28.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:28.287 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:28.287 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:45:28.287 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:45:28.288 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:45:28.288 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:45:28.289 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:45:28.290 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:45:28.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:28.290 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:45:28.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:45:28.290 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:45:28.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:45:28.290 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:45:28.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:45:28.294 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:45:28.294 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:45:28.294 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:45:28.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:45:28.298 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:45:28.777 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:45:28.820 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:45:28.821 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:45:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:28.822 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:45:28.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:28.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:28.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:28.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:28.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:28.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:28.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:28.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:28.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:28.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:28.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:28.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:28.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:29.248 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:45:29.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:29.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:29.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:29.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:29.720 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:45:30.192 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:45:30.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:30.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:30.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:30.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:30.664 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:45:31.137 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:45:31.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:31.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:31.299 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:31.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:31.609 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:45:32.082 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:45:32.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:32.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:32.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:32.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:32.553 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:45:32.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:32.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:32.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:32.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:32.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:32.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:32.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:32.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:32.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:32.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:32.946 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:32.946 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:32.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:32.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:32.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:32.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:32.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:33.023 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:45:33.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:45:33.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:45:33.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:45:33.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:45:33.494 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:45:33.967 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:45:34.440 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:45:34.912 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:45:35.383 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:45:35.854 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:45:36.327 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:45:36.799 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:45:37.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:37.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:37.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:37.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:37.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:37.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:37.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:37.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:37.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:37.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:37.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:37.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:37.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:37.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:37.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:37.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:37.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:37.272 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:45:37.745 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:45:38.217 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:45:38.690 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:45:39.163 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:45:39.636 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:45:40.108 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:45:40.581 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:45:41.054 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:45:41.526 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:45:41.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:41.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:41.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:41.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:41.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:41.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:41.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:41.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:41.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:41.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:41.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:41.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:41.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:41.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:41.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:41.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:41.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:41.997 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:45:42.470 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:45:42.943 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:45:43.415 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:45:43.886 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:45:44.360 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:45:44.832 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:45:45.304 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:45:45.778 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:45:45.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:45.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:45.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:45.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:45.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:45.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:45.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:45.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:45.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:45.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:45.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:45.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:45.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:45.989 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:45.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:45.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:46.250 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:45:46.723 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:45:47.196 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:45:47.669 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:45:48.141 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:45:48.612 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:45:49.086 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:45:49.559 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:45:50.030 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:45:50.503 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:45:50.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:50.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:50.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:50.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:50.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:50.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:50.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:50.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:50.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:50.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:50.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:50.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:50.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:50.622 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:45:50.622 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:45:50.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:50.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:50.976 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:45:51.450 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:45:51.922 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:45:52.395 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:45:52.869 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:45:53.341 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:45:53.813 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:45:54.287 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:45:54.759 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:45:55.233 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:45:55.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:55.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:55.437 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:55.437 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:55.437 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:45:55.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:45:55.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:45:55.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:45:55.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:55.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:45:55.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:45:55.457 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:45:55.457 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:45:55.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:45:55.505 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:45:55.505 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:45:55.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:55.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:45:55.706 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:45:56.179 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:45:56.651 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:45:57.123 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:45:57.597 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:45:58.070 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:45:58.541 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:45:59.014 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:45:59.483 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:45:59.954 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:46:00.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:00.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:00.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:00.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:00.319 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:00.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:00.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:00.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:00.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:00.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:00.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:00.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:00.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:00.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:00.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:00.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:00.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:00.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:00.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:00.427 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:46:00.900 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:46:01.372 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:46:01.843 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:46:02.314 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:46:02.788 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:46:03.260 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:46:03.734 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:46:04.206 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:46:04.679 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:46:05.150 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:46:05.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:05.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:05.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:05.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:05.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:05.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:05.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:05.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:05.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:05.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:05.210 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:05.210 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:05.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:05.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:05.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:05.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:05.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:05.623 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:46:06.096 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:46:06.568 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:46:07.042 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:46:07.514 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:46:07.986 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:46:08.457 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:46:08.931 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:46:09.403 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:46:09.876 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:46:10.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:10.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:10.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:10.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:10.083 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:10.083 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:10.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:10.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:10.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:10.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:10.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:10.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:10.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:46:10.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:10.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:10.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:10.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:10.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:10.347 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:46:10.819 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:46:11.293 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:46:11.765 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:46:12.236 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:46:12.710 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:46:13.182 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:46:13.656 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:46:14.128 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:46:14.600 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:46:14.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:14.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:14.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:14.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:14.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:14.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:14.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:14.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:14.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:14.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:14.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:14.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:14.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:14.893 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:14.893 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:46:14.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:14.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:15.073 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:46:15.545 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:46:16.018 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:46:16.491 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:46:16.964 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:46:17.438 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:46:17.912 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:46:18.384 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:46:18.856 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:46:19.330 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:46:19.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:19.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:19.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:19.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:19.643 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:19.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:19.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:19.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:19.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:19.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:19.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:19.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:19.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:19.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:19.709 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:19.709 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:46:19.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:19.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:19.802 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:46:20.275 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:46:20.748 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:46:21.220 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:46:21.694 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:46:22.167 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:46:22.639 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:46:23.112 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:46:23.585 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:46:24.057 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:46:24.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:24.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:24.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:24.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:24.526 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:24.530 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:46:24.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:24.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:24.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:24.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:24.542 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:24.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:24.542 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:24.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:24.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:24.589 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:24.589 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:24.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:24.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:25.003 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:46:25.475 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:46:25.949 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:46:26.422 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:46:26.895 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:46:27.368 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:46:27.840 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:46:28.314 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:46:28.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:28.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:28.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:28.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:28.633 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:28.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:28.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:28.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:28.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:28.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:28.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:28.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:28.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:28.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:28.701 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:28.701 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:28.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:28.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:28.786 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:46:29.257 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:46:29.730 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:46:30.203 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:46:30.675 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 02:46:31.149 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 02:46:31.622 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 02:46:32.094 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 02:46:32.568 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 02:46:32.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:32.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:32.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:32.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:32.906 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:32.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:32.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:32.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:32.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:32.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:32.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:32.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:32.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:32.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:32.976 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:32.977 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:32.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:32.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:33.040 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 02:46:33.512 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 02:46:33.986 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 02:46:34.458 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 02:46:34.931 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 02:46:35.404 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 02:46:35.877 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 02:46:36.349 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 02:46:36.823 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 02:46:37.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:37.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:37.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:37.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:37.178 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:37.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:37.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:37.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:37.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:37.196 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:37.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:37.197 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:37.197 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:37.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:37.245 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:37.245 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:37.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:37.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:37.294 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 02:46:37.767 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 02:46:38.240 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 02:46:38.713 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 02:46:39.185 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 02:46:39.657 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 02:46:40.130 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 02:46:40.603 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 02:46:41.076 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 02:46:41.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:41.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:41.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:41.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:41.452 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:41.452 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=15792 tn=3 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:41.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:41.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:41.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:41.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:41.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:41.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:41.474 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:41.474 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:41.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:41.521 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:41.521 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:41.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:41.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:41.548 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 02:46:42.021 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 02:46:42.494 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 02:46:42.966 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 02:46:43.439 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 02:46:43.913 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 02:46:44.386 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 02:46:44.859 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 02:46:45.332 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 02:46:45.804 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 02:46:45.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:45.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:45.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:45.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:45.886 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:45.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:45.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:45.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:45.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:45.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:45.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:45.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:45.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:45.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:45.953 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:45.953 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:45.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:45.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:46.275 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 02:46:46.749 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 02:46:47.222 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 02:46:47.695 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 02:46:48.167 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 02:46:48.640 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 02:46:49.113 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 02:46:49.585 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 02:46:50.057 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 02:46:50.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:50.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:50.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:50.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:50.163 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:50.164 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=17671 tn=1 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:50.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:50.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:50.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:50.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:50.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:50.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:50.184 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:50.184 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:50.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:50.234 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:50.234 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:50.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:50.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:50.531 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 02:46:51.004 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 02:46:51.476 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 02:46:51.948 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 02:46:52.421 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 02:46:52.893 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 02:46:53.365 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 02:46:53.838 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 02:46:54.310 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 02:46:54.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:54.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:54.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:54.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:54.436 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:54.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:54.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:54.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:46:54.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:54.456 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:46:54.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:46:54.456 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:46:54.456 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:46:54.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:54.505 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:46:54.505 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:46:54.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:54.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:54.781 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 02:46:55.254 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 02:46:55.727 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 02:46:56.199 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 02:46:56.670 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 02:46:57.143 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 02:46:57.615 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 02:46:58.088 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 02:46:58.561 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 02:46:58.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:46:58.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:46:58.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:46:58.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:46:58.702 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:46:58.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:46:58.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:46:58.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:46:58.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:46:58.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:46:58.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:46:58.716 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:46:58.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:46:58.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:46:58.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:46:58.717 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:46:58.717 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19518 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:58.717 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19518 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:58.717 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19518 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:58.717 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19518 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:58.717 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19518 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:46:58.717 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=19518 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:03.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:03.720 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:47:03.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:03.720 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:03.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:03.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:03.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:03.731 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:03.731 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:03.731 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:03.731 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:47:03.737 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:47:03.738 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:47:03.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:03.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:03.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:03.739 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:47:03.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:03.739 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:47:03.742 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:47:03.743 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:47:03.743 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:03.743 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:03.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:03.744 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:47:03.744 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:03.744 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:47:03.747 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:47:03.747 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:47:03.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:03.748 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:03.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:03.748 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:47:03.749 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:03.749 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.752 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:47:03.752 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:47:03.752 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:47:03.753 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:47:03.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:03.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:03.755 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:03.755 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:47:03.755 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:47:03.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:03.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:08.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:08.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:47:08.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:08.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:08.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:08.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:08.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:08.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:08.772 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:08.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:08.772 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:47:08.775 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:47:08.775 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:47:08.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:08.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:08.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:08.776 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:47:08.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:08.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:47:08.778 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:47:08.778 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:47:08.778 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:08.778 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:08.778 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:08.778 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:47:08.778 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:08.778 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:47:08.780 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:47:08.780 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:47:08.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:08.780 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:08.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:08.781 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:47:08.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:08.781 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:47:08.784 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:47:08.784 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:47:08.784 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:08.789 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:47:09.266 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:47:09.307 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:47:09.309 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:47:09.311 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:47:09.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:09.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:09.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:09.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:09.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:09.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:09.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:09.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:09.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:09.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:09.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:09.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:09.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:09.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:09.737 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:47:09.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:09.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:09.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:09.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:10.209 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:47:10.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:10.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:10.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:10.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:10.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:10.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:10.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:10.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:10.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:10.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:10.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:10.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:10.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:10.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:10.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:10.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:10.682 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:47:10.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:10.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:10.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:10.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:11.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:47:11.628 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:47:11.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:11.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:11.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:11.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:11.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:11.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:11.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:11.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:11.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:11.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:11.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:11.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:11.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:11.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:11.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:11.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:11.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:11.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:11.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:11.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:11.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:12.100 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:47:12.571 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:47:12.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:12.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:12.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:12.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:13.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:13.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:13.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:13.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:13.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:13.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:13.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:13.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:13.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:13.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:13.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:13.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:13.041 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:47:13.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:13.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:13.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:13.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:13.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:13.512 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:47:13.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:13.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:13.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:13.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:13.983 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:47:14.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:14.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:14.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:14.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:14.456 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:47:14.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:14.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:14.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:14.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:14.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:14.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:14.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:14.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:14.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:14.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:14.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:14.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:14.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:14.929 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:47:15.402 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:47:15.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:15.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:15.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:15.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:15.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:15.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:15.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:15.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:15.543 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:15.543 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:15.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:15.590 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:15.591 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:47:15.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:15.873 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:47:16.346 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:47:16.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:16.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:16.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:16.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:16.547 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:16.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:16.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:16.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:16.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:16.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:16.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:16.571 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:16.571 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:16.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:16.617 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:16.617 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:47:16.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:16.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:16.819 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:47:17.292 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:47:17.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:17.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:17.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:17.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:17.567 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:17.585 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:17.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:17.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:17.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:17.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:17.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:17.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:17.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:17.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:17.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:17.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:17.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:17.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:17.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:17.765 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:47:18.237 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:47:18.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:18.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:18.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:18.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:18.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:18.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:18.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:18.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:18.614 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:18.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:18.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:18.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:18.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:18.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:18.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:18.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:18.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:18.707 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:47:19.179 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:47:19.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:19.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:19.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:19.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:19.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:19.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:19.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:19.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:19.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:19.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:19.634 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:19.634 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:19.651 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:47:19.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:19.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:19.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:19.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:19.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:19.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:20.124 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:47:20.596 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:47:20.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:20.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:20.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:20.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:21.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:21.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:21.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:21.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:21.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:21.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:21.019 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:21.019 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:21.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:21.069 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:47:21.072 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:21.072 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:21.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:21.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:21.542 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:47:22.014 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:47:22.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:22.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:22.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:22.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:22.445 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:22.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:22.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:22.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:22.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:22.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:22.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:22.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:22.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:22.487 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:47:22.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:22.514 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:22.514 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:22.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:22.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:22.956 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:47:23.430 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:47:23.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:23.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:23.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:23.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:23.470 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:23.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:23.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:23.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:23.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:23.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:23.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:23.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:23.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:23.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:23.538 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:23.539 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:23.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:23.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:23.903 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:47:24.376 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:47:24.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:24.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:24.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:24.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:24.532 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:24.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:24.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:24.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:24.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:24.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:24.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:24.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:24.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:24.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:24.615 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:24.615 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:24.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:24.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:24.848 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:47:25.319 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:47:25.791 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:47:25.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:25.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:25.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:25.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:25.969 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:25.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:25.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:25.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:25.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:25.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:25.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:25.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:25.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:26.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:26.038 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:26.038 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:26.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:26.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:26.264 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:47:26.737 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:47:27.210 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:47:27.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:27.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:27.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:27.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:27.404 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:27.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:27.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:27.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:27.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:27.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:27.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:27.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:27.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:27.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:27.473 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:27.473 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:27.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:27.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:27.683 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:47:28.156 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:47:28.627 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:47:28.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:28.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:28.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:28.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:28.843 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:28.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:28.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:28.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:28.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:28.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:28.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:28.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:28.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:28.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:28.913 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:28.913 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:28.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:28.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:29.099 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:47:29.570 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:47:29.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:29.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:29.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:29.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:29.962 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:29.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:29.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:29.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:29.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:29.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:29.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:29.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:29.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:30.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:30.043 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:47:30.046 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:30.046 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:30.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:30.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:30.516 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:47:30.989 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:47:31.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:31.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:31.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:31.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:31.400 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:31.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:31.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:31.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:31.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:31.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:31.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:31.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:31.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:31.461 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:47:31.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:31.469 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:31.469 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:31.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:31.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:31.934 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:47:32.406 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:47:32.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:32.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:32.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:32.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:32.837 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:32.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:32.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:32.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:32.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:32.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:32.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:32.848 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:32.848 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:32.879 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:47:32.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:32.901 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:32.901 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:47:32.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:32.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:33.352 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:47:33.824 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:47:34.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:34.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:34.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:34.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:34.274 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:34.282 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:34.282 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:47:34.282 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:47:34.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:39.290 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:47:39.290 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:47:39.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:39.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:39.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:39.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:39.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:47:39.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:39.303 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:39.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:47:39.303 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:47:39.309 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:47:39.309 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:47:39.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:39.310 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:39.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:47:39.310 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:47:39.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:47:39.311 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:47:39.313 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:47:39.313 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:47:39.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:39.313 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:39.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:47:39.314 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:47:39.314 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:47:39.314 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:47:39.316 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:47:39.316 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:47:39.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:39.316 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:47:39.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:47:39.316 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:47:39.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:47:39.316 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:47:39.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:47:39.320 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:47:39.320 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:47:39.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:47:39.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:47:39.325 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:47:39.803 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:47:39.846 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:47:39.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:39.850 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:47:39.853 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:47:39.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:39.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:39.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:39.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:39.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:39.886 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:39.887 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:39.887 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:39.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:39.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:39.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:39.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:39.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:40.276 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:47:40.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:40.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:40.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:40.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:40.747 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:47:41.220 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:47:41.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:41.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:41.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:41.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:41.693 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:47:42.165 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:47:42.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:42.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:42.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:42.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:42.639 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:47:42.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:43.112 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:47:43.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:43.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:43.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:43.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:43.583 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:47:43.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:43.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:43.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:43.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:43.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:43.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:43.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:43.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:43.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:43.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:43.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:43.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:43.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:43.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:43.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:44.056 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:47:44.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:47:44.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:47:44.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:47:44.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:47:44.529 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:47:45.001 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:47:45.472 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:47:45.946 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:47:46.418 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:47:46.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:46.889 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:47:47.363 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:47:47.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:47.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:47.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:47.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:47.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:47.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:47.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:47.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:47.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:47.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:47.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:47.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:47.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:47.581 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:47.581 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:47.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:47.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:47.835 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:47:48.308 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:47:48.782 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:47:49.256 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:47:49.730 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:47:50.204 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:47:50.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:50.677 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:47:51.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:51.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:51.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:51.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:51.132 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:51.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:51.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:51.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:51.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:51.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:51.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:51.149 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:47:51.150 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:47:51.150 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:47:51.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:51.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:51.622 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:47:52.095 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:47:52.568 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:47:53.041 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:47:53.514 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:47:53.986 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:47:54.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:54.459 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:47:54.932 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:47:54.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:54.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:54.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:54.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:54.990 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:47:55.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:55.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:55.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:55.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:55.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:55.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:55.011 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:55.011 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:55.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:55.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:55.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:55.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:55.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:55.404 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:47:55.875 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:47:56.349 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:47:56.821 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:47:57.293 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:47:57.764 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:47:58.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:58.238 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:47:58.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:47:58.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:58.674 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:47:58.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:47:58.674 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=4177 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:47:58.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:47:58.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:58.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:58.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:58.675 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:47:58.675 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:47:58.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:47:58.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:47:58.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:47:58.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:58.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:47:58.710 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:47:59.182 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:47:59.653 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:48:00.127 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:48:00.599 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:48:01.072 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:48:01.544 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:48:01.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:01.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:01.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:01.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:01.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:01.981 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=4891 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:02.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:02.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:02.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:02.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:02.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:02.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:02.003 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:02.003 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:02.017 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:48:02.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:02.049 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:02.049 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:02.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:02.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:02.489 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:48:02.960 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:48:03.434 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:48:03.907 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:48:04.381 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:48:04.853 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:48:05.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:05.326 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:48:05.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:05.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:05.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:05.719 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:05.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:05.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:05.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:05.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:05.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:05.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:05.746 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:05.746 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:05.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:05.798 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:48:06.271 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:48:06.744 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:48:07.217 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:48:07.690 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:48:08.163 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:48:08.636 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:48:08.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:09.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:09.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:09.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:09.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:09.030 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:09.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:09.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:09.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:09.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:09.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:48:09.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:48:09.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:48:09.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:48:09.045 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:48:09.045 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:48:09.045 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:48:14.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:48:14.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:48:14.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:48:14.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:48:14.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:48:14.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:48:14.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:48:14.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:48:14.060 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:14.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:48:14.060 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:48:14.063 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:48:14.063 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:48:14.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:48:14.064 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:14.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:48:14.064 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:48:14.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:48:14.064 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:48:14.066 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:48:14.066 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:48:14.067 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:48:14.067 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:14.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:48:14.067 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:48:14.067 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:48:14.067 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:48:14.069 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:48:14.069 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:48:14.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:48:14.069 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:48:14.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:48:14.069 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:48:14.069 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:48:14.069 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.071 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:48:14.071 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:48:14.071 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:48:14.072 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:48:14.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:48:14.076 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:48:14.554 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:48:14.589 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:48:14.591 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:48:14.592 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:48:14.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:14.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:14.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:14.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:14.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:14.618 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:14.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:14.618 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:14.618 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:14.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:14.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:14.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:14.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:14.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:15.026 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:48:15.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:15.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:15.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:15.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:15.498 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:48:15.972 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:48:16.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:16.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:16.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:16.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:16.444 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:48:16.917 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:48:17.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:17.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:17.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:17.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:17.388 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:48:17.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:17.861 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:48:18.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:18.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:18.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:18.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:18.334 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:48:18.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:18.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:18.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:18.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:18.408 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=936 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:18.408 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=936 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:18.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:18.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:18.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:18.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:18.409 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:18.409 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:18.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:18.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:18.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:18.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:18.808 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:48:19.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:48:19.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:48:19.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:48:19.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:48:19.280 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:48:19.752 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:48:20.223 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:48:20.697 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:48:21.169 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:48:21.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:21.642 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:48:22.113 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:48:22.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:22.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:22.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:22.261 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1768 tn=3 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:22.261 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1768 tn=4 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:22.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:22.261 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1768 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:22.261 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1768 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:22.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.261 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=1768 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:22.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:22.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:22.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:22.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:22.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:22.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:22.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:22.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:22.587 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:48:23.059 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:48:23.533 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:48:24.005 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:48:24.478 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:48:24.951 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:48:25.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:25.424 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:48:25.896 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:48:26.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:26.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:26.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:26.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:26.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:26.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:26.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:26.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:26.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:26.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:26.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:26.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:26.367 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:48:26.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:26.841 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:48:27.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:27.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:27.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:27.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:27.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:27.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:27.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:27.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:27.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:27.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:27.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:27.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:27.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:27.153 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:27.153 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:27.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:27.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:27.311 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:48:27.783 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:48:28.257 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:48:28.730 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:48:29.203 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:48:29.677 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:48:30.149 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:48:30.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:30.622 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:48:30.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:30.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:30.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:30.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:30.695 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:30.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:30.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:30.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:30.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:30.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:30.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:30.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:30.713 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:30.713 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:30.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:30.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:31.096 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:48:31.569 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:48:32.043 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:48:32.515 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:48:32.989 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:48:33.461 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:48:33.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:33.933 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:48:34.407 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:48:34.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:34.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:34.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:34.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:34.554 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:34.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:34.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:34.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:34.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:34.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:34.556 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:34.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:34.589 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:34.589 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:34.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:34.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:34.880 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:48:35.351 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:48:35.824 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:48:36.298 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:48:36.770 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:48:37.245 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:48:37.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:37.719 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:48:38.193 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:48:38.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:38.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:38.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:38.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:38.416 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:38.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:38.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:38.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:38.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:38.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:38.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:38.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:38.430 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:38.430 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:48:38.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:38.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:38.666 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:48:38.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:39.139 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:48:39.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:39.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:39.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:39.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:39.382 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:39.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:39.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:39.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:39.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:39.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:39.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:39.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:39.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:39.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:39.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:39.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:39.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:39.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:39.611 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:48:40.082 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:48:40.558 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:48:41.030 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:48:41.501 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:48:41.974 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:48:42.447 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:48:42.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:42.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:42.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:42.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:42.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:42.887 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=6217 tn=5 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:42.887 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=6217 tn=6 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:48:42.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:42.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:42.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:42.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:42.888 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:42.888 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:42.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:42.919 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:48:42.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:42.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:42.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:42.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:43.392 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:48:43.865 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:48:44.337 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:48:44.808 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:48:45.281 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:48:45.754 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:48:45.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:46.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:46.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:46.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:46.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:46.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:46.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:46.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:46.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:46.196 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:46.196 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:46.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:46.226 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:48:46.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:46.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:46.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:46.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:46.699 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:48:47.172 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:48:47.644 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:48:48.115 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:48:48.589 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:48:49.061 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:48:49.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:49.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:49.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:49.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:49.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:49.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:49.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:49.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:49.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:49.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:49.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:49.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:49.533 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:48:49.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:49.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:49.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:49.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:49.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:50.004 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:48:50.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:50.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:50.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:50.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:50.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:50.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:50.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:50.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:50.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:50.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:50.454 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:50.454 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:50.474 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:48:50.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:50.500 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:50.501 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:50.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:50.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:50.946 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:48:51.420 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:48:51.891 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:48:52.364 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:48:52.838 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:48:53.309 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:48:53.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:53.781 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:48:54.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:54.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:54.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:54.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:54.173 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:54.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:54.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:54.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:54.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:54.174 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:54.174 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:54.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:54.201 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:54.201 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:54.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:54.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:54.255 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:48:54.727 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:48:55.200 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:48:55.673 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:48:56.145 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:48:56.619 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:48:57.092 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:48:57.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:57.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:48:57.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:57.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:48:57.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:48:57.487 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:48:57.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:48:57.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:57.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:48:57.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:48:57.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:48:57.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:48:57.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:48:57.514 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:48:57.514 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:48:57.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:57.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:48:57.564 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:48:58.037 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:48:58.510 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:48:58.982 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:48:59.456 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:48:59.928 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:49:00.400 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:49:00.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:00.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:00.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:00.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:00.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:00.793 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:49:00.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:49:00.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:00.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:00.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:00.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:49:00.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:49:00.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:49:00.820 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:49:00.820 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:49:00.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:00.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:00.874 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:49:01.346 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:49:01.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:01.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:01.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:01.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:01.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:01.741 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:49:01.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:01.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:01.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:01.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:01.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:01.759 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:01.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:01.759 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:01.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:01.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:01.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:01.760 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10291 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:01.760 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10291 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:01.760 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10291 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:01.760 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10291 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:01.760 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10291 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:01.760 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10291 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:01.760 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10291 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:06.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:06.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:06.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:06.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:06.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:06.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:06.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:06.771 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:06.771 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:06.771 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:06.771 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:06.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:06.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:06.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:06.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:06.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:06.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:06.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:06.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:06.781 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:06.781 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:06.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:06.781 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:06.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:06.782 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:06.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:06.782 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:06.785 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:06.786 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:06.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:06.786 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:06.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:06.786 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:06.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:06.786 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.792 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:49:06.792 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:49:06.793 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:06.793 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:06.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:06.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:06.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:06.797 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:07.276 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:07.316 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:07.318 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:07.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:07.320 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:07.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:07.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:07.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:49:07.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:07.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:07.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:07.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:49:07.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:49:07.748 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:07.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:07.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:07.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:07.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:08.219 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:08.690 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:08.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:08.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:08.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:08.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:09.161 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:09.632 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:09.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:09.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:09.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:09.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:10.103 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:10.573 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:49:10.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:10.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:10.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:10.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:11.044 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:49:11.515 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:49:11.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:11.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:11.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:11.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:11.986 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:49:12.456 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:49:12.927 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:49:13.398 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:49:13.868 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:49:14.339 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:49:14.809 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:49:15.281 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:49:15.751 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:49:16.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:16.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:16.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:16.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:16.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:16.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:16.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:16.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:16.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:16.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:16.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:16.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:16.115 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:16.115 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:16.115 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:16.115 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2019 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:21.119 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:21.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:21.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:21.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:21.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:21.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:21.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:21.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:21.130 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:21.130 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:21.130 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:21.132 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:21.132 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:21.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:21.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:21.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:21.133 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:21.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:21.133 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:21.134 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:21.134 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:21.134 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:21.134 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:21.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:21.134 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:21.134 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:21.134 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:21.136 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:21.136 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:21.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:21.136 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:21.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:21.136 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:21.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:21.136 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:49:21.138 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:49:21.138 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:21.138 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:21.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:21.143 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:21.622 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:21.659 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:21.660 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:21.662 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:21.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:21.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:21.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:21.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:49:21.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:21.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:21.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:21.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:49:21.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:49:22.094 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:22.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:22.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:22.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:22.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:22.564 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:23.035 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:23.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:23.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:23.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:23.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:23.506 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:23.976 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:24.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:24.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:24.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:24.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:24.448 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:24.918 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:49:25.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:25.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:25.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:25.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:25.389 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:49:25.860 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:49:26.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:26.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:26.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:26.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:26.330 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:49:26.801 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:49:27.273 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:49:27.743 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:49:28.213 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:49:28.685 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:49:29.156 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:49:29.626 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:49:30.097 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:49:30.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:30.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:30.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:30.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:30.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:30.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:30.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:30.472 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:30.472 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:30.472 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:30.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:30.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:30.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:30.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2021 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:30.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2021 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:30.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2021 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:30.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2021 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:30.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2021 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:30.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2021 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:30.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2021 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:49:35.474 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:35.474 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:35.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:35.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:35.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:35.475 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:35.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:35.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:35.478 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:35.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:35.478 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:35.479 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:35.479 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:35.479 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:35.479 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:35.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:35.479 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:35.480 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:35.480 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:35.480 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:35.480 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:35.480 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:35.480 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:35.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:35.480 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:35.480 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:35.480 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:35.481 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:35.482 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:35.482 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:35.482 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:35.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:35.482 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:35.482 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:35.482 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:35.483 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:35.483 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:35.483 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:35.483 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:49:35.484 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:49:35.484 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:35.484 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:35.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:35.489 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:35.967 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:36.007 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:36.010 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:36.012 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:36.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:36.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:36.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:36.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:49:36.439 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:36.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:36.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:36.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:36.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:36.915 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:37.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:37.018 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:37.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:37.019 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:49:37.019 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:49:37.387 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:37.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:37.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:37.488 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:37.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:37.858 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:38.329 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:38.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:38.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:38.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:38.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:38.799 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:39.270 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:49:39.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:39.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:39.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:39.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:39.741 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:49:40.212 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:49:40.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:40.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:40.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:40.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:40.683 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:49:41.153 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:49:41.624 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:49:42.095 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:49:42.565 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:49:43.037 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:49:43.507 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:49:43.978 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:49:44.449 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:49:44.922 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:49:45.394 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:49:45.866 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:49:46.337 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:49:46.811 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:49:47.283 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:49:47.755 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:49:48.229 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:49:48.701 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:49:48.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:48.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:48.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:48.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:48.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:48.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:48.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:48.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:48.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:48.820 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:48.820 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:49:48.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:48.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:53.827 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:49:53.827 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:49:53.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:53.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:53.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:53.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:53.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:49:53.830 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:53.830 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:53.831 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:49:53.831 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:49:53.833 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:49:53.833 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:49:53.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:53.834 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:53.834 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:49:53.834 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:49:53.834 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:49:53.834 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:49:53.836 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:49:53.836 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:49:53.836 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:53.836 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:53.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:49:53.836 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:49:53.836 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:49:53.836 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:49:53.838 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:49:53.838 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:49:53.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:53.838 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:49:53.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:49:53.838 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:49:53.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:49:53.838 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:49:53.840 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:49:53.840 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:49:53.840 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:49:53.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:49:53.845 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:49:54.319 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:49:54.359 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:54.360 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:49:54.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:49:54.361 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:49:54.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:49:54.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:49:54.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:49:54.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:49:54.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:49:54.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:49:54.363 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:49:54.363 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:49:54.790 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:49:54.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:54.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:54.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:54.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:55.262 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:49:55.409 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:55.733 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:49:55.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:55.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:55.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:55.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:55.934 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:56.207 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:49:56.448 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:56.678 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:49:56.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:56.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:56.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:56.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:57.151 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:49:57.621 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:49:57.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:57.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:57.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:57.847 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:58.092 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:49:58.471 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:58.566 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:49:58.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:49:58.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:49:58.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:49:58.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:49:58.999 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:59.038 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:49:59.510 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:49:59.522 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:49:59.981 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:50:00.039 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:00.455 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:50:00.927 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:50:01.399 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:50:01.870 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:50:02.045 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:02.343 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:50:02.816 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:50:03.288 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:50:03.759 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:50:04.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:04.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:04.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:04.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:04.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:04.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:04.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:04.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:04.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:04.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:04.092 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:04.092 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:04.092 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:09.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:09.099 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:09.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:09.099 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:09.099 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:09.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:09.108 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:09.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:09.109 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:09.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:09.110 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:09.114 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:09.114 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:09.114 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:09.114 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:09.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:09.115 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:09.115 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:09.116 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:09.117 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:09.117 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:09.118 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:09.118 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:09.118 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:09.118 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:09.118 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:09.118 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:09.120 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:09.120 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:09.120 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:09.120 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:09.120 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:09.121 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:09.121 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:09.121 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:09.123 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:09.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:50:09.124 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:50:09.124 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:09.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:09.129 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:09.605 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:09.652 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:09.654 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:09.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:09.655 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:09.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:09.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:09.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:09.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:09.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:09.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:09.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:09.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:09.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:09.708 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:09.708 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:09.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:09.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:09.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:09.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:09.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:09.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:09.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:09.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:09.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:09.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:09.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:09.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:09.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:09.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:09.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:09.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:09.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:09.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:09.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:09.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.049 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.049 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.049 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.072 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:10.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:10.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:10.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:10.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:10.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.543 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:10.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.565 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.637 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:10.637 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:50:10.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.646 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:10.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.660 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.660 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.683 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:10.683 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:50:10.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.690 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:10.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:10.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.800 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.800 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:10.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.875 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:10.875 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:50:10.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.887 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:10.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.905 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.905 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.914 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:10.914 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:50:10.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:10.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.932 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:10.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:10.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:10.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:10.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:10.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:10.947 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:10.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:10.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:10.963 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:10.963 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:10.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:10.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.011 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:11.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.078 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:11.079 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=425 tn=1 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:11.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:11.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:11.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:11.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:11.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:11.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:11.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:11.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:11.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:11.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:11.158 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:11.158 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:11.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.332 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:11.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:11.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:11.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:11.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:11.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:11.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:11.391 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:11.391 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:11.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.482 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:11.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.595 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:11.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:11.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:11.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:11.613 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:11.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:11.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:11.667 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:11.667 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:11.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:11.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.840 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:11.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:11.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:11.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:11.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:11.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:11.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:11.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:11.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:11.906 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:11.906 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:11.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:11.955 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:50:12.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:12.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:12.098 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:12.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:12.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:12.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:12.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:12.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:12.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:12.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:12.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:12.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:12.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:12.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:12.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:12.146 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:12.146 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:12.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:12.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:12.355 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:12.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:12.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:12.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:12.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:12.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:12.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:12.375 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:12.425 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:50:12.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:12.433 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:12.433 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:12.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:12.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:12.611 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:12.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:12.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:12.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:12.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.632 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:12.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:12.632 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:12.632 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:12.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:12.655 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:50:12.655 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:50:12.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:12.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:12.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:12.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:12.855 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:50:12.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:12.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:12.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:12.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:12.862 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:12.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:12.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:12.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:12.862 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:12.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:12.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:17.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:17.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:17.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:17.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:17.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:17.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:17.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:17.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:17.877 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:17.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:17.877 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:17.879 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:17.879 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:17.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:17.880 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:17.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:17.880 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:17.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:17.881 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:17.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:17.882 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:17.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:17.882 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:17.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:17.882 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:17.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:17.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:17.885 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:17.885 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:17.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:17.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:17.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:17.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:17.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:17.885 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:17.888 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:17.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:17.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:50:17.889 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:50:17.889 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:17.889 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:17.894 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:18.371 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:18.413 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:18.415 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:18.417 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:18.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:18.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:18.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:18.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:18.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:18.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:18.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:18.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:18.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:18.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 02:50:18.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:18.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:18.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:18.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:18.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:18.843 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:18.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:18.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:18.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:18.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:19.315 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:19.788 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:19.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:19.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:19.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:19.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:20.261 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:20.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:20.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:20.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:20.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:20.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:20.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:20.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:20.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:20.538 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:20.538 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:20.538 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:20.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:20.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:25.544 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:25.544 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:25.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:25.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:25.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:25.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:25.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:25.552 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:25.553 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.553 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:25.553 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:25.557 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:25.557 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:25.558 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:25.558 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:25.559 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.559 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:25.559 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:25.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:25.562 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:25.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:25.563 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:25.563 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.564 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:25.564 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:25.565 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:25.566 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:25.566 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:25.566 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:25.566 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:25.566 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.566 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:25.566 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:25.569 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:50:25.570 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:50:25.570 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:25.570 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:25.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:25.572 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:25.572 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:25.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:30.578 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:30.578 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:30.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:30.578 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:30.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:30.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:30.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:30.588 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:30.588 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:30.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:30.589 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:30.592 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:30.593 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:30.593 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:30.593 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:30.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:30.594 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:30.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:30.594 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:30.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:30.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:30.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:30.596 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:30.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:30.597 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:30.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:30.597 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:30.598 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:30.598 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:30.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:30.598 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:30.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:30.599 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:30.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:30.599 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:30.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:50:30.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:50:30.602 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:30.602 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:30.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:30.607 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:31.082 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:31.127 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:31.129 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:31.131 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:31.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:31.554 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:31.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:31.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:31.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:31.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:32.024 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:32.491 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:32.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:32.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:32.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:32.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:32.961 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:33.433 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:50:33.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:33.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:33.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:33.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:33.908 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:50:34.380 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:50:34.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:34.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:34.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:34.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:34.855 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:50:35.327 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:50:35.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:35.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:35.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:35.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:35.803 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:50:36.275 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:50:36.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:36.623 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:36.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:36.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:36.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:36.625 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:36.625 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:36.625 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:36.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:36.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:36.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:36.626 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1302 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:36.626 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1302 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:36.626 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1302 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:36.626 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1302 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:36.626 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1302 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:36.626 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1302 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:36.626 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1302 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:41.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:41.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:41.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:41.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:41.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:41.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:41.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:41.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:41.638 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:41.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:41.638 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:41.642 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:41.642 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:41.643 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:41.643 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:41.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:41.643 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:41.644 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:41.644 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:41.645 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:41.646 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:41.646 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:41.646 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:41.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:41.646 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:41.646 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:41.646 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:41.648 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:41.648 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:41.648 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:41.648 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:41.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:41.648 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:41.648 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:41.648 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.652 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:50:41.652 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:50:41.652 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:41.653 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.653 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:41.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:41.657 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:42.135 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:42.174 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:42.175 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:42.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:42.176 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:42.607 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:42.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:42.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:42.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:42.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:43.082 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:43.554 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:43.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:43.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:43.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:43.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:44.028 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:50:44.500 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:50:44.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:44.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:44.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:44.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:44.972 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:50:45.446 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:50:45.660 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:45.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:45.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:45.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:45.918 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:50:46.390 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:50:46.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:46.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:46.662 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:46.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:46.864 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:50:47.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:47.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:47.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:47.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:47.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:47.191 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:47.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:47.191 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:47.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:47.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:47.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:47.192 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1195 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:47.192 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1195 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:47.192 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1195 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:47.192 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1195 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:47.193 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1195 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:47.193 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1195 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:50:52.193 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:52.194 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:52.194 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:52.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:52.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:52.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:52.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:52.203 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:52.203 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:52.203 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:52.204 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:52.206 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:52.207 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:52.207 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:52.207 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:52.207 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:52.208 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:52.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:52.208 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:52.210 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:52.210 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:52.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:52.210 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:52.210 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:52.210 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:52.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:52.210 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:52.212 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:52.212 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:52.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:52.212 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:52.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:52.212 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:52.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:52.212 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.215 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:50:52.215 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:50:52.215 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:52.216 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:52.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:52.217 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:52.217 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:52.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:57.225 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:50:57.225 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:50:57.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:57.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:57.225 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:57.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:57.234 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:50:57.235 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:57.235 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:57.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:50:57.236 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:50:57.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:50:57.241 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:50:57.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:57.241 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:57.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:50:57.242 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:50:57.242 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:50:57.242 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:50:57.244 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:50:57.245 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:50:57.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:57.245 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:57.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:50:57.245 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:50:57.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:50:57.246 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:50:57.247 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:50:57.247 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:50:57.247 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:57.247 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:50:57.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:50:57.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:50:57.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:50:57.248 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:50:57.251 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:50:57.251 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:50:57.251 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:50:57.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:50:57.256 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:50:57.730 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:50:57.775 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:50:57.776 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:50:57.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:50:57.778 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:50:57.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:50:57.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:50:57.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:50:58.202 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:50:58.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:58.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:58.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:58.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:58.677 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:50:58.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:50:58.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:50:58.783 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:50:58.783 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:50:58.783 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:50:59.149 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:50:59.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:50:59.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:50:59.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:50:59.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:50:59.620 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:51:00.090 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:51:00.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:00.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:00.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:00.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:00.558 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:51:01.027 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:51:01.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:01.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:01.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:01.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:01.499 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:51:01.970 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:51:02.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:02.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:02.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:02.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:02.442 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:51:02.911 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:51:03.382 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:51:03.853 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:51:04.324 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:51:04.795 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:51:05.265 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:51:05.736 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:51:06.207 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:51:06.677 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:51:07.148 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:51:07.618 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:51:08.089 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:51:08.561 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:51:09.034 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:51:09.506 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:51:09.978 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:51:10.448 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:51:10.912 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:51:11.375 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:51:11.838 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:51:12.301 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:51:12.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:12.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:12.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:12.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:12.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:12.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:12.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:12.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:12.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:12.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:12.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:12.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:12.634 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:17.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:17.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:17.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:17.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:17.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:17.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:17.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:17.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:17.652 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:17.652 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:17.652 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:17.659 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:17.659 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:17.660 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:17.660 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:17.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:17.660 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:17.661 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:17.661 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:17.664 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:17.664 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:17.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:17.665 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:17.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:17.665 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:17.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:17.665 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:17.669 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:17.670 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:17.670 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:17.670 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:17.670 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:17.670 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:17.670 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:17.670 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:17.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:51:17.676 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:51:17.676 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:17.676 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:17.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:17.681 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:18.158 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:18.208 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:18.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:18.212 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:18.214 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:18.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:18.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:18.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:51:18.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:18.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:18.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:18.249 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:51:18.249 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:51:18.296 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:18.300 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:18.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:18.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:18.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:18.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:18.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:18.628 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:18.678 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:18.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:18.679 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:18.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:19.102 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:19.574 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:51:19.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:19.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:19.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:19.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:20.045 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:51:20.516 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:51:20.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:20.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:20.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:20.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:20.988 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:51:21.462 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:51:21.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:21.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:21.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:21.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:21.934 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:51:22.408 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:51:22.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:22.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:22.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:22.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:22.880 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:51:23.353 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:51:23.826 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:51:24.299 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:51:24.771 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:51:25.242 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:51:25.716 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:51:26.188 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:51:26.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:26.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:26.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:26.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:26.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:26.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:26.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:26.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:26.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:26.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:26.332 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:26.332 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:26.332 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:26.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:26.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:26.332 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1869 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:26.332 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:26.332 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:26.332 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:26.332 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:26.332 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:31.340 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:31.340 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:31.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:31.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:31.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:31.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:31.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:31.350 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:31.350 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:31.351 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:31.351 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:31.354 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:31.354 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:31.355 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:31.355 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:31.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:31.355 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:31.355 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:31.355 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:31.359 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:31.359 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:31.359 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:31.359 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:31.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:31.359 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:31.359 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:31.359 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:31.362 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:31.362 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:31.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:31.362 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:31.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:31.362 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:31.363 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:31.363 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:51:31.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:51:31.366 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:31.367 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:31.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:31.371 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:31.849 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:31.888 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:31.889 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:31.891 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:31.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:31.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:31.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:31.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:51:31.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:31.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:31.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:31.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:51:31.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:51:31.940 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:31.944 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:31.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:31.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:31.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:31.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:31.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:32.320 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:32.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:32.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:32.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:32.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:32.792 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:32.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:32.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:32.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:32.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:32.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:32.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:32.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:32.821 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:32.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:32.821 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:32.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:32.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:32.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=313 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=313 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=313 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=313 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:32.821 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=314 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:37.827 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:37.827 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:37.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:37.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:37.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:37.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:37.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:37.830 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:37.830 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:37.831 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:37.831 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:37.832 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:37.832 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:37.832 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:37.832 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:37.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:37.832 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:37.833 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:37.833 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:37.833 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:37.834 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:37.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:37.834 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:37.834 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:37.834 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:37.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:37.834 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:37.836 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:37.836 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:37.836 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:37.836 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:37.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:37.836 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:37.836 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:37.836 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.839 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:51:37.839 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:51:37.839 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:37.840 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:37.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:37.844 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:38.319 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:38.364 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:38.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:38.368 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:38.372 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:38.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:38.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:38.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:51:38.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:38.407 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:38.407 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:38.408 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:51:38.408 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:51:38.457 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:38.461 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:38.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:38.477 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:51:38.477 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:51:38.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:38.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:38.790 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:38.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:38.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:38.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:38.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:39.263 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:39.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:39.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:39.462 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:51:39.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:39.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:39.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:39.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:39.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:39.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:39.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:39.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:39.468 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:39.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:39.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:44.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:44.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:44.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:44.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:44.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:44.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:44.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:44.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:44.483 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:44.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:44.483 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:44.488 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:44.488 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:44.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:44.488 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:44.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:44.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:44.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:44.489 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:44.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:44.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:44.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:44.493 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:44.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:44.494 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:44.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:44.494 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:44.497 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:44.497 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:44.498 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:44.498 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:44.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:44.498 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:44.498 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:44.498 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:44.503 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:44.503 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:44.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:51:44.504 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:51:44.504 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:44.504 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:44.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:44.509 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:44.986 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:45.037 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:45.039 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:45.041 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:45.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:45.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:45.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:45.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:51:45.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:45.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:45.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:45.072 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:51:45.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:51:45.076 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:45.078 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:45.084 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:51:45.084 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:51:45.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:45.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:45.457 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:45.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:45.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:45.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:45.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:45.930 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:46.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:46.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:46.129 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:51:46.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:46.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:46.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:46.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:46.134 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:46.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:46.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:46.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:46.134 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:46.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:46.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:51.145 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:51.145 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:51.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:51.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:51.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:51.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:51.154 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:51.155 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:51.155 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:51.156 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:51.156 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:51.160 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:51.160 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:51.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:51.161 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:51.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:51.161 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:51.162 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:51.162 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:51.163 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:51.164 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:51.164 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:51.164 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:51.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:51.164 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:51.164 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:51.164 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:51.166 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:51.166 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:51.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:51.166 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:51.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:51.167 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:51.167 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:51.167 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:51:51.170 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:51:51.170 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:51.170 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:51.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:51.175 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:51.651 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:51.696 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:51.697 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:51.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:51.698 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:51.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:51.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:51.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:51:51.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:51.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:51.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:51.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:51:51.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:51:51.742 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:51.745 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:51.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:51.753 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:51:51.753 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:51:51.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:51.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:52.121 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:52.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:52.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:52.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:52.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:52.592 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:52.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:52.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:52.789 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:51:52.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:52.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:52.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:52.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:52.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:52.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:52.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:52.797 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:51:52.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (TRX2@172.18.128.20:5700/2) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:52.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:52.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:52.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:51:57.802 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:51:57.803 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:51:57.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:57.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:57.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:57.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:57.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:51:57.810 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:57.810 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:57.811 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:51:57.811 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:51:57.814 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:51:57.814 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:51:57.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:57.815 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:57.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:51:57.815 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:51:57.815 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:51:57.815 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:51:57.817 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:51:57.818 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:51:57.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:57.818 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:57.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:51:57.819 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:51:57.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:51:57.819 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:51:57.820 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:51:57.820 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:51:57.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:57.820 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:51:57.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:51:57.821 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:51:57.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:51:57.821 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:51:57.823 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:51:57.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:51:57.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:51:57.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:51:57.823 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:51:57.824 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:51:57.824 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:51:57.824 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:51:57.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:51:57.829 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:51:58.305 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:51:58.347 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:58.349 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:58.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:58.350 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:51:58.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:51:58.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:51:58.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:51:58.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:58.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:58.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:58.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:51:58.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:51:58.397 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:51:58.401 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:51:58.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:51:58.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:51:58.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:51:58.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:58.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:51:58.773 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:51:58.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:58.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:58.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:58.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:51:59.247 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:51:59.719 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:51:59.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:51:59.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:51:59.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:51:59.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:00.192 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:52:00.663 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:52:00.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:00.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:00.829 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:00.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:01.133 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:52:01.607 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:52:01.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:01.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:01.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:01.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:02.080 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:52:02.552 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:52:02.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:02.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:02.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:02.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:03.023 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:52:03.496 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:52:03.969 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:52:04.441 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:52:04.912 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:52:05.386 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:52:05.858 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:52:06.331 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:52:06.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:06.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:06.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:06.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:06.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:06.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:06.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:52:06.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:06.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:06.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:06.433 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:52:06.433 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:52:06.468 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:06.473 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:06.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:06.484 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:52:06.484 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:52:06.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:06.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:06.802 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:52:07.275 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:52:07.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:07.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:07.510 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:52:07.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:07.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:07.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:07.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:07.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:07.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:07.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:07.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:07.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:07.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:52:07.520 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:52:07.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2094 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (TRX1@172.18.128.20:5700/1) RX TRXD message (ver=1 fn=2096 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2094 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2094 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2094 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2094 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2095 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:07.522 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2096 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:12.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:12.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:52:12.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:12.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:12.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:12.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:12.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:12.534 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:12.535 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:12.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:12.535 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:52:12.541 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:52:12.541 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:52:12.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:12.542 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:12.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:12.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:52:12.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:12.543 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:52:12.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:52:12.546 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:52:12.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:12.546 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:12.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:12.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:52:12.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:12.547 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:52:12.548 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:52:12.548 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:52:12.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:12.549 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:12.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:12.549 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:52:12.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:12.549 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:52:12.551 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:52:12.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:52:12.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:52:12.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:52:12.551 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:52:12.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:52:12.552 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:52:12.552 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:52:12.552 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:12.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:12.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:12.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:12.557 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:52:13.032 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:52:13.077 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:13.079 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:13.080 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:52:13.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:13.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:13.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:13.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:52:13.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:13.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:13.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:13.110 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:52:13.110 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:52:13.124 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:13.127 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:13.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:13.135 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:52:13.135 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:52:13.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:13.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:13.503 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:52:13.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:13.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:13.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:13.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:13.971 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:52:14.171 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:14.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:14.171 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:52:14.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:14.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:14.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:14.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:14.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:14.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:14.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:14.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:14.176 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:14.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:52:14.176 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:52:19.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:19.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:52:19.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:19.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:19.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:19.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:19.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:19.192 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:19.192 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:19.193 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:19.193 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:52:19.197 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:52:19.197 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:52:19.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:19.197 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:19.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:19.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:52:19.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:19.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:52:19.202 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:52:19.202 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:52:19.203 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:19.203 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:19.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:19.203 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:52:19.203 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:19.203 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:52:19.207 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:52:19.207 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:52:19.207 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:19.207 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:19.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:19.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:52:19.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:19.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:52:19.212 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:52:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:52:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:52:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:52:19.212 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:52:19.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:52:19.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:52:19.213 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:52:19.213 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:52:19.213 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:19.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:19.218 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:52:19.695 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:52:19.742 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:19.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:19.745 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:19.746 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:52:19.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:19.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:19.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:52:19.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:19.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:19.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:19.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:52:19.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:52:19.787 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:19.790 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:19.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:19.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:19.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:19.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:19.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:20.166 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:52:20.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:20.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:20.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:20.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:20.638 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:52:21.110 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:52:21.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:21.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:21.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:21.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:21.583 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:52:22.056 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:52:22.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:22.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:22.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:22.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:22.528 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:52:23.002 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:52:23.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:23.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:23.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:23.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:23.474 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:52:23.947 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:52:24.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:24.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:24.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:24.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:24.420 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:52:24.893 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:52:25.365 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:52:25.836 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:52:26.310 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:52:26.782 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:52:27.254 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:52:27.728 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:52:27.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:27.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:27.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:27.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:27.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:27.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:27.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:52:27.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:27.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:27.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:27.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:52:27.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:52:27.861 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:27.865 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:27.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:27.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:27.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:27.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:27.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:28.199 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:52:28.671 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:52:29.143 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:52:29.614 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:52:30.088 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:52:30.560 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:52:31.035 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:52:31.509 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:52:31.981 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:52:32.453 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:52:32.927 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:52:33.399 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:52:33.871 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:52:34.345 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:52:34.817 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:52:35.289 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:52:35.760 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:52:35.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:35.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:35.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:35.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:35.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:35.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:35.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:52:35.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:35.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:35.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:35.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:52:35.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:52:35.943 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:35.948 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:35.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:35.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:35.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:35.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:35.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:36.234 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:52:36.706 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:52:37.178 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:52:37.648 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:52:38.119 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:52:38.590 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:52:39.061 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:52:39.534 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:52:40.007 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:52:40.479 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:52:40.950 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:52:41.421 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:52:41.894 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:52:42.367 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:52:42.839 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:52:43.313 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:52:43.785 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:52:43.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:43.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:43.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:43.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:43.982 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:43.982 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:43.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:52:43.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:43.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:43.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:43.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:52:43.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:52:44.020 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:44.024 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:44.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:44.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:44.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:44.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:44.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:44.257 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:52:44.728 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:52:45.199 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:52:45.672 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:52:46.145 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:52:46.617 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:52:47.088 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:52:47.559 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:52:48.032 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:52:48.505 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:52:48.977 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:52:49.448 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:52:49.922 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:52:50.394 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:52:50.866 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:52:51.337 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:52:51.811 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:52:52.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:52.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:52.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:52.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:52.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:52.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:52.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:52.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:52.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:52.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:52.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:52.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:52:52.057 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:52:52.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:52.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:52.057 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:52.057 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:52.057 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:52.057 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:52.057 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:52.057 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7094 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:52:57.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:52:57.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:52:57.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:57.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:57.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:57.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:57.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:52:57.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:57.070 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:57.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:52:57.071 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:52:57.074 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:52:57.074 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:52:57.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:57.075 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:57.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:52:57.076 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:52:57.076 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:52:57.076 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:52:57.078 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:52:57.078 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:52:57.079 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:57.079 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:57.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:52:57.079 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:52:57.079 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:52:57.079 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:52:57.081 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:52:57.081 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:52:57.081 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:57.081 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:52:57.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:52:57.081 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:52:57.082 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:52:57.082 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.085 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:52:57.085 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:52:57.085 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:52:57.086 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:52:57.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:52:57.090 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:52:57.565 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:52:57.614 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:57.617 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:57.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:57.619 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:52:57.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:52:57.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:52:57.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:52:57.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:57.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:52:57.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:52:57.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:52:57.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:52:57.658 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:52:57.661 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:52:57.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:52:57.668 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:52:57.668 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:52:57.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:57.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:52:58.037 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:52:58.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:58.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:58.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:58.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:58.509 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:52:58.982 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:52:59.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:52:59.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:52:59.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:52:59.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:52:59.455 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:52:59.928 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:53:00.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:00.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:00.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:00.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:00.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:00.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:00.155 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:53:00.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:00.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:00.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:00.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:00.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:00.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:00.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:00.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:00.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:00.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:00.161 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:05.172 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:05.172 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:05.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:05.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:05.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:05.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:05.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:05.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:05.182 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:05.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:05.183 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:05.189 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:05.189 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:05.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:05.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:05.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:05.190 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:05.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:05.190 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:05.195 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:05.195 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:05.195 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:05.195 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:05.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:05.196 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:05.196 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:05.196 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:05.200 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:05.200 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:05.200 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:05.200 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:05.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:05.200 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:05.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:05.201 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:05.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:53:05.207 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:53:05.207 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:05.207 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:05.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:05.212 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:05.688 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:05.750 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:05.752 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:05.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:05.754 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:05.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:05.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:05.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:53:05.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:05.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:05.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:05.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:53:05.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:53:05.826 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:05.829 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:05.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:05.841 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:53:05.841 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:53:05.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:05.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:06.153 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:53:06.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:06.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:06.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:06.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:06.624 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:53:06.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:06.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:06.822 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:53:06.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:06.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:06.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:06.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:06.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:06.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:06.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:06.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:06.827 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:06.827 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:06.827 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:11.833 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:11.833 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:11.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:11.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:11.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:11.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:11.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:11.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:11.842 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:11.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:11.843 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:11.847 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:11.847 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:11.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:11.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:11.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:11.849 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:11.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:11.849 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:11.852 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:11.852 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:11.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:11.853 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:11.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:11.854 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:11.854 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:11.855 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:11.857 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:11.857 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:11.857 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:11.857 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:11.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:11.857 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:11.858 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:11.858 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:11.862 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:53:11.863 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:53:11.863 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:11.863 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:11.868 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:12.343 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:12.391 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:12.393 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:12.395 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:12.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:12.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:12.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:12.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:53:12.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:12.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:12.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:12.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:53:12.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:53:12.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:12.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:12.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:12.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:12.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:12.815 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:53:12.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:12.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:12.867 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:12.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:13.287 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:53:13.758 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:53:13.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:13.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:13.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:13.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:14.231 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:53:14.704 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:53:14.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:14.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:14.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:14.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:15.178 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:53:15.650 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:53:15.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:15.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:15.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:15.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:16.123 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:53:16.596 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:53:16.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:16.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:16.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:16.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:17.069 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:53:17.541 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:53:18.015 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:53:18.488 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:53:18.960 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:53:19.431 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:53:19.902 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:53:20.375 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:53:20.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:20.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:20.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:20.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:20.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:20.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:20.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:20.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:20.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:20.479 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:20.479 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:20.480 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:20.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:20.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:20.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:20.480 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1861 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:20.480 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:20.481 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:20.481 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:20.481 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:20.481 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:25.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:25.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:25.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:25.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:25.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:25.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:25.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:25.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:25.492 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:25.493 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:25.493 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:25.497 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:25.497 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:25.497 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:25.497 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:25.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:25.497 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:25.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:25.498 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:25.502 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:25.503 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:25.503 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:25.503 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:25.503 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:25.503 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:25.503 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:25.504 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:25.508 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:25.508 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:25.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:25.509 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:25.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:25.509 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:25.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:25.509 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:25.515 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:25.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:25.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:25.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:53:25.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:53:25.517 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:25.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:25.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:25.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:25.522 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:25.997 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:26.049 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:26.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:26.050 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:26.051 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:26.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:26.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:26.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:53:26.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:26.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:26.070 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:26.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:53:26.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:53:26.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:26.097 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:53:26.097 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:53:26.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:26.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:26.468 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:53:26.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:26.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:26.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:26.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:26.940 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:53:27.414 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:53:27.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:27.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:27.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:27.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:27.887 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:53:28.360 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:53:28.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:28.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:28.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:28.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:28.834 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:53:29.307 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:53:29.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:29.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:29.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:29.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:29.780 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:53:30.253 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:53:30.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:30.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:30.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:30.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:30.725 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:53:31.198 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:53:31.671 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:53:32.144 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:53:32.618 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:53:33.089 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:53:33.562 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:53:34.036 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:53:34.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:34.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:34.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:34.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:34.107 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:53:34.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:34.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:34.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:34.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:34.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:34.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:34.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:34.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:34.130 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:34.130 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:34.130 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:34.130 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:34.131 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:34.131 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:34.131 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:34.131 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:34.131 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.132 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:39.132 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:39.132 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:39.132 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:39.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:39.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:39.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:39.141 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:39.141 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:39.141 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:39.141 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:39.143 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:39.144 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:39.144 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:39.144 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:39.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:39.145 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:39.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:39.145 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:39.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:39.148 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:39.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:39.148 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:39.149 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:39.149 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:39.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:39.149 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:39.152 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:39.153 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:39.153 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:39.153 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:39.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:39.153 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:39.153 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:39.153 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:39.158 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:39.158 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:39.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:39.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.159 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:53:39.159 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:53:39.159 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:39.160 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:39.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:39.164 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:39.640 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:39.692 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:39.694 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:39.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:39.696 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:39.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:39.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:39.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:53:39.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:39.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:39.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:39.723 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:53:39.723 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:53:39.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:39.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:39.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:39.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:39.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:39.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:39.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:39.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:39.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:39.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:39.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:39.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:39.900 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:39.900 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.900 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.900 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.900 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.900 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.900 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.900 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:39.901 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=160 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:53:44.904 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:44.904 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:44.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:44.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:44.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:44.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:44.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:44.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:44.914 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:44.915 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:44.915 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:44.918 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:44.919 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:44.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:44.920 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:44.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:44.921 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:44.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:44.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:44.923 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:44.923 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:44.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:44.924 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:44.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:44.924 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:44.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:44.924 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:44.927 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:44.928 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:44.928 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:44.928 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:44.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:44.928 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:44.928 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:44.928 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:53:44.932 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:53:44.932 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:44.932 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:53:44.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:44.937 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:53:45.411 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:53:45.463 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:53:45.465 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:53:45.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:53:45.468 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:53:45.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:45.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:45.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:53:45.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:53:45.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:53:45.502 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:53:45.502 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:53:45.502 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:53:45.883 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:53:45.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:45.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:45.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:45.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:46.354 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:53:46.825 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:53:46.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:46.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:46.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:46.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:47.298 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:53:47.771 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:53:47.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:47.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:47.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:47.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:48.243 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:53:48.714 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:53:48.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:48.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:48.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:48.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:49.187 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:53:49.659 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:53:49.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:49.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:49.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:49.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:50.132 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:53:50.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:53:50.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:53:50.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:53:50.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:53:50.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:50.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:50.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:50.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:50.157 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:50.157 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:50.606 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:53:51.083 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:53:51.553 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:53:52.030 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:53:52.508 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:53:52.979 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:53:53.457 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:53:53.936 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:53:54.415 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:53:54.893 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:53:55.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:53:55.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:53:55.159 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:55.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:55.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:55.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:55.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:55.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:55.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:55.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:55.165 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:55.165 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:55.165 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:53:55.165 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:53:55.167 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:53:55.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:53:55.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:55.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:55.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:53:55.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:53:55.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:53:55.167 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:53:55.169 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:53:55.169 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:53:55.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:55.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:55.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:53:55.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:53:55.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:53:55.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:53:55.171 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:53:55.171 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:53:55.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:55.171 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:53:55.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:53:55.172 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:53:55.172 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:53:55.172 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:53:55.173 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:53:55.174 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:53:55.174 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:53:55.174 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:53:55.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:53:55.175 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:53:55.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:00.186 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:54:00.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:00.186 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:00.186 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:00.186 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:00.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:00.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:00.204 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:00.204 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:54:00.209 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:54:00.209 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:54:00.209 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:00.209 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.210 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:00.210 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.211 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:00.211 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:54:00.212 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:54:00.212 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:54:00.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:00.213 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:00.213 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:00.213 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:54:00.215 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:54:00.215 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:54:00.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:00.215 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:00.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:00.215 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:00.215 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:54:00.218 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:54:00.218 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:54:00.218 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:00.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:00.223 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:54:00.700 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:54:00.744 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:00.748 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:00.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:00.750 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:54:00.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:00.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:00.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:54:00.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:00.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:00.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:00.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:54:00.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:54:01.172 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:54:01.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:01.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:01.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:01.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:01.643 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:54:02.114 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:54:02.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:02.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:02.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:02.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:02.580 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:54:03.043 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:54:03.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:03.224 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:03.224 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:03.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:03.507 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:54:03.979 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:54:04.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:04.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:04.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:04.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:04.449 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:54:04.915 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:54:05.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:05.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:05.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:05.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:05.380 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:54:05.845 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:54:06.309 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:54:06.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:06.779 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:54:07.245 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:54:07.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:07.711 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:54:08.177 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:54:08.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:08.643 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:54:09.106 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:54:09.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:09.573 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:54:10.042 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:54:10.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:10.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:10.512 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:54:10.979 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:54:11.446 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:54:11.910 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:54:12.378 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:54:12.845 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:54:13.310 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:54:13.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:13.781 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:54:14.252 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:54:14.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:14.723 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:54:15.193 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:54:15.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:15.662 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:54:16.132 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:54:16.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:16.600 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:54:17.069 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:54:17.537 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:54:17.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:18.004 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:54:18.469 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:54:18.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:18.933 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:54:19.398 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:54:19.864 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:54:20.333 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:54:20.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:20.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:20.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:20.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:20.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:20.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:20.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:20.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:20.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:54:20.733 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:54:20.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:20.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:20.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:20.734 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4475 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:20.734 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4475 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:20.734 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4475 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:20.734 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4475 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:20.734 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4475 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:20.734 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4475 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:25.731 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:25.731 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:54:25.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:25.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:25.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:25.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:25.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:25.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:25.735 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:25.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:25.735 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:54:25.736 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:54:25.736 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:54:25.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:25.736 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:25.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:25.736 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:54:25.737 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:25.737 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:54:25.737 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:54:25.737 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:54:25.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:25.737 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:25.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:25.737 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:54:25.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:25.737 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:54:25.738 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:54:25.738 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:54:25.738 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:25.739 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:25.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:25.739 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:54:25.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:25.739 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.740 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:54:25.740 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:54:25.740 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:54:25.741 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:25.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:25.745 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:54:26.211 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:54:26.256 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:26.257 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:26.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:26.258 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:54:26.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:26.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:26.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:54:26.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:26.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:26.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:26.274 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:54:26.274 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:54:26.303 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:26.306 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:26.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:54:26.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:26.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:26.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:26.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:26.676 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:54:26.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:26.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:26.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:26.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:27.140 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:54:27.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:54:27.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:27.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:27.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:27.578 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:27.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:27.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:27.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:27.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:27.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:27.579 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:27.579 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:54:27.579 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:54:27.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:27.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:32.582 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:32.582 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:54:32.582 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:32.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:32.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:32.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:32.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:32.590 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:32.590 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:32.590 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:32.590 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:54:32.592 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:54:32.592 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:54:32.592 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:32.592 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:32.592 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:32.592 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:54:32.592 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:32.592 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:54:32.595 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:54:32.595 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:54:32.595 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:32.595 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:32.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:32.595 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:54:32.595 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:32.595 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:54:32.597 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:54:32.598 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:54:32.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:32.598 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:32.598 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:32.598 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:54:32.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:32.598 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:54:32.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:54:32.603 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:54:32.603 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:54:32.603 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:32.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:32.607 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:54:33.076 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:54:33.118 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:33.119 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:33.119 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:54:33.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:33.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:33.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:33.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:54:33.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:33.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:33.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:33.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:54:33.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:54:33.165 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:33.166 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:33.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:54:33.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:33.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:33.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:33.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:33.541 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:54:33.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:33.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:33.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:33.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:34.015 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:54:34.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 02:54:34.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:34.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:34.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:34.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:34.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:34.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:34.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:34.454 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:34.454 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:34.454 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:54:34.454 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:54:34.454 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:34.454 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:34.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:34.454 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:34.454 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:34.454 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:34.454 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:34.454 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:34.454 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:54:39.463 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:54:39.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:54:39.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:39.463 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:39.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:39.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:39.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:54:39.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:39.478 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:39.478 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:54:39.478 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:54:39.481 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:54:39.481 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:54:39.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:39.482 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:39.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:54:39.482 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:54:39.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:54:39.482 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:54:39.485 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:54:39.485 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:54:39.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:39.485 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:39.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:54:39.486 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:54:39.486 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:54:39.486 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:54:39.488 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:54:39.488 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:54:39.488 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:39.488 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:54:39.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:54:39.488 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:54:39.488 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:54:39.488 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.491 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:54:39.491 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:54:39.491 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:54:39.492 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:54:39.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:54:39.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:54:39.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:54:39.496 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:54:39.967 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:54:40.011 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:54:40.012 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:54:40.012 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:54:40.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:40.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:40.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:40.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:54:40.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:40.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:40.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:40.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:54:40.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:54:40.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:40.060 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:40.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:40.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:40.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:40.434 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:54:40.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:40.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:40.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:40.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:40.902 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:54:41.371 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:54:41.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:41.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:41.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:41.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:41.840 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:54:42.307 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:54:42.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:42.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:42.774 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:54:43.245 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:54:43.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:43.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:43.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:43.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:43.714 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:54:44.182 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:54:44.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:54:44.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:54:44.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:54:44.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:54:44.653 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:54:45.120 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:54:45.588 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:54:46.060 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:54:46.533 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:54:47.006 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:54:47.479 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:54:47.951 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:54:48.422 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:54:48.895 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:54:49.368 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:54:49.841 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:54:50.312 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:54:50.785 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:54:51.258 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:54:51.730 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:54:52.203 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:54:52.676 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:54:53.146 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:54:53.618 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:54:54.090 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:54:54.564 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:54:55.036 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:54:55.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:55.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:55.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:55.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:54:55.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:54:55.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:54:55.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:54:55.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:54:55.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:54:55.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:54:55.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:54:55.363 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:54:55.363 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 02:54:55.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:54:55.509 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:54:55.982 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:54:56.454 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:54:56.927 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:54:57.401 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:54:57.873 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:54:58.346 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:54:58.819 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:54:59.292 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:54:59.765 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:55:00.238 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:55:00.711 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:55:01.184 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:55:01.657 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:55:02.130 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:55:02.602 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:55:03.075 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:55:03.549 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:55:04.021 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:55:04.495 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:55:04.967 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 02:55:05.440 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 02:55:05.913 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 02:55:06.386 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 02:55:06.859 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 02:55:07.332 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 02:55:07.805 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 02:55:08.277 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 02:55:08.751 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 02:55:09.224 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 02:55:09.696 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 02:55:10.170 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 02:55:10.643 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 02:55:10.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:10.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:10.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:10.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:55:10.828 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:55:10.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:10.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:55:10.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:55:10.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:10.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:10.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:10.848 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:55:10.848 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:55:10.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:10.883 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:55:10.883 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 02:55:10.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:10.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:11.114 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 02:55:11.588 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 02:55:12.061 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 02:55:12.533 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 02:55:13.005 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 02:55:13.479 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 02:55:13.951 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 02:55:14.424 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 02:55:14.897 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 02:55:15.369 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 02:55:15.842 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 02:55:16.315 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 02:55:16.787 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 02:55:17.260 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 02:55:17.733 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 02:55:18.205 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 02:55:18.678 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 02:55:19.152 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 02:55:19.624 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 02:55:20.097 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 02:55:20.570 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 02:55:21.042 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 02:55:21.515 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 02:55:21.988 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 02:55:22.460 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 02:55:22.933 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 02:55:23.406 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 02:55:23.878 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 02:55:24.352 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 02:55:24.825 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 02:55:25.296 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 02:55:25.770 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 02:55:26.243 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 02:55:26.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:26.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:26.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:26.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:55:26.310 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:55:26.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:26.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:55:26.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:55:26.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:26.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:26.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:26.324 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:55:26.324 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:55:26.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:26.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:26.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:26.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:26.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:26.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:26.715 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 02:55:27.186 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 02:55:27.660 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 02:55:28.132 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 02:55:28.605 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 02:55:29.078 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 02:55:29.551 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 02:55:30.023 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 02:55:30.494 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 02:55:30.987 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 02:55:31.459 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 02:55:31.933 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 02:55:32.405 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 02:55:32.878 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 02:55:33.351 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 02:55:33.824 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 02:55:34.296 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 02:55:34.767 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 02:55:35.240 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 02:55:35.713 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 02:55:36.186 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 02:55:36.657 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 02:55:37.130 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 02:55:37.602 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 02:55:38.075 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 02:55:38.548 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 02:55:39.020 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 02:55:39.493 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 02:55:39.964 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 02:55:40.437 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 02:55:40.909 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 02:55:41.382 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 02:55:41.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:41.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:41.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:41.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:55:41.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:41.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:41.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:41.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:41.820 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:41.820 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:41.820 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:55:41.820 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:55:41.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:41.820 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:41.820 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:41.820 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13459 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:41.820 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13459 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:41.820 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13459 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:41.820 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13459 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:41.820 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13459 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:41.820 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=13459 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:55:46.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:46.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:55:46.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:46.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:46.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:46.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:46.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:46.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:46.840 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:46.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:46.840 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:55:46.845 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:55:46.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:55:46.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:46.847 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:46.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:46.847 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:55:46.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:46.848 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:55:46.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:55:46.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:55:46.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:46.852 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:46.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:46.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:55:46.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:46.853 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:55:46.855 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:55:46.856 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:55:46.856 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:46.856 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:46.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:46.857 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:55:46.857 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:46.857 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:55:46.860 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:55:46.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:55:46.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:55:46.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:55:46.860 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:55:46.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:55:46.861 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:55:46.861 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:46.861 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:46.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:55:46.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:46.863 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:55:46.863 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:46.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:55:51.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:55:51.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:51.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:51.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:51.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:51.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:55:51.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:51.876 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:51.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:55:51.876 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:55:51.879 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:55:51.879 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:55:51.879 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:51.879 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:51.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:55:51.880 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:55:51.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:55:51.880 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:55:51.881 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:55:51.882 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:55:51.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:51.882 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:51.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:55:51.882 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:55:51.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:55:51.882 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:55:51.884 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:55:51.884 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:55:51.884 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:51.884 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:55:51.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:55:51.884 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:55:51.884 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:55:51.884 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:55:51.887 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:55:51.887 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:55:51.887 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:55:51.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:55:51.892 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:55:52.371 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:55:52.408 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:55:52.410 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:52.411 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:55:52.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:52.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:55:52.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:55:52.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:55:52.443 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:55:52.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:52.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:52.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:52.447 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:55:52.447 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:55:52.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:55:52.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:55:52.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:55:52.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:52.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:55:52.842 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:55:52.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:52.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:52.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:52.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:53.314 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:55:53.787 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:55:53.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:53.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:53.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:53.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:54.260 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:55:54.733 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:55:54.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:54.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:54.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:54.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:55.207 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:55:55.679 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:55:55.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:55.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:55.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:55.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:56.160 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:55:56.633 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:55:56.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:55:56.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:55:56.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:55:56.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:55:57.106 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:55:57.578 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:55:58.049 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:55:58.523 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:55:58.996 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:55:59.468 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:55:59.942 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:56:00.414 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:56:00.887 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:56:01.360 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:56:01.833 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:56:02.305 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:56:02.778 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:56:02.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:02.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:02.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:02.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:56:02.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:02.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:02.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:02.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:02.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:02.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:02.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:02.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:02.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:02.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:56:02.872 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:56:02.872 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2369 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:02.873 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2369 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:02.873 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2369 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:02.873 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2369 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:02.873 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2369 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:02.873 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2369 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:02.873 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2369 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:07.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:07.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:56:07.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:07.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:07.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:07.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:07.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:07.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:07.884 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:07.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:07.884 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:56:07.888 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:56:07.888 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:56:07.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:07.889 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:07.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:07.890 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:56:07.890 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:07.891 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:56:07.893 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:56:07.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:56:07.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:07.894 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:07.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:07.894 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:56:07.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:07.895 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:56:07.897 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:56:07.898 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:56:07.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:07.898 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:07.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:07.898 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:56:07.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:07.898 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:56:07.903 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:56:07.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.904 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:56:07.904 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:56:07.904 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:56:07.905 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:07.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:07.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:07.909 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:56:08.386 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:56:08.422 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:56:08.423 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:08.424 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:56:08.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:08.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:08.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:56:08.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:56:08.447 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:08.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:08.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:08.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:08.450 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:56:08.450 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:56:08.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:08.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:08.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:08.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:08.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:08.856 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:56:08.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:08.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:08.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:08.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:09.329 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:56:09.802 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:56:09.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:09.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:09.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:09.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:10.275 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:56:10.748 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:56:10.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:10.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:10.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:10.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:11.220 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:56:11.691 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:56:11.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:11.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:11.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:11.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:12.162 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:56:12.635 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:56:12.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:12.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:12.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:12.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:13.108 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:56:13.580 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:56:14.054 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:56:14.526 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:56:14.999 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:56:15.472 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:56:15.945 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:56:16.417 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:56:16.891 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:56:17.363 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:56:17.836 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:56:18.307 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:56:18.780 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:56:18.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:18.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:18.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:18.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:56:18.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:18.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:18.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:18.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:18.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:18.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:18.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:18.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:18.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:18.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:56:18.869 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:56:23.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:23.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:56:23.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:23.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:23.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:23.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:23.883 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:23.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:23.883 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:23.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:23.884 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:56:23.887 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:56:23.888 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:56:23.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:23.888 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:23.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:23.889 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:56:23.890 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:23.890 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:56:23.892 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:56:23.892 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:56:23.892 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:23.892 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:23.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:23.893 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:56:23.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:23.893 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:56:23.895 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:56:23.895 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:56:23.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:23.895 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:23.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:23.896 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:56:23.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:23.896 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:56:23.899 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:56:23.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:56:23.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:56:23.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:56:23.899 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:56:23.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:56:23.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:56:23.900 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:56:23.900 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:56:23.900 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:23.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:23.905 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:56:24.382 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:56:24.425 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:56:24.427 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:24.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:24.429 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:56:24.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:24.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:56:24.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:56:24.448 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:24.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:24.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:24.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:24.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:56:24.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:56:24.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:24.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:24.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:24.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:24.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:24.854 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:56:24.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:24.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:24.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:24.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:25.325 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:56:25.340 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:25.796 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:56:25.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:25.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:25.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:25.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:26.269 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:56:26.742 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:56:26.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:26.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:26.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:26.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:27.215 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:56:27.688 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:56:27.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:27.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:27.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:27.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:28.161 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:56:28.633 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:56:28.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:28.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:28.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:28.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:29.106 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:56:29.579 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:56:30.052 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:56:30.525 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:56:30.998 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:56:31.470 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:56:31.943 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:56:32.416 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:56:32.889 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:56:33.362 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:56:33.835 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:56:34.307 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:56:34.781 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:56:35.253 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:56:35.726 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:56:36.199 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:56:36.672 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:56:37.144 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:56:37.618 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:56:38.090 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:56:38.563 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:56:39.036 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:56:39.509 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:56:39.981 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:56:40.452 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:56:40.925 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:56:41.398 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:56:41.871 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:56:42.344 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:56:42.817 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:56:43.289 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:56:43.762 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:56:44.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:44.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:44.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:44.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:56:44.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:44.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:44.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:44.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:44.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:44.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:44.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:44.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:44.085 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:44.085 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:56:44.085 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:56:44.085 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4356 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:44.085 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4356 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:44.085 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4356 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:44.085 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4356 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:44.085 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4356 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:44.085 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4356 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:56:49.088 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:56:49.088 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:56:49.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:49.088 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:49.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:49.089 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:49.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:56:49.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:49.099 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:49.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:56:49.099 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:56:49.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:56:49.103 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:56:49.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:49.104 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:49.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:56:49.105 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:56:49.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:56:49.105 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:56:49.107 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:56:49.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:56:49.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:49.107 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:49.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:56:49.108 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:56:49.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:56:49.108 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:56:49.109 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:56:49.110 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:56:49.110 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:49.110 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:56:49.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:56:49.110 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:56:49.110 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:56:49.110 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.113 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:56:49.113 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:56:49.113 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:56:49.113 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:56:49.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:56:49.118 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:56:49.596 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:56:49.632 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:56:49.633 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:49.634 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:56:49.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:49.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:56:49.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:56:49.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:56:49.655 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:56:49.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:49.659 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:49.659 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:49.659 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:56:49.659 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:56:49.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:56:49.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:56:49.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:56:49.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:49.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:56:50.069 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:56:50.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:50.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:50.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:50.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:50.543 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:56:50.554 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:51.016 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:56:51.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:51.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:51.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:51.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:51.488 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:56:51.521 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:51.962 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:56:52.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:52.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:52.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:52.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:52.434 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:56:52.487 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:52.906 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:56:53.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:53.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:53.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:53.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:53.377 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:56:53.447 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:53.851 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:56:54.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:56:54.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:56:54.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:56:54.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:56:54.324 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:56:54.413 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:54.796 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:56:55.270 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:56:55.373 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:55.742 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:56:56.220 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:56:56.344 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:56.693 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:56:57.166 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:56:57.311 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:57.639 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:56:58.112 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:56:58.272 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:58.585 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:56:59.057 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:56:59.238 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:56:59.528 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:57:00.002 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:57:00.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:00.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:00.083 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:00.083 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:00.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:00.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:00.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:00.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:00.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:00.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:00.097 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:00.097 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:00.097 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:00.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:00.097 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:05.106 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:05.106 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:05.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:05.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:05.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:05.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:05.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:05.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:05.117 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:05.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:05.117 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:05.119 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:05.119 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:05.119 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:05.119 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:05.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:05.120 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:05.120 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:05.120 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:05.120 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:05.121 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:05.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:05.121 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:05.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:05.121 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:05.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:05.121 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:05.122 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:05.122 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:05.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:05.122 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:05.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:05.122 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:05.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:05.122 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:57:05.124 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:57:05.124 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:05.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:05.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:05.129 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:05.603 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:05.648 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:05.649 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:05.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:05.650 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:05.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:05.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:05.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:05.677 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:05.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:05.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:05.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:05.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:05.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:05.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:05.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:05.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:05.703 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:05.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:05.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:06.074 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:06.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:06.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:06.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:06.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:06.546 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:06.562 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:57:06.563 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:07.019 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:07.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:07.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:07.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:07.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:07.490 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:57:07.963 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:57:08.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:08.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:08.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:08.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:08.436 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:57:08.908 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:57:09.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:09.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:09.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:09.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:09.379 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:57:09.853 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:57:10.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:10.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:10.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:10.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:10.325 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:57:10.798 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:57:11.271 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:57:11.744 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:57:12.216 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:57:12.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:12.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:12.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:12.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:12.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:12.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:12.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:12.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:12.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:12.363 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:12.363 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:12.363 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:12.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:12.364 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:12.364 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:12.364 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:12.364 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:12.364 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:12.364 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:12.364 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:12.364 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:12.364 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:17.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:17.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:17.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:17.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:17.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:17.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:17.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:17.370 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:17.370 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:17.370 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:17.370 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:17.371 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:17.372 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:17.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:17.372 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:17.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:17.372 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:17.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:17.372 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:17.373 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:17.373 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:17.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:17.373 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:17.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:17.373 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:17.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:17.373 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:17.374 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:17.374 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:17.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:17.374 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:17.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:17.374 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:17.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:17.374 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:57:17.376 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:57:17.376 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:17.376 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:17.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:17.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:17.381 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:17.860 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:17.900 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:17.902 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:17.904 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:17.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:17.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:17.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:17.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:17.929 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:17.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:17.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:17.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:17.932 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:17.932 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:17.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:17.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:17.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:17.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:17.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:18.331 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:18.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:18.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:18.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:18.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:18.803 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:18.819 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:57:19.276 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:19.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:19.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:19.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:19.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:19.749 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:57:20.222 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:57:20.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:20.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:20.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:20.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:20.694 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:57:21.167 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:57:21.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:21.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:21.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:21.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:21.640 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:57:22.113 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:57:22.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:22.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:22.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:22.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:22.586 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:57:23.059 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:57:23.531 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:57:24.005 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:57:24.477 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:57:24.950 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:57:25.420 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:57:25.891 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:57:26.366 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:57:26.838 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:57:27.312 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:57:27.784 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:57:27.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:27.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:27.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:27.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:27.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:27.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:27.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:27.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:27.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:27.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:27.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:27.984 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:27.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:27.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:27.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:27.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2289 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:27.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2289 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:27.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2289 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:27.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2289 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:27.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2289 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:27.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2289 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:32.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:32.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:32.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:32.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:32.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:32.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:32.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:32.999 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:32.999 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:32.999 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:32.999 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:33.004 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:33.005 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:33.005 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:33.005 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:33.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:33.005 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:33.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:33.006 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:33.010 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:33.010 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:33.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:33.010 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:33.011 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:33.011 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:33.011 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:33.011 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:33.014 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:33.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:33.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:33.015 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:33.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:33.015 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:33.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:33.015 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:33.019 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:33.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:33.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:33.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:33.019 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:57:33.020 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:57:33.020 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:33.020 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:33.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:33.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:33.025 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:33.504 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:33.544 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:33.545 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:33.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:33.547 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:33.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:33.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:33.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:33.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:33.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:33.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:33.575 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:33.575 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:33.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:33.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:33.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:33.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:33.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:33.975 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:33.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:33.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:33.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:33.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:33.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:33.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:33.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:34.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:34.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:34.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:34.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:34.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:34.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:34.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:34.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:34.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:34.026 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:57:34.027 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:57:34.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.448 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:34.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:34.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:34.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:34.708 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:57:34.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:34.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:34.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:34.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:34.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:34.727 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:34.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:34.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:34.780 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:34.781 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:34.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:34.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:34.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:34.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:34.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:34.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:34.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:34.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:34.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:34.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:34.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:34.914 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:57:34.914 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:57:34.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:34.920 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:35.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:35.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:35.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:35.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:35.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:35.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:35.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:35.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:35.312 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:57:35.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:35.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:35.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:35.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:35.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:35.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:35.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:35.327 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:35.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:35.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:35.327 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.328 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.329 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.329 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.329 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.329 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.329 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:35.329 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=499 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:57:40.329 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:40.329 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:40.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:40.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:40.333 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:40.333 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:40.333 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:40.333 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:40.334 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:40.334 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:40.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:40.334 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:40.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:40.334 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:40.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:40.334 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:40.335 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:40.335 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:40.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:40.335 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:40.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:40.335 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:40.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:40.335 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:40.336 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:40.336 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:40.336 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:40.336 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:40.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:40.337 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:40.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:40.337 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:40.338 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:40.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:40.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:40.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:40.338 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:40.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:57:40.339 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:57:40.339 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:40.339 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:40.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:40.343 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:40.820 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:40.863 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:40.864 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:40.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:40.866 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:40.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:40.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:40.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:40.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:40.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:40.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:40.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:40.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:40.912 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:40.916 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 02:57:40.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:40.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:40.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:40.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:40.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:41.291 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:41.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:41.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:41.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:41.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:41.313 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:41.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:41.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:41.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:41.314 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:41.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:41.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:41.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:41.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:41.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:41.314 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:57:46.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:46.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:46.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:46.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:46.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:46.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:46.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:46.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:46.331 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:46.332 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:57:46.332 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:57:46.338 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:57:46.338 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:57:46.339 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:46.339 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:46.339 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:46.340 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:57:46.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:57:46.341 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:57:46.343 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:57:46.343 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:57:46.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:46.344 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:46.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:46.344 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:57:46.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:57:46.344 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:57:46.346 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:57:46.346 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:57:46.346 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:46.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:57:46.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:46.347 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:57:46.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:57:46.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.350 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:57:46.351 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:57:46.351 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:57:46.351 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:57:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:57:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:57:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:57:46.355 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:57:46.833 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:57:46.879 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:57:46.882 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:57:46.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:46.884 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:57:46.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:46.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:46.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:46.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:46.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:46.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:46.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:46.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:46.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:46.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:46.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:46.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:46.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:47.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:47.303 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:57:47.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:47.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:47.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:47.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:47.776 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:57:48.249 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:57:48.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:48.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:48.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:48.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:48.720 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:57:49.193 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:57:49.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:49.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:49.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:49.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:49.666 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:57:50.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:50.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:50.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:50.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:50.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:50.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:50.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:50.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:50.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:50.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:50.065 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:50.065 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:50.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:50.087 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:57:50.087 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 02:57:50.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:50.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:50.138 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:57:50.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:50.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:50.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:50.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:50.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:50.610 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:57:51.084 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:57:51.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:51.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:51.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:51.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:51.556 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:57:52.030 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:57:52.503 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:57:52.975 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:57:53.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:53.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:53.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:53.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:53.233 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:57:53.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:53.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:53.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:53.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:53.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:53.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:53.253 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:53.253 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:53.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:53.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:53.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:53.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:53.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:53.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:53.446 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:57:53.917 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:57:54.390 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:57:54.862 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:57:55.334 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:57:55.805 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:57:56.276 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:57:56.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:56.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:56.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:56.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:56.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:56.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:56.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:57:56.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:56.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:57:56.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:57:56.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:57:56.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:57:56.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:56.517 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:57:56.518 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:57:56.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:56.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:56.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:56.747 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:57:57.218 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:57:57.691 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:57:58.164 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:57:58.636 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:57:59.109 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:57:59.581 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:57:59.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:57:59.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:57:59.674 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:57:59.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:57:59.674 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:57:59.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:57:59.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:57:59.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:57:59.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:57:59.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:57:59.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:57:59.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:57:59.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:57:59.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:57:59.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:57:59.687 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:58:04.692 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:04.692 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:58:04.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:04.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:04.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:04.692 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:04.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:04.708 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:04.708 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:04.709 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:04.709 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:58:04.711 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:58:04.711 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:58:04.711 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:04.711 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:04.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:04.711 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:58:04.711 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:04.711 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:58:04.713 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:58:04.713 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:58:04.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:04.713 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:04.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:04.713 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:58:04.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:04.713 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:58:04.715 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:58:04.715 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:58:04.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:04.715 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:04.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:04.715 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:58:04.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:04.715 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:58:04.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:58:04.717 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:58:04.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:04.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:04.722 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:58:05.197 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:58:05.241 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:58:05.243 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:58:05.244 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:58:05.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:05.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:05.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:58:05.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:58:05.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:05.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:58:05.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:58:05.248 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:58:05.248 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:58:05.669 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:58:05.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:05.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:05.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:05.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:06.141 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:58:06.614 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:58:06.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:06.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:06.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:06.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:07.086 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:58:07.558 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:58:07.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:07.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:07.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:07.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:08.029 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:58:08.502 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:58:08.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:08.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:08.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:08.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:08.975 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:58:09.447 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:58:09.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:09.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:09.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:09.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:09.918 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:58:10.391 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:58:10.864 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:58:11.336 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:58:11.807 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:58:12.280 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:58:12.753 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:58:13.225 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:58:13.696 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:58:14.169 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:58:14.641 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:58:15.113 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:58:15.584 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:58:16.057 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:58:16.530 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:58:17.002 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:58:17.473 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:58:17.946 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:58:18.419 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:58:18.891 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:58:19.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:19.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:58:19.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:19.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:19.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:19.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:19.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:19.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:19.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:58:19.188 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:58:24.193 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:24.193 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:58:24.193 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:24.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:24.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:24.193 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:24.196 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:24.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:24.197 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.197 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:24.197 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:58:24.198 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:58:24.198 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:58:24.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:24.198 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:24.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:24.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:58:24.199 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:58:24.199 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:58:24.199 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:24.199 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.199 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:24.199 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.199 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:24.199 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:58:24.200 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:58:24.200 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:58:24.200 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:24.200 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:24.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:24.200 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.200 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:24.200 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:58:24.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:58:24.203 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:58:24.203 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:58:24.203 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:24.207 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:58:24.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:58:24.723 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:58:24.724 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:58:24.725 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:58:24.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:24.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:24.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:58:24.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:58:24.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:24.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:58:24.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:58:24.746 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:58:24.746 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:58:24.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:24.790 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 02:58:24.790 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 02:58:24.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:24.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:25.158 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:58:25.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:25.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:25.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:25.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:25.632 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:58:26.104 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:58:26.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:26.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:26.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:26.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:26.577 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:58:26.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:26.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:26.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:58:26.791 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 02:58:26.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:58:26.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:26.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:58:26.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:58:26.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:58:26.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:58:27.050 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:58:27.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:27.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:27.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:27.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:27.522 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:58:27.994 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:58:28.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:28.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:28.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:28.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:28.465 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:58:28.939 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:58:29.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:29.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:29.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:29.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:29.411 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:58:29.883 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:58:30.354 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:58:30.825 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:58:31.296 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:58:31.765 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:58:32.237 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:58:32.709 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:58:33.180 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:58:33.651 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:58:34.122 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:58:34.595 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:58:35.067 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:58:35.540 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:58:36.011 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:58:36.484 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:58:36.956 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:58:37.429 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:58:37.899 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:58:38.370 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:58:38.843 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:58:39.316 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:58:39.788 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:58:40.262 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:58:40.734 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:58:41.206 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:58:41.680 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:58:42.152 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:58:42.625 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:58:43.097 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:58:43.570 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:58:44.042 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:58:44.513 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:58:44.987 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:58:45.459 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:58:45.931 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:58:46.402 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 02:58:46.875 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 02:58:47.348 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 02:58:47.820 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 02:58:48.294 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 02:58:48.766 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 02:58:49.238 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 02:58:49.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:49.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:49.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:58:49.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:49.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:49.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:49.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:49.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:49.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:49.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:49.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:49.535 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:49.535 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:58:49.535 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:58:49.535 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5472 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:49.535 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5472 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:49.535 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5472 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:49.535 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5472 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:49.535 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5472 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:49.535 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5472 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:58:54.534 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:58:54.534 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:58:54.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:54.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:54.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:54.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:54.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:58:54.538 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:54.538 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:54.538 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:58:54.538 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:58:54.539 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:58:54.539 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:58:54.539 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:54.539 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:54.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:58:54.539 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:58:54.539 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:58:54.539 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:58:54.540 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:58:54.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:58:54.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:54.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:54.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:58:54.540 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:58:54.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:58:54.540 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:58:54.541 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:58:54.541 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:58:54.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:54.541 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:58:54.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:58:54.541 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:58:54.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:58:54.542 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:58:54.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:58:54.544 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:58:54.544 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:58:54.544 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:58:54.548 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:58:55.010 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:58:55.054 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:58:55.055 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:58:55.055 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:58:55.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:58:55.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:58:55.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:58:55.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:58:55.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:58:55.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:58:55.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:58:55.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:58:55.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:58:55.473 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:58:55.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:55.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:55.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:55.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:55.936 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:58:56.398 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:58:56.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:56.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:56.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:56.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:56.866 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:58:57.338 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:58:57.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:57.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:57.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:57.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:57.810 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:58:58.281 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:58:58.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:58.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:58.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:58.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:58.752 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:58:59.225 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:58:59.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:58:59.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:58:59.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:58:59.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:58:59.698 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:59:00.170 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:59:00.641 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:59:01.114 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:59:01.587 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:59:02.059 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:59:02.532 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:59:03.005 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:59:03.477 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:59:03.948 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:59:04.421 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:59:04.894 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:59:05.366 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:59:05.837 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:59:06.310 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:59:06.782 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:59:07.254 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:59:07.726 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:59:08.199 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:59:08.671 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:59:09.143 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:59:09.617 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:59:10.089 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:59:10.562 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:59:11.035 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:59:11.507 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:59:11.979 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:59:12.451 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:59:12.924 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:59:13.391 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:59:13.863 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:59:14.336 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:59:14.808 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:59:15.280 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:59:15.751 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:59:16.224 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:59:16.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:16.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:59:16.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:16.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:16.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:16.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:16.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:16.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:16.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:16.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:16.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:59:16.567 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:59:16.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:16.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4769 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:16.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4769 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:16.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4769 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:16.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4769 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:16.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4769 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:16.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4769 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:16.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4769 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 02:59:21.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:21.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:59:21.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:21.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:21.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:21.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:21.580 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:21.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:21.581 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:21.582 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:21.582 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:59:21.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:59:21.586 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:59:21.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:21.586 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:21.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:21.587 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:59:21.587 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:21.587 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:59:21.589 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:59:21.589 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:59:21.589 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:21.589 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:21.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:21.590 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:59:21.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:21.590 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:59:21.592 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:59:21.592 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:59:21.592 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:21.592 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:21.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:21.593 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:59:21.593 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:21.593 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:59:21.596 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:59:21.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:59:21.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:59:21.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:59:21.596 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:59:21.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:59:21.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:59:21.597 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:59:21.597 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:21.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:21.602 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:59:22.078 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:59:22.124 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:59:22.127 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:59:22.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:59:22.129 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:59:22.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:22.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:59:22.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:59:22.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:59:22.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:59:22.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:59:22.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:59:22.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:59:22.549 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:59:22.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:22.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:22.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:22.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:23.021 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:59:23.494 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:59:23.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:23.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:23.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:23.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:23.967 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:59:24.439 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:59:24.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:24.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:24.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:24.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:24.910 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:59:25.383 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:59:25.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:25.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:25.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:25.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:25.856 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:59:26.328 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:59:26.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:26.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:26.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:26.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:26.801 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:59:27.274 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:59:27.746 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:59:28.217 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:59:28.691 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:59:29.163 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:59:29.635 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:59:30.106 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:59:30.579 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:59:31.052 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:59:31.524 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:59:31.995 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:59:32.468 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:59:32.941 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 02:59:33.413 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 02:59:33.886 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 02:59:34.359 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 02:59:34.831 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 02:59:35.302 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 02:59:35.775 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 02:59:36.248 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 02:59:36.720 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 02:59:37.191 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 02:59:37.664 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 02:59:38.137 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 02:59:38.609 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 02:59:39.080 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 02:59:39.553 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 02:59:40.026 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 02:59:40.498 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 02:59:40.971 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 02:59:41.444 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 02:59:41.916 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 02:59:42.387 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 02:59:42.860 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 02:59:43.333 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 02:59:43.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:43.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:59:43.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:43.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:43.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:43.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:43.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:43.617 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:43.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:43.617 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:43.617 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:43.617 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:59:43.617 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 02:59:48.622 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 02:59:48.622 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 02:59:48.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:48.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:48.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:48.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:48.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 02:59:48.631 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:48.631 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:48.631 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 02:59:48.631 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 02:59:48.632 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 02:59:48.632 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 02:59:48.632 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:48.632 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:48.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 02:59:48.632 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 02:59:48.633 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 02:59:48.633 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 02:59:48.634 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 02:59:48.634 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 02:59:48.634 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:48.634 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:48.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 02:59:48.634 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 02:59:48.634 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 02:59:48.634 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 02:59:48.637 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 02:59:48.637 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 02:59:48.637 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:48.637 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 02:59:48.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 02:59:48.637 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 02:59:48.637 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 02:59:48.637 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 02:59:48.641 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 02:59:48.641 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 02:59:48.641 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 02:59:48.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 02:59:48.645 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 02:59:49.124 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 02:59:49.170 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 02:59:49.172 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 02:59:49.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 02:59:49.174 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 02:59:49.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 02:59:49.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 02:59:49.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 02:59:49.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 02:59:49.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 02:59:49.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 02:59:49.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 02:59:49.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 02:59:49.595 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 02:59:49.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:49.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:49.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:49.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:50.067 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 02:59:50.539 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 02:59:50.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:50.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:50.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:50.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:51.010 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 02:59:51.483 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 02:59:51.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:51.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:51.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:51.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:51.956 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 02:59:52.428 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 02:59:52.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:52.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:52.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:52.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:52.899 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 02:59:53.369 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 02:59:53.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 02:59:53.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 02:59:53.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 02:59:53.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 02:59:53.840 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 02:59:54.313 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 02:59:54.786 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 02:59:55.258 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 02:59:55.729 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 02:59:56.203 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 02:59:56.675 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 02:59:57.147 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 02:59:57.618 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 02:59:58.091 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 02:59:58.564 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 02:59:59.036 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 02:59:59.507 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 02:59:59.980 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:00:00.453 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:00:00.925 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:00:01.396 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:00:01.869 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:00:02.338 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:00:02.808 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:00:03.279 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:00:03.752 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:00:04.223 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:00:04.695 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:00:05.167 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:00:05.638 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:00:06.111 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:00:06.584 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:00:07.056 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:00:07.526 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:00:07.997 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:00:08.471 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:00:08.943 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:00:09.415 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:00:09.886 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:00:10.359 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:00:10.831 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:00:11.304 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:00:11.777 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:00:12.249 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:00:12.721 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:00:13.193 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:00:13.666 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:00:14.138 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:00:14.610 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:00:15.081 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:00:15.555 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:00:16.027 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:00:16.499 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:00:16.970 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:00:17.443 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:00:17.916 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:00:18.388 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:00:18.859 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:00:19.333 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:00:19.805 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:00:20.277 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:00:20.748 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:00:21.222 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:00:21.694 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:00:22.165 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:00:22.637 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:00:22.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:00:22.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:00:22.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:22.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:22.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:22.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:22.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:22.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:22.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:22.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:22.672 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:22.672 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:00:22.672 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:00:22.672 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7354 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:00:27.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:27.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:00:27.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:27.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:27.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:27.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:27.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:27.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:27.684 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:27.685 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:00:27.685 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:00:27.687 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:00:27.688 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:00:27.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:27.688 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:27.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:27.689 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:00:27.689 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:00:27.690 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:00:27.692 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:00:27.692 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:00:27.692 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:27.693 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:27.693 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:27.693 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:00:27.694 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:00:27.694 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:00:27.696 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:00:27.697 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:00:27.697 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:27.697 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:00:27.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:27.698 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:00:27.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:00:27.698 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:00:27.702 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.703 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:00:27.703 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:00:27.704 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:00:27.704 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:00:27.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:00:27.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.705 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:00:27.706 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:00:27.708 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:00:28.185 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:00:28.235 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:00:28.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:00:28.239 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:00:28.242 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:00:28.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:00:28.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:00:28.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:00:28.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:00:28.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:00:28.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:00:28.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:00:28.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:00:28.657 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:00:28.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:28.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:28.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:28.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:29.129 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:00:29.602 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:00:29.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:29.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:29.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:29.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:30.075 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:00:30.547 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:00:30.710 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:30.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:30.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:30.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:31.018 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:00:31.491 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:00:31.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:31.712 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:31.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:31.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:31.963 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:00:32.435 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:00:32.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:32.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:32.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:32.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:32.906 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:00:33.379 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:00:33.852 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:00:34.324 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:00:34.795 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:00:35.268 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:00:35.741 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:00:36.213 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:00:36.684 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:00:37.157 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:00:37.630 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:00:38.102 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:00:38.575 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:00:39.048 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:00:39.520 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:00:39.991 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:00:40.464 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:00:40.936 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:00:41.409 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:00:41.882 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:00:42.354 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:00:42.827 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:00:43.300 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:00:43.773 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:00:44.244 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:00:44.715 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:00:45.186 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:00:45.660 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:00:46.132 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:00:46.604 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:00:47.075 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:00:47.548 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:00:48.021 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:00:48.493 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:00:48.964 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:00:49.435 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:00:49.908 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:00:50.380 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:00:50.852 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:00:51.323 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:00:51.796 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:00:52.269 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:00:52.741 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:00:53.211 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:00:53.682 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:00:54.156 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:00:54.628 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:00:55.100 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:00:55.571 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:00:55.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:00:55.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:00:55.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:00:55.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:00:55.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:00:55.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:00:55.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:00:55.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:00:55.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:00:55.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:00:55.730 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:00:55.730 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:00:55.730 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:00.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:00.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:00.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:00.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:00.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:00.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:00.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:00.744 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:00.744 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:00.744 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:00.744 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:00.749 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:00.749 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:00.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:00.749 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:00.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:00.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:00.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:00.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:00.756 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:00.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:00.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:00.757 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:00.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:00.757 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:00.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:00.758 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:00.763 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:00.763 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:00.763 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:00.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:00.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:00.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:00.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:00.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:00.772 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:00.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:00.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.773 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:01:00.773 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:01:00.773 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:00.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:00.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:00.778 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:01.255 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:01.309 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:01.311 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:01.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:01.315 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:01.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:01.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:01.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:01.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:01.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:01.333 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:01.333 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:01.333 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:01.333 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:01.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:01.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:06.337 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:06.337 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:06.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:06.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:06.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:06.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:06.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:06.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:06.349 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:06.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:06.349 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:06.352 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:06.353 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:06.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:06.353 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:06.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:06.354 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:06.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:06.354 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:06.356 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:06.356 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:06.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:06.356 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:06.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:06.356 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:06.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:06.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:06.358 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:06.358 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:06.358 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:06.359 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:06.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:06.359 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:06.359 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:06.359 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:06.361 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:06.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:06.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:06.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:01:06.362 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:01:06.362 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:06.362 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:06.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:06.367 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:06.843 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:06.876 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:06.877 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:06.877 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:06.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:06.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:06.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:06.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:06.881 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:06.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:06.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:06.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:06.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:06.881 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:06.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:06.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:11.892 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:11.892 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:11.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:11.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:11.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:11.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:11.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:11.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:11.902 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:11.902 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:11.902 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:11.904 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:11.904 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:11.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:11.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:11.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:11.906 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:11.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:11.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:11.907 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:11.908 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:11.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:11.908 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:11.908 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:11.908 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:11.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:11.908 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:11.910 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:11.910 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:11.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:11.910 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:11.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:11.910 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:11.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:11.910 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:11.912 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:11.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:11.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:11.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:11.912 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:01:11.913 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:01:11.913 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:11.913 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:11.917 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:12.395 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:12.438 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:12.440 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:12.443 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:12.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:12.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:12.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:12.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:12.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:12.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:12.459 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:12.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:12.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:12.459 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:12.459 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:12.459 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:17.469 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:17.469 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:17.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:17.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:17.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:17.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:17.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:17.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:17.479 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:17.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:17.479 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:17.482 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:17.482 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:17.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:17.482 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:17.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:17.483 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:17.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:17.483 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:17.486 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:17.486 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:17.486 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:17.486 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:17.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:17.487 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:17.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:17.487 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:17.490 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:17.490 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:17.490 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:17.490 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:17.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:17.491 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:17.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:17.491 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.496 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:01:17.496 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:01:17.496 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:17.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:17.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:17.501 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:17.975 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:18.029 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:18.032 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:18.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:18.034 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:18.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:18.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:01:18.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:01:18.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:18.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:18.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:18.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:01:18.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:01:18.447 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:18.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:18.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:18.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:18.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:18.918 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:19.392 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:19.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:19.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:19.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:19.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:19.864 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:20.336 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:20.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:20.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:20.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:20.503 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:20.807 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:21.280 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:21.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:21.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:21.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:21.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:21.753 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:01:22.225 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:01:22.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:22.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:22.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:22.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:22.696 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:01:23.169 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:01:23.639 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:01:24.112 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:01:24.584 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:01:25.055 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:01:25.529 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:01:26.001 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:01:26.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:26.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:01:26.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:26.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:26.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:26.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:26.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:26.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:26.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:26.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:26.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:26.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:26.080 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:26.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:26.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:26.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:26.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:26.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:26.080 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:31.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:31.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:31.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:31.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:31.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:31.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:31.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:31.095 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:31.095 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:31.095 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:31.095 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:31.098 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:31.098 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:31.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:31.098 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:31.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:31.099 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:31.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:31.099 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:31.101 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:31.101 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:31.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:31.101 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:31.101 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:31.101 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:31.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:31.101 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:31.103 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:31.103 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:31.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:31.103 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:31.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:31.103 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:31.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:31.104 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:01:31.107 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:01:31.107 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:31.107 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:31.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:31.111 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:31.589 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:31.620 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:31.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:31.621 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:31.622 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:31.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:31.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:01:31.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:01:31.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:31.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:31.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:31.623 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:01:31.623 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:01:32.060 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:32.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:32.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:32.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:32.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:32.532 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:33.006 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:33.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:33.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:33.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:33.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:33.478 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:33.950 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:34.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:34.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:34.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:34.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:34.424 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:34.896 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:35.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:35.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:35.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:35.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:35.368 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:01:35.839 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:01:36.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:36.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:36.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:36.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:36.313 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:01:36.785 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:01:37.257 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:01:37.728 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:01:38.201 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:01:38.674 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:01:39.146 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:01:39.617 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:01:39.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:39.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:01:39.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:39.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:39.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:39.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:39.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:39.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:39.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:39.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:39.643 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:39.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:39.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:39.643 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:39.643 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:39.643 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:39.643 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:39.643 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:39.643 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1844 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:01:44.649 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:44.649 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:44.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:44.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:44.650 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:44.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:44.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:44.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:44.660 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:44.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:44.661 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:44.666 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:44.666 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:44.666 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:44.666 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:44.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:44.667 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:44.668 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:44.668 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:44.670 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:44.670 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:44.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:44.671 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:44.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:44.671 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:44.671 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:44.671 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:44.673 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:44.673 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:44.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:44.673 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:44.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:44.673 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:44.674 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:44.674 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.677 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:01:44.677 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:01:44.677 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:44.677 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:44.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:44.682 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:45.160 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:45.206 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:45.208 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:45.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:45.210 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:45.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:45.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:01:45.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:01:45.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:45.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:45.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:45.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:01:45.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:01:45.632 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:45.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:45.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:45.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:45.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:46.104 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:01:46.578 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:01:46.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:46.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:46.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:46.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:47.050 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:01:47.522 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:01:47.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:47.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:47.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:47.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:47.993 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:01:48.467 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:01:48.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:48.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:48.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:48.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:48.939 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:01:49.411 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:01:49.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:49.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:49.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:49.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:49.882 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:01:50.355 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:01:50.828 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:01:51.300 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:01:51.771 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:01:52.244 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:01:52.716 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:01:53.188 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:01:53.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:53.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:01:53.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:53.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:53.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:53.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:53.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:53.264 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:53.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:53.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:53.264 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:53.264 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:53.264 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:01:58.273 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:01:58.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:01:58.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:58.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:58.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:58.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:58.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:01:58.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:58.286 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:58.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:01:58.286 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:01:58.289 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:01:58.289 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:01:58.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:58.289 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:58.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:01:58.290 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:01:58.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:01:58.290 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:01:58.291 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:01:58.291 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:01:58.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:58.292 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:58.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:01:58.292 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:01:58.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:01:58.292 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:01:58.293 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:01:58.293 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:01:58.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:58.294 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:01:58.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:01:58.294 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:01:58.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:01:58.294 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.296 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:01:58.296 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:01:58.296 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:01:58.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:01:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:01:58.301 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:01:58.778 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:01:58.824 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:01:58.826 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:01:58.828 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:01:58.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:01:58.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:01:58.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:01:58.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:01:58.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:01:58.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:01:58.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:01:58.831 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:01:58.831 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:01:59.249 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:01:59.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:01:59.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:01:59.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:01:59.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:01:59.721 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:02:00.192 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:02:00.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:00.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:00.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:00.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:00.665 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:02:01.138 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:02:01.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:01.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:01.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:01.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:01.610 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:02:02.081 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:02:02.302 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:02.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:02.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:02.303 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:02.552 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:02:03.025 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:02:03.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:03.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:03.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:03.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:03.497 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:02:03.969 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:02:04.440 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:02:04.913 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:02:05.386 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:02:05.856 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:02:06.328 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:02:06.799 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:02:06.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:06.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:02:06.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:06.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:06.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:06.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:06.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:06.886 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:06.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:06.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:06.887 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:06.887 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:02:06.887 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:06.887 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:06.888 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:06.888 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:06.888 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:06.888 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:06.888 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:11.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:11.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:02:11.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:11.889 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:11.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:11.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:11.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:11.897 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:11.897 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:11.898 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:11.898 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:02:11.902 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:02:11.902 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:02:11.903 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:11.903 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:11.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:11.904 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:02:11.904 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:11.904 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:02:11.906 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:02:11.907 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:02:11.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:11.907 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:11.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:11.908 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:02:11.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:11.908 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:02:11.910 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:02:11.910 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:02:11.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:11.910 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:11.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:11.910 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:02:11.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:11.910 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:02:11.914 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:02:11.914 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:02:11.914 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:11.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:11.919 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:02:12.396 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:02:12.442 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:02:12.445 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:02:12.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:02:12.447 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:02:12.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:12.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:02:12.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:02:12.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:02:12.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:02:12.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:02:12.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:02:12.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:02:12.868 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:02:12.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:12.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:12.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:12.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:13.339 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:02:13.811 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:02:13.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:13.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:13.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:13.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:14.284 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:02:14.756 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:02:14.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:14.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:14.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:14.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:15.228 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:02:15.700 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:02:15.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:15.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:15.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:15.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:16.173 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:02:16.645 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:02:16.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:16.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:16.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:16.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:17.118 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:02:17.591 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:02:18.063 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:02:18.535 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:02:19.007 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:02:19.480 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:02:19.952 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:02:20.424 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:02:20.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:20.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:02:20.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:20.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:20.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:20.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:20.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:20.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:20.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:20.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:02:20.498 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:20.498 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:20.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:20.498 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:20.498 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:20.498 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:20.498 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:20.498 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:20.498 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:25.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:25.504 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:02:25.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:25.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:25.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:25.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:25.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:25.514 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:25.514 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:25.514 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:25.515 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:02:25.518 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:02:25.519 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:02:25.519 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:25.519 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:25.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:25.520 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:02:25.520 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:25.520 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:02:25.522 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:02:25.522 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:02:25.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:25.523 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:25.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:25.523 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:02:25.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:25.523 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:02:25.525 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:02:25.525 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:02:25.525 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:25.526 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:25.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:25.526 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:02:25.526 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:25.526 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:02:25.529 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:02:25.529 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:02:25.529 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:25.534 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:02:26.011 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:02:26.050 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:02:26.051 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:02:26.051 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:02:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:02:26.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:26.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:02:26.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:02:26.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:02:26.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:02:26.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:02:26.053 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:02:26.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:02:26.482 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:02:26.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:26.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:26.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:26.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:26.954 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:02:27.427 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:02:27.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:27.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:27.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:27.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:27.900 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:02:28.372 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:02:28.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:28.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:28.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:28.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:28.843 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:02:29.315 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:02:29.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:29.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:29.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:29.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:29.788 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:02:30.260 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:02:30.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:30.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:30.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:30.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:30.731 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:02:31.204 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:02:31.680 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:02:32.152 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:02:32.623 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:02:33.097 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:02:33.569 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:02:34.041 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:02:34.512 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:02:34.985 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:02:35.458 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:02:35.930 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:02:36.401 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:02:36.874 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:02:37.347 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:02:37.819 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:02:38.290 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:02:38.763 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:02:39.236 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:02:39.708 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:02:40.179 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:02:40.652 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:02:41.125 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:02:41.597 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:02:42.068 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:02:42.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:42.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:02:42.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:42.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:42.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:42.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:42.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:42.114 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:42.114 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:02:42.114 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:42.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:42.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:42.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:42.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3582 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:42.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3582 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:42.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3582 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:42.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3582 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:42.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3582 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:42.114 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3582 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:47.118 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:47.118 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:02:47.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:47.118 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:47.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:47.118 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:47.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:47.127 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:47.127 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:47.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:02:47.128 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:02:47.130 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:02:47.130 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:02:47.130 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:47.130 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:47.131 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:47.131 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:02:47.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:02:47.131 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:02:47.133 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:02:47.133 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:02:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:47.133 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:47.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:47.133 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:02:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:02:47.133 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:02:47.136 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:02:47.136 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:02:47.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:47.136 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:02:47.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:47.136 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:02:47.136 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:02:47.136 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:02:47.139 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:02:47.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:02:47.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:02:47.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:02:47.139 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:02:47.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:02:47.140 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:02:47.140 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:02:47.140 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:02:47.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:02:47.145 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:02:47.619 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:02:47.669 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:02:47.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:02:47.673 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:02:47.676 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:02:47.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:47.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:02:47.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:02:47.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:02:47.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:02:47.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:02:47.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:02:47.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:02:48.090 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:02:48.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:48.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:48.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:48.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:48.562 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:02:49.034 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:02:49.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:49.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:49.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:49.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:49.505 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:02:49.978 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:02:50.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:50.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:50.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:50.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:50.451 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:02:50.923 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:02:51.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:51.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:51.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:51.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:51.394 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:02:51.867 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:02:52.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:52.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:52.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:52.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:52.339 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:02:52.812 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:02:53.283 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:02:53.756 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:02:54.228 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:02:54.700 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:02:55.171 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:02:55.644 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:02:55.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:02:55.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:02:55.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:02:55.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:02:55.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:02:55.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:02:55.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:02:55.732 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:02:55.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:02:55.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:02:55.732 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:02:55.732 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:02:55.732 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:02:55.733 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:55.733 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:55.733 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:55.733 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:55.733 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:02:55.733 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:00.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:00.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:00.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:00.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:00.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:00.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:00.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:00.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:00.737 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:00.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:00.737 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:00.738 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:00.738 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:00.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:00.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:00.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:00.739 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:00.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:00.739 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:00.740 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:00.740 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:00.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:00.740 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:00.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:00.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:00.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:00.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:00.741 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:00.741 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:00.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:00.741 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:00.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:00.741 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:00.741 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:00.741 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.743 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:00.743 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:00.743 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:00.744 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:00.748 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:01.224 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:01.268 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:01.270 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:01.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:01.272 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:01.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:01.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:01.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:01.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:03:01.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:03:01.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:03:01.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:03:01.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:03:01.696 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:03:01.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:01.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:01.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:01.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:02.168 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:03:02.641 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:03:02.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:02.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:02.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:02.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:03.114 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:03:03.586 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:03:03.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:03.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:03.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:03.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:04.057 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:03:04.530 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:03:04.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:04.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:04.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:04.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:05.002 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:03:05.474 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:03:05.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:05.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:05.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:05.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:05.945 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:03:06.419 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:03:06.891 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:03:07.363 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:03:07.834 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:03:08.307 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:03:08.778 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:03:09.240 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:03:09.703 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:03:10.165 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:03:10.633 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:03:11.106 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:03:11.577 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:03:12.049 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:03:12.522 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:03:12.994 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:03:13.467 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:03:13.938 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:03:14.411 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:03:14.883 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:03:15.355 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:03:15.826 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:03:16.297 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:03:16.770 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:03:17.243 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:03:17.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:17.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:17.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:17.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:17.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:17.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:17.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:17.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:17.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:17.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:17.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:17.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:17.345 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:17.345 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:17.345 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:17.345 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:17.345 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:17.346 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:17.346 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:17.346 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:17.346 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3594 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:22.352 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:22.353 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:22.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:22.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:22.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:22.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:22.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:22.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:22.360 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:22.361 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:22.361 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:22.362 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:22.362 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:22.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:22.363 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:22.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:22.363 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:22.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:22.363 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:22.365 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:22.365 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:22.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:22.365 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:22.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:22.365 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:22.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:22.365 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:22.367 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:22.367 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:22.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:22.367 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:22.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:22.367 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:22.367 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:22.367 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:22.370 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:22.370 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:22.370 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:22.375 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:22.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:22.904 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:22.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:22.907 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:22.909 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:22.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:22.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:22.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:22.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:22.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:22.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:22.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:22.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:22.951 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:22.951 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:22.951 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:22.951 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:22.951 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:22.952 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:22.952 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:22.952 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:22.952 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:22.952 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:22.952 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:22.952 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:27.956 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:27.956 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:27.956 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:27.957 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:27.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:27.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:27.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:27.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:27.971 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:27.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:27.972 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:27.974 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:27.974 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:27.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:27.974 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:27.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:27.975 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:27.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:27.975 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:27.978 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:27.978 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:27.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:27.978 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:27.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:27.978 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:27.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:27.978 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:27.981 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:27.981 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:27.981 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:27.981 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:27.981 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:27.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:27.982 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:27.982 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:27.987 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:27.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:27.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:27.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.988 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:27.988 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:27.988 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:27.988 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:27.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:27.993 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:28.469 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:28.521 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:28.523 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:28.526 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:28.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:28.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:28.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:28.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:28.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:28.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:28.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:28.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:28.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:28.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:28.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:28.565 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:28.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:28.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:28.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:28.566 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:28.566 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:28.566 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:28.566 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:28.566 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:28.566 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:33.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:33.566 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:33.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:33.566 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:33.566 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:33.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:33.578 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:33.579 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:33.579 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:33.579 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:33.579 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:33.582 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:33.582 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:33.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:33.582 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:33.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:33.583 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:33.583 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:33.583 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:33.584 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:33.584 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:33.584 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:33.584 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:33.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:33.584 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:33.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:33.585 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:33.586 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:33.586 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:33.586 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:33.586 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:33.586 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:33.586 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:33.587 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:33.587 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:33.589 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:33.589 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:33.589 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:33.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:33.594 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:34.067 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:34.116 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:34.118 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:34.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:34.120 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:34.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:34.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:34.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:34.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:34.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:34.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:34.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:34.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:34.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:34.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:34.156 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:34.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:34.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:34.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:34.157 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:34.157 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:34.157 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:34.157 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:34.157 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:34.157 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:34.157 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:39.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:39.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:39.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:39.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:39.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:39.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:39.174 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:39.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:39.175 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:39.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:39.175 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:39.178 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:39.178 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:39.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:39.178 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:39.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:39.178 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:39.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:39.178 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:39.181 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:39.181 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:39.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:39.181 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:39.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:39.181 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:39.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:39.181 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:39.183 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:39.183 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:39.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:39.183 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:39.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:39.183 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:39.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:39.183 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:39.186 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:39.186 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:39.186 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:39.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:39.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:39.666 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:39.708 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:39.709 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:39.709 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:39.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:39.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:39.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:39.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:39.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:39.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:39.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:39.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:39.753 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:39.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:39.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:39.753 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:39.753 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:39.753 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:39.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:44.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:44.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:44.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:44.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:44.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:44.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:44.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:44.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:44.769 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:44.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:44.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:44.774 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:44.774 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:44.775 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:44.775 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:44.775 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:44.775 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:44.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:44.776 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:44.778 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:44.779 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:44.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:44.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:44.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:44.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:44.780 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:44.780 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:44.782 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:44.782 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:44.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:44.782 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:44.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:44.782 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:44.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:44.782 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:44.786 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:44.786 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:44.786 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:44.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:44.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:44.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:44.791 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:45.267 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:45.314 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:45.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:45.318 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:45.321 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:45.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:45.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:45.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:45.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:45.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:45.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:45.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:45.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:45.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:45.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:45.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:45.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:45.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:45.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:45.373 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:45.374 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:45.374 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:45.374 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:03:50.379 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:50.379 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:50.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:50.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:50.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:50.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:50.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:50.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:50.392 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:50.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:50.393 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:50.399 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:50.399 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:50.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:50.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:50.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:50.400 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:50.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:50.400 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:50.404 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:50.404 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:50.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:50.405 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:50.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:50.405 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:50.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:50.405 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:50.409 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:50.409 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:50.409 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:50.409 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:50.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:50.409 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:50.409 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:50.409 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:50.413 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:50.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:50.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:50.414 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:50.414 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:50.414 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:50.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:50.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:50.419 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:50.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:50.944 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:50.947 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:50.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:50.950 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:50.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:50.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:50.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:50.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:50.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:50.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:50.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:50.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:50.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:50.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:50.998 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:50.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:50.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:50.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:50.998 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:03:50.998 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:50.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:56.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:03:56.005 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:03:56.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:56.005 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:56.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:56.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:56.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:03:56.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:56.011 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:56.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:03:56.011 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:03:56.014 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:03:56.014 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:03:56.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:56.015 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:56.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:03:56.015 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:03:56.015 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:03:56.016 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:03:56.017 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:03:56.018 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:03:56.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:56.018 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:56.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:03:56.018 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:03:56.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:03:56.019 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:03:56.020 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:03:56.020 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:03:56.020 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:56.020 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:03:56.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:03:56.020 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:03:56.021 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:03:56.021 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:03:56.023 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:03:56.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:03:56.024 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:03:56.024 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:03:56.024 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:03:56.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:03:56.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:03:56.029 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:03:56.506 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:03:56.549 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:03:56.550 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:03:56.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:03:56.551 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:03:56.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:03:56.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:03:56.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:03:56.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:03:56.559 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:03:56.559 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:03:56.559 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:03:56.559 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:03:56.978 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:03:57.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:57.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:57.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:57.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:57.449 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:03:57.922 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:03:58.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:58.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:58.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:58.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:58.394 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:03:58.866 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:03:59.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:03:59.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:03:59.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:03:59.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:03:59.338 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:03:59.811 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:04:00.031 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:00.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:00.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:00.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:00.283 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:04:00.755 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:04:01.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:01.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:01.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:01.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:01.227 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:04:01.700 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:04:02.172 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:04:02.644 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:04:03.116 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:04:03.586 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:04:04.057 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:04:04.531 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:04:05.003 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:04:05.475 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:04:05.946 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:04:06.419 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:04:06.892 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:04:07.364 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:04:07.837 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:04:08.310 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:04:08.782 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:04:09.253 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:04:09.724 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:04:10.197 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:04:10.669 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:04:11.140 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:04:11.612 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:04:12.085 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:04:12.558 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:04:13.030 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:04:13.503 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:04:13.976 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:04:14.448 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:04:14.919 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:04:15.392 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:04:15.865 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:04:16.337 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:04:16.808 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:04:17.281 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:04:17.753 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:04:18.225 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:04:18.696 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:04:19.169 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:04:19.642 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:04:20.114 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:04:20.585 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:04:21.059 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:04:21.531 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:04:22.003 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:04:22.474 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:04:22.947 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:04:23.419 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:04:23.892 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:04:24.365 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:04:24.837 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:04:25.309 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:04:25.780 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:04:26.251 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:04:26.724 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:04:27.197 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:04:27.668 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:04:28.140 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:04:28.613 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:04:29.085 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:04:29.557 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:04:30.028 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:04:30.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:04:30.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:04:30.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:30.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:30.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:30.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:30.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:30.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:30.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:30.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:30.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:30.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:04:30.052 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:30.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:30.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:30.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:30.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7351 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:35.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:35.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:04:35.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:35.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:35.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:35.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:35.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:35.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:35.065 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:35.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:35.066 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:35.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:35.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:35.068 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:35.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:35.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:35.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:35.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:35.069 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:35.071 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:35.071 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:35.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:35.071 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:35.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:35.071 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:35.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:35.071 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:35.073 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:35.073 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:35.073 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:35.073 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:35.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:35.073 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:35.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:35.074 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.076 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:04:35.076 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:04:35.076 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:35.077 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:35.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:35.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:35.081 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:35.560 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:35.603 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:35.605 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:35.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:35.607 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:36.032 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:36.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:36.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:36.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:36.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:36.503 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:36.977 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:37.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:37.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:37.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:37.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:37.449 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:37.921 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:38.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:38.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:38.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:38.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:38.396 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:38.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:38.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:38.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:38.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:38.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:38.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:38.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:38.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:38.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:38.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:04:38.630 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:38.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:43.636 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:43.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:04:43.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:43.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:43.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:43.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:43.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:43.644 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:43.644 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:43.644 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:43.645 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:43.648 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:43.648 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:43.649 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:43.649 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:43.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:43.650 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:43.651 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:43.651 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:43.653 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:43.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:43.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:43.654 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:43.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:43.655 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:43.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:43.656 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:43.658 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:43.658 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:43.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:43.659 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:43.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:43.659 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:43.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:43.659 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:43.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:04:43.665 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:04:43.665 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:43.665 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:43.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:43.670 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:44.148 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:44.199 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:44.201 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:44.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:44.204 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:44.620 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:44.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:44.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:44.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:44.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:45.091 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:45.566 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:45.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:45.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:45.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:45.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:46.038 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:46.514 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:46.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:46.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:46.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:46.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:46.990 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:47.462 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:04:47.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:47.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:47.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:47.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:47.937 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:04:48.409 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:04:48.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:48.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:48.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:48.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:48.885 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:04:49.357 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:04:49.832 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:04:50.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:50.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:50.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:50.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:50.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:50.222 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:50.222 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:04:50.222 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:04:50.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:50.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:50.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:50.222 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:04:55.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:04:55.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:04:55.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:55.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:55.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:55.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:55.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:04:55.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:55.236 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:55.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:04:55.236 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:04:55.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:04:55.240 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:04:55.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:55.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:55.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:04:55.241 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:04:55.242 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:04:55.242 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:04:55.243 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:04:55.244 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:04:55.244 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:55.244 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:55.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:04:55.244 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:04:55.244 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:04:55.244 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:04:55.247 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:04:55.247 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:04:55.247 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:55.247 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:04:55.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:04:55.247 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:04:55.247 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:04:55.247 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:04:55.250 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:04:55.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:04:55.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:04:55.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:04:55.250 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:04:55.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:04:55.251 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:04:55.251 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:04:55.251 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:04:55.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:04:55.256 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:04:55.735 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:04:55.779 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:04:55.781 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:04:55.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:04:55.783 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:04:56.207 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:04:56.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:56.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:56.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:56.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:56.682 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:04:57.154 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:04:57.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:57.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:57.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:57.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:57.629 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:04:58.101 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:04:58.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:58.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:58.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:58.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:58.576 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:04:59.048 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:04:59.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:04:59.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:04:59.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:04:59.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:04:59.523 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:04:59.995 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:05:00.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:00.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:00.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:00.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:00.470 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:05:00.942 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:05:01.413 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:05:01.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:01.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:01.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:01.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:01.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:01.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:01.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:01.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:01.800 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:01.800 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:01.800 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:06.805 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:06.805 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:06.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:06.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:06.805 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:06.805 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:06.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:06.815 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:06.815 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:06.816 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:06.816 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:06.819 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:06.820 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:06.820 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:06.820 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:06.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:06.821 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:06.822 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:06.822 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:06.824 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:06.824 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:06.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:06.825 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:06.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:06.825 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:06.826 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:06.826 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:06.828 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:06.828 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:06.828 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:06.828 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:06.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:06.829 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:06.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:06.829 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:06.832 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:06.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:06.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:06.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:06.832 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:06.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:05:06.833 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:05:06.833 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:06.833 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:06.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:06.838 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:07.315 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:07.361 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:07.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:07.365 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:07.366 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:07.787 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:07.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:07.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:07.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:07.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:08.261 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:05:08.734 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:05:08.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:08.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:08.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:08.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:09.205 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:05:09.681 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:05:09.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:09.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:09.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:09.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:10.155 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:05:10.628 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:05:10.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:10.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:10.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:10.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:11.100 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:05:11.576 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:05:11.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:11.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:11.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:11.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:12.048 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:05:12.523 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:05:12.995 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:05:13.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:13.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:13.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:13.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:13.381 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:13.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:13.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:13.381 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:13.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:13.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:13.382 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:18.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:18.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:18.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:18.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:18.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:18.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:18.397 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:18.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:18.400 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:18.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:18.400 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:18.406 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:18.407 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:18.408 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:18.408 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:18.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:18.409 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:18.409 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:18.410 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:18.412 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:18.413 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:18.413 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:18.413 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:18.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:18.414 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:18.415 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:18.415 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:18.417 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:18.417 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:18.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:18.418 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:18.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:18.418 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:18.419 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:18.419 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:18.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:05:18.423 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:05:18.423 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:18.423 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:18.428 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:18.906 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:18.952 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:18.954 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:18.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:18.956 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:19.378 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:19.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:19.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:19.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:19.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:19.853 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:05:20.325 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:05:20.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:20.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:20.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:20.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:20.800 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:05:21.272 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:05:21.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:21.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:21.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:21.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:21.746 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:05:22.219 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:05:22.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:22.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:22.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:22.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:22.690 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:05:22.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:23.165 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:05:23.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:23.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:23.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:23.433 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:23.637 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:05:24.108 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:05:24.579 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:05:25.055 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:05:25.527 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:05:26.002 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:05:26.474 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:05:26.950 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:05:26.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:26.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:26.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:26.978 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:26.979 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:26.979 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:26.979 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:26.979 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:26.979 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:26.979 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:26.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:31.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:31.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:31.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:31.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:31.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:31.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:31.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:31.998 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:31.998 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:31.998 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:31.998 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:32.000 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:32.000 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:32.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:32.001 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:32.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:32.001 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:32.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:32.002 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:32.003 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:32.003 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:32.003 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:32.003 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:32.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:32.003 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:32.003 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:32.003 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:32.004 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:32.004 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:32.005 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:32.005 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:32.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:32.005 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:32.005 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:32.005 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:05:32.008 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:05:32.008 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:32.008 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:32.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:32.013 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:32.491 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:32.539 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:32.541 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:32.543 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:32.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:32.963 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:33.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:33.437 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:05:33.909 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:05:34.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:34.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:34.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:34.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:34.381 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:05:34.855 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:05:35.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:35.327 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:05:35.799 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:05:36.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:36.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:36.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:36.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:36.274 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:05:36.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:36.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:36.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:36.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:36.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:36.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:36.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:36.562 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:36.563 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:36.563 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:36.563 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=982 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=982 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:36.563 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=983 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:41.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:41.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:41.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:41.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:41.567 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:41.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:41.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:41.577 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:41.577 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:41.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:41.578 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:41.582 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:41.582 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:41.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:41.583 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:41.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:41.583 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:41.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:41.584 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:41.586 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:41.586 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:41.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:41.587 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:41.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:41.587 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:41.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:41.587 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:41.589 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:41.589 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:41.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:41.589 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:41.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:41.589 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:41.590 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:41.590 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:05:41.593 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:05:41.593 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:41.593 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:41.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:41.598 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:42.076 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:42.121 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:42.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:42.122 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:42.123 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:42.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:42.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:42.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:42.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:42.134 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:42.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:42.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:42.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:42.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:42.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:42.135 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:47.139 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:47.139 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:47.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:47.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:47.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:47.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:47.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:47.148 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:47.148 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:47.149 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:47.149 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:47.152 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:47.152 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:47.153 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:47.153 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:47.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:47.154 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:47.154 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:47.154 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:47.156 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:47.156 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:47.156 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:47.156 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:47.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:47.157 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:47.157 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:47.157 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:47.159 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:47.159 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:47.159 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:47.159 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:47.159 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:47.159 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:47.159 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:47.159 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:47.162 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:47.162 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:47.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:05:47.163 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:05:47.163 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:47.163 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:47.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:47.168 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:47.645 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:47.688 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:47.690 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:47.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:47.692 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:47.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:47.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:47.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:47.708 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:47.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:47.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:47.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:47.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:47.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:47.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:47.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:47.710 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:52.715 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:52.715 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:52.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:52.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:52.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:52.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:52.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:52.724 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:52.725 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:52.725 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:52.725 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:52.728 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:52.729 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:52.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:52.729 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:52.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:52.730 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:52.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:52.731 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:52.732 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:52.733 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:52.733 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:52.733 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:52.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:52.734 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:52.734 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:52.734 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:52.735 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:52.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:52.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:52.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:52.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:52.736 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:52.736 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:52.736 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.739 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:05:52.739 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:05:52.739 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:52.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:52.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:52.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:52.744 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:53.223 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:53.272 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:53.274 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:53.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:53.276 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:53.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:53.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:53.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:53.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:53.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:53.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:53.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:53.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:53.289 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:53.289 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:53.289 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:05:53.289 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:53.289 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:53.289 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:53.289 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:53.289 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:53.289 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:53.289 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:05:58.292 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:05:58.292 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:05:58.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:58.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:58.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:58.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:58.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:05:58.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:58.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:58.301 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:05:58.301 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:05:58.303 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:05:58.303 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:05:58.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:58.304 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:58.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:05:58.304 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:05:58.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:05:58.305 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:05:58.306 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:05:58.306 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:05:58.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:58.306 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:58.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:05:58.306 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:05:58.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:05:58.306 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:05:58.308 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:05:58.308 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:05:58.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:58.308 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:05:58.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:05:58.308 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:05:58.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:05:58.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:05:58.311 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:05:58.311 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:05:58.311 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:05:58.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:05:58.316 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:05:58.791 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:05:58.838 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:05:58.841 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:05:58.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:05:58.843 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:05:58.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:05:58.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:05:58.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:05:58.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:05:58.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:05:58.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:05:58.848 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:05:58.848 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:05:59.263 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:05:59.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:05:59.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:05:59.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:05:59.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:05:59.735 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:00.208 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:00.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:00.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:00.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:00.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:00.681 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:01.153 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:01.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:01.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:01.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:01.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:01.624 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:01.908 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:06:01.908 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:01.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:01.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:01.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:01.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:01.953 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:06:01.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:01.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:01.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:01.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:01.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:01.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:01.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:01.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:01.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:01.962 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:01.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:01.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:06.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:06.966 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:06.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:06.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:06.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:06.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:06.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:06.975 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:06.975 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:06.975 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:06.975 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:06.978 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:06.978 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:06.979 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:06.979 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:06.979 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:06.979 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:06.979 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:06.979 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:06.984 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:06.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:06.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:06.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:06.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:06.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:06.985 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:06.985 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:06.988 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:06.989 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:06.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:06.989 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:06.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:06.989 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:06.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:06.989 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:06.995 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:06.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:06.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:06.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:06.995 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:06.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.996 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:06:06.996 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:06:06.996 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:06.996 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:06.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:06.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:07.001 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:07.480 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:07.525 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:07.527 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:07.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:07.529 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:07.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:07.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:07.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:06:07.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:07.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:07.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:07.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:06:07.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:06:07.952 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:08.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:08.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:08.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:08.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:08.423 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:08.896 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:09.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:09.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:09.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:09.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:09.369 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:09.841 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:10.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:10.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:10.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:10.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:10.312 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:10.595 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:06:10.595 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:10.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:10.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:10.786 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:11.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:11.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:11.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:11.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:11.258 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:11.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:11.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:11.270 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:06:11.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:11.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:11.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:11.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:11.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:11.282 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:11.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:11.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:11.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:11.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:11.283 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:11.283 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:11.283 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=925 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:16.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:16.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:16.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:16.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:16.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:16.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:16.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:16.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:16.304 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:16.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:16.305 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:16.309 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:16.309 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:16.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:16.310 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:16.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:16.310 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:16.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:16.310 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:16.313 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:16.314 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:16.314 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:16.314 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:16.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:16.314 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:16.314 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:16.314 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:16.316 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:16.316 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:16.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:16.316 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:16.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:16.316 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:16.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:16.317 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:06:16.319 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:06:16.319 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:16.319 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:16.324 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:16.802 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:16.846 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:16.848 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:16.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:16.850 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:16.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:16.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:16.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:06:16.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:16.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:16.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:16.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:06:16.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:06:17.274 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:17.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:17.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:17.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:17.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:17.745 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:18.219 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:18.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:18.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:18.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:18.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:18.691 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:19.163 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:19.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:19.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:19.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:19.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:19.634 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:19.918 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:06:19.918 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:19.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:19.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:20.105 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:20.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:20.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:20.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:20.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:20.578 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:21.051 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:06:21.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:21.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:21.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:21.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:21.523 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:06:21.994 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:06:22.467 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:06:22.939 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:06:23.411 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:06:23.882 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:06:24.355 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:06:24.828 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:06:24.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:24.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:24.920 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:06:24.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:24.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:24.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:24.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:24.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:24.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:24.933 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:24.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:24.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:24.933 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:24.933 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:24.933 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:24.933 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:24.933 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:29.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:29.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:29.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:29.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:29.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:29.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:29.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:29.946 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:29.946 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:29.947 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:29.947 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:29.949 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:29.949 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:29.950 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:29.950 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:29.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:29.950 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:29.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:29.951 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:29.953 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:29.953 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:29.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:29.953 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:29.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:29.954 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:29.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:29.954 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:29.957 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:29.957 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:29.958 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:29.958 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:29.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:29.958 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:29.958 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:29.958 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:29.963 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:29.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:29.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:29.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:29.963 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:29.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:06:29.964 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:06:29.964 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:29.964 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:29.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:29.969 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:30.446 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:30.498 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:30.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:30.502 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:30.505 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:30.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:30.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:30.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:06:30.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:30.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:30.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:30.516 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:06:30.516 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:06:30.917 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:30.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:30.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:30.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:30.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:31.389 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:31.862 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:31.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:31.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:31.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:31.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:32.335 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:32.807 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:32.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:32.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:32.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:32.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:33.278 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:33.561 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:06:33.561 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:33.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:33.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:33.751 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:33.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:33.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:33.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:33.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:34.224 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:34.696 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:06:34.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:34.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:34.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:34.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:35.169 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:06:35.642 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:06:36.114 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:06:36.587 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:06:37.060 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:06:37.532 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:06:38.006 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:06:38.478 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:06:38.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:38.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:38.565 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:06:38.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:38.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:38.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:38.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:38.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:38.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:38.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:38.583 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:38.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:38.583 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:38.583 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:38.583 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:43.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:43.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:43.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:43.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:43.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:43.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:43.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:43.598 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:43.598 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:43.598 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:43.598 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:43.601 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:43.601 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:43.601 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:43.601 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:43.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:43.602 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:43.602 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:43.602 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:43.604 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:43.604 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:43.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:43.604 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:43.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:43.604 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:43.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:43.604 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:43.606 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:43.606 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:43.606 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:43.606 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:43.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:43.606 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:43.606 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:43.606 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:06:43.609 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:06:43.609 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:43.609 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:43.614 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:44.092 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:44.133 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:44.136 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:44.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:44.138 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:44.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:44.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:44.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:06:44.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:44.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:44.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:44.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:06:44.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:06:44.565 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:44.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:44.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:44.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:44.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:45.036 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:45.510 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:45.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:45.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:45.613 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:45.613 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:45.982 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:06:46.454 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:06:46.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:46.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:46.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:46.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:46.928 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:06:47.208 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:06:47.208 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:47.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:47.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:47.400 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:06:47.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:47.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:47.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:47.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:47.872 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:06:48.345 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:06:48.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:48.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:48.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:48.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:48.818 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:06:49.290 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:06:49.761 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:06:50.234 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:06:50.707 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:06:51.179 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:06:51.650 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:06:52.123 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:06:52.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:52.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:52.211 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:06:52.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:52.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:52.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:52.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:52.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:52.231 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:52.231 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:52.231 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:52.231 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:06:52.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:52.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:52.231 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:52.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:52.231 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:06:57.238 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:06:57.238 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:06:57.238 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:57.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:57.239 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:57.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:57.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:06:57.249 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:57.249 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.249 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:06:57.250 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:06:57.253 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:06:57.254 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:06:57.254 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:57.254 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.254 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:06:57.255 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.255 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:06:57.255 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:06:57.257 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:06:57.258 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:06:57.258 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:57.258 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.258 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:06:57.258 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:06:57.259 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:06:57.260 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:06:57.261 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:06:57.261 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:57.261 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:06:57.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:06:57.261 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.261 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:06:57.261 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:06:57.264 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:06:57.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:06:57.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:06:57.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:06:57.264 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:06:57.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:06:57.265 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:06:57.265 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:06:57.265 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:06:57.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:06:57.269 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:06:57.746 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:06:57.787 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:06:57.789 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:06:57.791 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:06:57.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:06:57.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:06:57.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:06:57.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:06:57.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:57.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:06:57.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:06:57.800 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:06:57.800 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:06:57.837 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:06:57.837 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:06:57.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:57.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:06:58.218 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:06:58.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:58.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:58.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:58.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:58.690 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:06:59.163 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:06:59.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:06:59.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:06:59.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:06:59.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:06:59.635 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:00.107 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:00.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:00.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:00.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:00.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:00.580 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:01.053 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:07:01.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:01.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:01.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:01.271 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:01.524 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:07:01.996 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:07:02.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:02.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:02.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:02.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:02.470 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:07:02.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:02.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:02.839 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:07:02.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:02.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:02.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:02.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:02.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:02.853 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:02.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:02.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:02.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:02.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:02.854 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:02.854 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1208 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:02.854 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1208 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:02.854 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1208 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:02.854 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1208 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:02.854 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1208 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:07.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:07.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:07.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:07.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:07.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:07.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:07.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:07.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:07.872 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:07.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:07.872 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:07.874 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:07.874 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:07.875 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:07.875 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:07.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:07.875 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:07.875 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:07.875 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:07.876 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:07.876 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:07.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:07.876 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:07.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:07.877 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:07.877 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:07.877 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:07.878 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:07.878 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:07.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:07.878 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:07.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:07.878 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:07.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:07.878 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.880 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:07:07.880 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:07:07.880 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:07.881 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:07.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:07.885 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:08.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:08.405 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:08.407 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:08.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:08.410 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:08.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:08.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:08.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:07:08.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:08.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:08.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:08.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:07:08.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:07:08.833 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:07:08.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:08.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:08.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:08.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:09.304 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:07:09.777 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:07:09.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:09.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:09.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:09.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:10.250 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:10.722 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:10.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:10.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:10.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:10.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:11.193 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:11.476 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:07:11.477 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:07:11.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:11.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:11.666 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:07:11.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:11.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:11.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:11.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:12.138 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:07:12.610 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:07:12.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:12.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:12.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:12.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:13.082 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:07:13.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:13.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:13.478 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:07:13.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:13.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:13.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:13.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:13.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:13.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:13.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:13.491 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:13.491 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:13.491 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:13.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:13.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:13.491 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1213 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:13.491 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1213 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:13.491 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1213 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:13.491 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1213 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:13.491 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1213 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:13.491 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1213 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:18.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:18.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:18.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:18.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:18.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:18.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:18.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:18.505 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:18.505 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:18.506 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:18.506 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:18.509 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:18.509 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:18.509 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:18.509 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:18.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:18.509 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:18.509 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:18.509 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:18.511 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:18.512 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:18.512 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:18.512 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:18.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:18.512 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:18.512 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:18.512 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:18.514 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:18.514 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:18.514 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:18.514 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:18.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:18.514 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:18.514 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:18.514 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:18.516 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:18.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:18.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:18.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:18.516 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:18.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:18.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:07:18.517 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:07:18.517 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:18.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:18.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:18.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:18.521 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:18.998 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:19.037 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:19.041 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:19.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:19.043 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:19.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:19.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:19.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:07:19.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:19.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:19.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:19.053 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:07:19.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:07:19.466 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:07:19.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:19.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:19.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:19.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:19.937 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:07:20.411 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:07:20.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:20.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:20.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:20.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:20.883 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:21.355 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:21.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:21.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:21.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:21.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:21.826 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:22.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:22.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:22.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:22.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:22.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:22.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:22.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:22.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:22.148 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:22.148 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:22.148 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:22.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:22.149 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:22.149 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:22.149 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:22.149 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:22.149 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:22.149 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:22.149 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:22.149 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:27.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:27.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:27.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:27.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:27.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:27.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:27.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:27.168 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:27.168 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:27.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:27.169 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:27.174 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:27.175 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:27.175 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:27.175 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:27.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:27.175 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:27.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:27.176 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:27.180 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:27.180 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:27.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:27.180 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:27.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:27.181 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:27.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:27.181 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:27.184 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:27.184 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:27.184 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:27.184 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:27.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:27.185 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:27.185 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:27.185 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.189 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:07:27.189 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:07:27.189 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:27.189 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:27.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:27.194 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:27.672 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:27.719 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:27.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:27.723 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:27.727 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:27.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:27.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:27.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:07:27.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:27.737 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:27.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:27.737 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:07:27.737 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:07:28.144 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:07:28.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:28.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:28.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:28.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:28.616 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:07:29.089 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:07:29.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:29.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:29.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:29.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:29.562 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:30.034 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:30.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:30.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:30.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:30.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:30.505 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:30.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:30.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:30.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:30.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:30.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:30.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:30.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:30.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:30.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:30.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:30.830 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:30.830 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:30.830 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:30.830 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:30.830 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:35.833 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:35.833 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:35.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:35.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:35.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:35.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:35.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:35.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:35.842 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:35.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:35.843 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:35.845 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:35.845 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:35.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:35.846 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:35.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:35.846 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:35.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:35.847 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:35.848 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:35.848 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:35.848 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:35.848 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:35.848 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:35.848 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:35.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:35.849 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:35.850 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:35.850 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:35.850 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:35.850 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:35.850 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:35.850 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:35.850 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:35.850 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:07:35.853 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:07:35.853 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:35.853 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:35.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:35.858 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:36.335 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:36.378 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:36.380 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:36.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:36.383 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:36.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:36.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:36.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:07:36.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:36.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:36.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:36.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:07:36.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:07:36.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:36.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:36.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:36.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:36.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:36.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:36.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:36.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:36.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:36.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:36.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:36.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:36.659 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:36.659 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:36.659 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:36.659 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:36.659 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:36.659 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:36.659 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:07:41.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:41.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:41.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:41.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:41.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:41.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:41.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:41.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:41.684 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:41.685 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:41.685 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:41.687 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:41.687 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:41.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:41.688 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:41.688 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:41.688 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:41.689 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:41.689 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:41.690 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:41.690 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:41.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:41.690 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:41.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:41.690 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:41.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:41.690 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:41.692 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:41.692 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:41.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:41.692 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:41.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:41.692 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:41.693 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:41.693 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:07:41.695 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:07:41.695 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:41.695 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:41.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:41.700 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:42.175 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:42.225 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:42.228 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:42.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:42.230 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:42.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:42.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:42.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:07:42.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:42.241 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:42.241 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:42.241 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:07:42.241 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:07:42.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:42.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:42.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:42.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:42.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:42.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:42.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:42.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:42.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:42.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:42.452 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:07:42.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:42.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:47.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:47.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:47.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:47.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:47.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:47.458 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:47.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:47.467 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:47.467 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:47.468 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:07:47.468 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:07:47.472 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:07:47.472 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:07:47.472 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:47.473 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:47.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:47.473 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:07:47.474 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:07:47.474 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:07:47.477 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:07:47.477 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:07:47.478 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:47.478 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:47.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:47.478 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:07:47.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:07:47.479 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:07:47.480 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:07:47.481 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:07:47.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:47.481 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:07:47.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:47.481 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:07:47.482 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:07:47.482 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:07:47.484 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:07:47.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:07:47.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:07:47.485 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:07:47.485 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:07:47.485 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:07:47.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:07:47.490 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:07:47.966 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:07:48.014 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:07:48.016 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:07:48.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:07:48.020 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:07:48.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:48.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:48.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:07:48.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:07:48.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:07:48.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:07:48.025 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:07:48.025 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:07:48.439 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:07:48.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:48.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:48.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:48.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:48.910 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:07:49.383 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:07:49.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:49.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:49.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:49.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:49.856 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:07:50.328 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:07:50.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:50.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:50.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:50.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:50.799 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:07:51.269 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:07:51.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:51.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:51.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:51.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:51.743 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:07:52.215 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:07:52.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:52.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:52.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:52.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:52.688 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:07:53.161 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:07:53.634 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:07:54.106 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:07:54.577 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:07:55.048 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:07:55.521 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:07:55.993 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:07:56.465 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:07:56.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:07:56.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:07:56.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:07:56.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:07:56.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:07:56.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:07:56.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:07:56.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:07:56.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:07:56.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:07:56.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:07:56.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:07:56.840 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:01.847 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:01.847 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:01.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:01.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:01.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:01.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:01.855 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:01.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:01.856 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:01.856 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:01.859 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:01.859 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:01.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:01.859 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:01.859 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:01.860 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:01.861 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:01.862 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:01.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:01.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:01.862 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:01.863 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:01.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:01.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:01.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:01.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:01.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:01.864 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:01.864 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:08:01.867 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:08:01.867 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:01.867 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:01.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:01.872 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:02.350 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:02.395 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:02.397 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:02.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:02.399 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:02.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:08:02.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:08:02.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:08:02.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:02.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:08:02.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:08:02.408 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:08:02.408 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:08:02.822 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:02.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:02.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:02.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:02.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:03.293 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:03.767 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:03.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:03.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:03.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:03.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:04.239 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:04.712 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:08:04.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:04.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:04.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:04.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:05.185 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:08:05.657 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:08:05.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:05.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:05.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:05.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:06.130 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:08:06.603 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:08:06.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:06.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:06.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:06.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:07.076 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:08:07.548 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:08:08.019 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:08:08.490 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:08:08.963 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:08:09.435 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:08:09.907 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:08:10.378 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:08:10.852 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:08:11.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:08:11.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:08:11.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:11.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:11.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:11.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:11.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:11.206 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:11.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:11.206 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:11.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:11.206 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:11.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:16.210 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:16.210 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:16.210 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:16.210 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:16.210 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:16.210 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:16.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:16.223 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:16.223 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.223 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:16.223 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:16.225 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:16.225 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:16.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:16.226 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.226 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:16.226 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.226 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:16.226 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:16.227 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:16.227 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:16.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:16.227 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:16.227 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:16.227 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:16.229 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:16.229 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:16.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:16.229 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:16.229 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:16.229 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:16.229 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:08:16.231 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:08:16.231 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:16.231 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:16.236 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:16.713 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:16.755 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:16.757 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:16.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:16.759 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:16.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:08:16.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:08:16.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:08:16.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:16.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:08:16.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:08:16.769 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:08:16.769 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:08:17.185 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:17.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:17.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:17.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:17.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:17.657 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:18.130 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:18.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:18.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:18.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:18.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:18.602 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:19.074 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:08:19.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:19.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:19.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:19.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:19.545 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:08:19.828 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:08:19.829 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-01-29 03:08:19.829 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:19.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:19.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:08:20.018 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:08:20.239 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:20.239 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:20.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:20.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:20.491 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:08:20.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:08:20.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:08:20.878 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:08:20.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:20.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:20.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:20.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:20.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:20.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:20.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:20.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:20.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:20.887 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:20.887 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:20.887 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:25.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:25.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:25.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:25.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:25.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:25.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:25.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:25.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:25.911 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:25.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:25.911 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:25.912 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:25.912 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:25.912 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:25.912 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:25.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:25.913 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:25.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:25.913 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:25.916 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:25.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:25.917 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:25.917 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:25.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:25.917 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:25.917 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:25.917 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:25.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:25.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:25.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:25.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:25.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:25.921 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:25.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:25.921 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:25.924 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:08:25.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:08:25.925 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:25.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:25.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:25.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:25.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:26.406 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:26.453 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:26.456 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:26.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:26.460 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:26.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:26.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:26.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:26.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:26.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:26.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:26.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:26.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:26.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:26.614 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:26.614 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:31.617 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:31.617 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:31.617 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:31.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:31.617 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:31.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:31.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:31.626 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:31.626 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:31.626 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:31.626 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:31.629 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:31.630 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:31.630 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:31.630 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:31.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:31.630 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:31.631 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:31.631 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:31.632 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:31.632 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:31.633 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:31.633 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:31.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:31.633 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:31.633 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:31.633 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:31.634 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:31.635 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:31.635 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:31.635 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:31.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:31.635 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:31.635 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:31.635 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:08:31.638 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:08:31.638 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:31.638 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:31.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:31.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:31.643 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:32.117 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:32.170 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:32.173 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:32.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:32.173 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:32.586 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:32.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:32.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:32.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:32.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:33.055 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:33.530 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:33.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:33.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:33.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:33.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:34.002 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:34.473 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:08:34.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:34.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:34.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:34.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:34.948 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:08:35.420 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:08:35.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:35.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:35.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:35.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:35.892 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:08:36.362 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:08:36.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:36.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:36.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:36.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:36.838 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:08:37.309 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:08:37.785 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:08:38.257 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:08:38.728 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:08:39.201 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:08:39.673 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:08:40.145 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:08:40.611 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:08:41.074 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:08:41.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:41.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:41.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:41.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:41.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:41.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:41.194 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:41.194 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:41.194 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:41.194 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:41.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:41.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:46.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:46.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:46.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:46.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:46.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:46.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:46.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:46.208 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:46.208 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:46.209 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:08:46.209 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:08:46.212 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:08:46.212 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:08:46.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:46.212 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:46.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:46.212 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:08:46.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:08:46.213 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:08:46.215 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:08:46.215 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:08:46.215 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:46.215 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:46.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:46.216 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:08:46.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:08:46.216 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:08:46.218 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:08:46.218 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:08:46.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:46.218 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:08:46.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:46.219 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:08:46.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:08:46.219 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:08:46.222 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:08:46.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:08:46.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:08:46.223 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:08:46.223 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:08:46.223 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:08:46.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:08:46.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:08:46.228 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:08:46.703 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:08:46.751 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:08:46.753 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:08:46.754 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:08:46.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:47.174 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:08:47.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:47.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:47.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:47.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:47.645 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:08:48.117 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:08:48.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:48.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:48.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:48.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:48.592 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:08:49.064 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:08:49.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:49.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:49.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:49.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:49.539 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:08:50.008 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:08:50.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:50.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:50.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:50.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:50.472 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:08:50.938 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:08:51.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:51.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:51.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:51.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:51.410 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:08:51.883 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:08:52.356 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:08:52.828 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:08:53.302 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:08:53.774 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:08:54.245 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:08:54.717 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:08:55.183 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:08:55.646 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:08:55.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:08:55.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:08:55.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:08:55.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:08:55.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:08:55.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:08:55.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:08:55.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:08:55.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:08:55.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:08:55.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:08:55.790 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:08:55.790 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2073 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:00.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:00.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:00.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:00.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:00.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:00.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:00.804 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:00.805 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:00.805 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:00.805 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:00.805 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:00.809 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:00.810 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:00.810 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:00.810 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:00.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:00.810 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:00.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:00.811 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:00.814 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:00.814 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:00.814 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:00.814 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:00.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:00.814 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:00.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:00.815 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:00.818 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:00.818 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:00.818 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:00.818 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:00.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:00.819 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:00.819 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:00.819 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:00.823 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:00.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:00.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:00.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:00.823 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:00.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:00.824 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:00.824 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:00.824 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:00.829 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:01.306 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:01.348 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:01.350 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:01.352 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:01.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:01.777 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:01.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:01.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:01.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:01.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:02.246 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:02.710 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:02.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:02.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:02.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:02.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:03.173 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:03.636 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:03.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:03.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:03.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:03.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:04.104 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:09:04.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:04.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:04.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:04.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:04.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:04.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:04.386 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:04.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:04.386 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:09.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:09.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:09.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:09.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:09.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:09.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:09.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:09.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:09.391 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:09.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:09.391 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:09.392 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:09.392 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:09.392 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:09.392 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:09.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:09.393 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:09.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:09.393 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:09.394 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:09.394 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:09.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:09.394 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:09.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:09.394 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:09.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:09.394 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:09.395 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:09.395 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:09.395 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:09.395 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:09.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:09.395 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:09.395 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:09.395 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:09.397 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:09.397 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:09.397 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:09.402 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:09.871 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:09.909 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:09.910 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:09.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:09.911 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:09.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:09.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:09.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:09:09.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:09.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:09.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:09.925 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:09:09.925 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:09:09.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:09.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:09.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:09.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:09.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:10.338 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:10.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:10.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:10.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:10.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:10.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:10.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:10.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:10.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:10.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:10.361 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:10.361 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:10.361 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:10.361 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:10.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:10.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:10.361 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:10.361 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:10.361 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:10.361 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:10.361 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:10.361 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:15.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:15.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:15.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:15.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:15.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:15.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:15.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:15.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:15.375 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:15.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:15.375 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:15.377 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:15.377 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:15.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:15.377 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:15.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:15.377 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:15.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:15.377 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:15.378 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:15.378 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:15.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:15.378 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:15.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:15.378 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:15.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:15.378 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:15.380 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:15.380 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:15.380 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:15.380 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:15.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:15.380 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:15.380 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:15.380 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:15.382 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:15.382 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:15.382 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:15.387 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:15.858 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:15.896 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:15.897 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:15.897 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:15.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:15.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:15.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:15.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:15.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:15.908 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:15.908 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:15.908 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:15.908 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:15.908 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:15.908 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:15.909 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:20.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:20.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:20.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:20.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:20.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:20.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:20.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:20.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:20.915 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:20.915 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:20.915 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:20.916 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:20.916 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:20.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:20.916 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:20.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:20.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:20.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:20.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:20.917 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:20.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:20.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:20.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:20.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:20.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:20.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:20.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:20.919 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:20.919 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:20.919 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:20.919 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:20.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:20.919 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:20.919 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:20.919 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:20.921 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:20.921 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:20.921 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:20.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:20.926 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:21.392 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:21.437 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:21.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:21.439 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:21.440 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:21.856 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:21.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:21.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:21.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:21.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:22.320 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:22.785 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:22.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:22.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:22.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:22.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:23.249 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:23.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:23.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:23.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:23.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:23.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:23.451 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:23.451 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:23.451 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:23.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:23.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:23.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:23.451 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=556 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:23.451 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=556 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:23.451 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=556 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:23.451 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=556 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:23.452 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=556 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:23.452 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=556 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:28.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:28.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:28.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:28.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:28.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:28.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:28.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:28.455 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:28.455 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:28.456 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:28.456 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:28.456 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:28.457 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:28.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:28.457 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:28.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:28.457 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:28.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:28.457 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:28.458 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:28.458 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:28.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:28.458 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:28.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:28.458 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:28.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:28.458 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:28.459 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:28.459 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:28.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:28.459 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:28.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:28.459 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:28.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:28.459 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:28.461 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:28.461 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:28.461 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:28.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:28.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:28.932 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:28.976 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:28.976 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:28.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:28.977 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:28.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:28.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:28.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:09:28.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:28.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:28.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:28.978 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:09:28.978 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:09:29.395 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:29.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:29.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:29.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:29.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:29.858 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:30.327 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:30.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:30.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:30.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:30.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:30.796 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:31.267 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:31.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:31.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:31.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:31.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:31.733 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:09:31.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:31.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:31.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:31.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:31.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:31.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:31.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:31.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:31.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:31.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:31.747 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:31.747 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:31.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:36.751 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:36.751 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:36.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:36.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:36.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:36.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:36.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:36.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:36.759 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:36.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:36.759 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:36.761 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:36.761 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:36.761 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:36.761 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:36.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:36.761 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:36.761 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:36.761 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:36.762 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:36.762 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:36.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:36.762 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:36.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:36.763 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:36.763 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:36.763 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:36.764 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:36.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:36.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:36.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:36.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:36.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:36.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:36.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:36.766 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:36.766 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:36.766 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:36.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:36.771 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:37.237 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:37.277 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:37.278 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:37.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:37.278 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:37.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:37.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:37.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:09:37.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:37.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:37.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:37.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:09:37.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:09:37.703 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:37.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:37.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:37.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:37.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:38.171 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:38.639 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:38.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:38.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:38.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:38.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:39.101 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:39.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:39.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:39.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:39.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:39.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:39.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:39.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:39.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:39.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:39.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:39.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:39.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:39.355 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:39.355 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=567 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:39.355 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=567 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:39.355 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=567 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:39.355 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=567 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:39.355 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=567 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:44.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:44.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:44.358 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:44.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:44.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:44.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:44.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:44.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:44.366 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:44.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:44.367 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:44.370 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:44.370 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:44.371 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:44.371 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:44.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:44.372 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:44.372 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:44.372 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:44.374 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:44.374 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:44.375 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:44.375 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:44.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:44.375 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:44.375 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:44.375 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:44.377 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:44.377 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:44.377 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:44.377 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:44.377 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:44.377 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:44.377 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:44.377 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.380 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:44.380 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:44.380 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:44.380 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:44.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:44.385 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:44.864 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:44.904 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:44.906 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:44.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:44.909 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:44.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:44.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:44.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:09:44.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:44.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:44.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:44.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:09:44.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:09:45.337 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:45.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:45.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:45.384 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:45.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:45.808 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:46.281 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:46.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:46.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:46.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:46.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:46.753 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:47.225 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:09:47.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:47.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:47.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:47.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:47.696 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:09:47.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:47.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:47.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:47.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:47.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:47.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:47.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:47.722 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:47.722 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:47.722 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:47.722 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:47.722 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:47.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:52.729 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:52.729 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:52.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:52.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:52.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:52.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:52.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:52.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:52.739 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:52.739 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:09:52.739 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:09:52.742 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:09:52.743 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:09:52.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:52.743 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:52.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:52.744 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:09:52.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:09:52.744 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:09:52.746 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:09:52.746 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:09:52.746 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:52.746 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:52.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:52.746 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:09:52.746 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:09:52.746 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:09:52.748 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:09:52.748 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:09:52.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:52.748 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:09:52.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:52.748 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:09:52.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:09:52.748 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:09:52.751 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:09:52.751 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:09:52.751 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:09:52.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:09:52.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:09:52.756 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:09:53.232 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:09:53.276 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:09:53.278 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:09:53.281 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:09:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:09:53.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:53.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:53.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:09:53.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:09:53.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:09:53.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:09:53.289 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:09:53.289 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:09:53.705 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:09:53.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:53.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:53.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:53.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:54.176 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:09:54.649 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:09:54.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:54.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:54.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:54.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:55.121 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:09:55.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:09:55.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:09:55.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:09:55.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:09:55.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:09:55.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:09:55.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:09:55.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:09:55.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:09:55.380 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:09:55.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:09:55.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:09:55.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:09:55.380 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:55.380 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:55.380 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:55.380 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:55.380 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:09:55.380 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:00.387 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:00.387 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:00.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:00.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:00.387 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:00.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:00.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:00.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:00.396 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:00.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:00.396 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:00.399 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:00.400 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:00.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:00.400 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:00.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:00.401 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:00.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:00.402 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:00.403 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:00.404 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:00.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:00.404 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:00.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:00.404 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:00.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:00.404 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:00.407 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:00.407 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:00.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:00.407 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:00.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:00.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:00.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:00.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:00.410 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:00.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:00.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:00.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:00.411 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:00.411 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:00.411 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:00.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:00.416 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:00.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:00.935 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:00.938 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:00.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:00.940 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:00.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:00.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:00.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:10:00.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:10:00.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:10:00.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:10:00.950 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:10:00.950 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:10:01.366 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:10:01.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:01.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:01.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:01.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:01.838 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:10:02.311 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:10:02.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:02.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:02.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:02.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:02.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:10:03.255 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:10:03.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:03.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:03.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:03.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:03.727 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:10:04.200 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:10:04.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:04.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:04.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:04.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:04.672 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:10:04.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:04.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:04.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:04.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:04.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:04.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:04.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:04.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:04.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:04.702 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:04.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:04.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:04.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:04.702 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:04.702 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:04.702 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:04.702 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:04.702 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:04.702 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:09.707 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:09.707 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:09.707 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:09.707 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:09.707 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:09.707 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:09.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:09.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:09.717 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:09.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:09.717 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:09.722 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:09.722 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:09.722 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:09.722 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:09.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:09.723 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:09.723 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:09.723 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:09.726 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:09.727 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:09.727 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:09.727 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:09.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:09.727 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:09.727 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:09.727 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:09.730 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:09.730 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:09.730 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:09.730 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:09.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:09.730 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:09.730 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:09.730 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.734 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:09.734 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:09.734 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:09.734 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:09.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:09.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:09.739 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:10.218 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:10.262 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:10.264 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:10.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:10.267 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:10.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:10.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:10.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:10:10.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:10:10.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:10:10.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:10:10.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:10:10.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:10:10.690 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:10:10.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:10.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:10.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:10.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:11.161 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:10:11.635 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:10:11.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:11.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:11.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:11.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:12.106 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:10:12.578 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:10:12.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:12.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:12.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:12.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:13.049 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:10:13.523 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:10:13.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:13.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:13.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:13.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:13.995 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:10:14.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:14.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:14.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:14.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:14.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:14.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:14.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:14.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:14.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:14.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:14.261 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:14.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:14.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:14.261 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=977 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.261 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=977 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.261 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=977 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.261 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=977 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.261 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=977 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:14.261 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=977 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:19.265 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:19.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:19.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:19.265 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:19.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:19.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:19.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:19.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:19.268 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.269 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:19.269 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:19.269 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:19.270 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:19.270 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:19.270 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:19.270 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.270 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:19.270 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:19.271 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:19.271 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:19.271 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:19.271 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:19.271 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.271 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:19.271 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:19.272 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:19.272 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:19.272 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:19.272 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:19.272 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:19.272 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.272 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:19.272 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.274 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:19.274 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:19.275 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:19.275 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:19.279 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:19.757 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:19.801 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:19.803 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:19.805 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:19.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:20.229 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:10:20.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:20.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:20.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:20.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:20.703 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:10:21.175 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:10:21.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:21.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:21.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:21.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:21.647 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:10:21.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:21.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:21.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:21.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:21.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:21.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:21.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:21.818 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:21.818 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:21.818 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:21.818 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:26.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:26.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:26.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:26.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:26.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:26.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:26.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:26.837 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:26.837 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:26.838 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:26.838 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:26.844 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:26.844 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:26.844 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:26.844 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:26.845 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:26.845 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:26.845 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:26.845 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:26.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:26.849 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:26.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:26.850 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:26.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:26.850 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:26.850 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:26.850 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:26.853 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:26.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:26.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:26.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:26.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:26.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:26.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:26.854 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:26.858 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:26.858 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:26.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:26.859 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:26.859 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:26.859 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:26.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:26.864 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:27.340 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:27.375 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:27.376 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:27.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:27.377 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:27.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:27.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:27.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:10:27.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:27.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:27.807 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:10:27.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:27.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:27.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:27.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:28.281 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:10:28.753 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:10:28.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:28.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:28.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:28.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:29.225 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:10:29.700 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:10:29.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:29.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:29.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:29.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:30.172 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:10:30.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:30.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:30.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:30.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:30.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:30.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:30.435 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:30.435 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:30.435 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:30.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:30.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:30.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:30.435 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.435 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.435 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.435 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.435 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:30.435 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:35.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:35.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:35.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:35.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:35.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:35.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:35.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:35.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:35.452 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:35.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:35.452 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:35.455 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:35.455 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:35.456 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:35.456 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:35.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:35.456 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:35.456 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:35.456 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:35.460 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:35.460 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:35.460 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:35.460 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:35.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:35.461 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:35.461 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:35.461 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:35.464 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:35.465 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:35.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:35.465 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:35.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:35.465 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:35.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:35.465 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:35.470 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:35.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:35.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:35.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:35.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:35.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:35.471 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:35.471 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.471 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:35.476 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:35.954 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:36.003 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:36.005 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:36.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:36.007 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:36.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:36.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:36.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:10:36.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:36.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:36.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:36.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:36.049 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:36.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:36.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:36.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:36.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:36.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:36.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:36.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:36.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:36.052 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:36.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:36.052 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:41.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:41.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:41.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:41.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:41.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:41.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:41.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:41.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:41.064 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:41.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:41.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:41.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:41.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:41.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:41.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:41.069 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:41.073 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:41.074 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:41.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:41.074 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:41.074 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:41.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:41.078 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:41.078 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:41.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:41.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:41.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:41.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:41.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:41.084 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:41.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:41.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:41.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:41.084 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:41.085 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:41.085 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.085 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:41.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:41.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.090 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:41.569 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:41.613 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:41.615 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:41.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:41.618 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:41.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:41.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:41.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:10:41.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:41.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:42.041 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:10:42.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:42.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:42.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:42.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:42.516 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:10:42.988 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:10:43.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:43.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:43.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:43.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:43.463 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:10:43.936 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:10:44.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:44.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:44.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:44.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:44.411 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:10:44.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:44.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:44.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:44.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:44.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:44.668 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:44.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:44.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:44.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:44.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:44.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:44.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:44.669 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:44.669 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=771 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:44.669 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=771 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:44.669 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=771 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:44.669 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=771 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:49.676 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:49.676 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:49.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:49.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:49.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:49.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:49.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:49.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:49.684 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:49.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:49.684 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:49.686 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:49.687 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:49.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:49.687 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:49.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:49.688 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:49.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:49.688 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:49.690 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:49.690 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:49.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:49.690 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:49.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:49.690 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:49.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:49.690 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:49.692 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:49.692 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:49.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:49.692 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:49.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:49.692 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:49.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:49.692 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:49.695 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:49.695 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.695 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:49.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:49.700 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:50.177 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:50.218 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:50.220 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:50.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:50.223 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:50.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:10:50.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:10:50.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:10:50.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:50.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:50.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:50.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:50.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:50.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:50.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:50.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:50.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:50.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:50.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:50.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:50.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:50.283 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:50.283 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:55.286 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:55.286 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:55.286 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:55.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:55.286 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:55.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:55.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:55.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:55.304 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:55.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:10:55.305 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:10:55.309 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:10:55.309 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:10:55.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:55.309 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:55.309 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:10:55.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:55.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:10:55.310 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:10:55.312 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:10:55.312 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:10:55.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:55.313 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:55.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:55.313 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:10:55.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:10:55.313 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:10:55.315 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:10:55.315 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:10:55.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:55.315 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:10:55.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:55.315 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:10:55.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:10:55.315 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:10:55.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:10:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:10:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:10:55.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:10:55.319 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:10:55.320 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:10:55.320 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:10:55.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:10:55.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:10:55.325 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:10:55.803 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:10:55.850 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:10:55.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:10:55.851 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:10:55.852 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:10:55.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:10:55.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:10:55.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:10:55.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:10:55.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:10:55.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:10:55.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:10:55.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:10:55.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:10:55.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:10:55.862 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:10:55.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:55.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:55.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:55.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:55.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:10:55.862 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:00.864 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:00.864 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:00.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:00.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:00.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:00.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:00.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:00.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:00.879 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:00.880 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:00.880 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:00.882 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:00.882 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:00.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:00.882 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:00.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:00.883 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:00.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:00.883 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:00.884 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:00.884 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:00.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:00.884 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:00.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:00.885 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:00.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:00.885 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:00.886 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:00.886 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:00.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:00.886 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:00.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:00.886 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:00.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:00.886 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:00.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:00.888 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:00.888 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:00.893 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:01.370 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:01.417 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:01.420 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:01.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:01.420 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:01.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:01.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:01.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:01.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:01.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:01.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:01.437 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:01.437 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:01.438 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:06.438 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:06.438 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:06.439 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:06.439 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:06.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:06.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:06.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:06.447 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:06.447 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:06.447 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:06.447 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:06.451 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:06.451 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:06.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:06.452 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:06.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:06.452 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:06.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:06.452 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:06.456 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:06.456 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:06.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:06.456 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:06.456 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:06.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:06.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:06.456 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:06.460 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:06.460 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:06.460 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:06.460 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:06.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:06.461 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:06.461 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:06.461 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:06.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:06.465 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:06.465 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:06.465 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:06.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:06.469 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:06.947 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:06.989 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:06.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:06.993 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:06.995 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:07.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:07.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:07.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:07.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:07.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:07.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:07.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:07.014 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:07.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:07.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:07.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:07.015 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:07.015 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:07.015 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:07.015 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:07.015 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:07.015 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:12.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:12.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:12.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:12.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:12.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:12.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:12.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:12.033 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:12.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:12.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:12.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:12.036 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:12.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:12.037 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:12.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:12.037 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:12.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:12.037 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:12.039 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:12.039 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:12.039 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:12.039 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:12.039 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:12.039 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:12.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:12.040 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:12.042 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:12.042 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:12.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:12.042 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:12.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:12.042 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:12.042 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:12.043 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:12.046 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:12.046 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:12.047 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:12.047 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:12.047 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:12.052 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:12.530 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:12.578 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:12.581 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:12.584 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:12.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:12.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:12.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:12.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:12.604 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:12.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:12.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:12.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:12.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:12.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:12.605 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:12.606 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:17.608 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:17.608 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:17.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:17.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:17.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:17.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:17.616 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:17.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:17.618 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:17.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:17.618 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:17.621 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:17.621 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:17.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:17.622 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:17.622 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:17.622 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:17.623 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:17.623 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:17.626 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:17.626 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:17.626 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:17.627 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:17.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:17.627 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:17.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:17.627 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:17.630 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:17.631 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:17.631 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:17.631 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:17.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:17.631 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:17.631 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:17.631 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:17.637 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:17.638 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:17.638 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:17.638 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:17.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:17.643 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:18.121 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:18.171 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:18.174 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:18.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:18.176 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:18.593 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:11:18.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:18.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:18.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:18.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:19.064 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:11:19.538 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:11:19.644 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:19.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:19.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:19.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:20.010 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:11:20.484 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:11:20.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:20.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:20.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:20.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:20.957 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:11:21.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:21.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:11:21.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:11:21.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:11:21.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:11:21.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:11:21.204 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:11:21.204 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:11:21.430 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:11:21.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:21.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:21.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:21.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:21.903 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:11:22.376 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:11:22.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:22.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:22.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:22.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:22.848 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:11:23.319 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:11:23.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:23.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:11:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:23.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:23.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:23.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:23.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:23.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:23.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:23.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:23.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:23.451 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:23.451 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:23.451 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:23.451 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1255 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:28.456 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:28.457 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:28.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:28.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:28.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:28.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:28.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:28.468 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:28.468 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:28.468 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:28.468 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:28.470 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:28.471 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:28.471 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:28.471 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:28.471 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:28.471 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:28.471 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:28.471 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:28.472 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:28.473 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:28.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:28.473 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:28.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:28.473 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:28.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:28.473 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:28.474 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:28.474 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:28.474 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:28.474 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:28.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:28.474 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:28.474 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:28.474 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:28.476 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:28.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:28.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:28.477 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:28.477 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:28.477 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:28.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:28.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:28.481 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:28.960 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:29.002 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:29.005 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:29.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:29.007 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:29.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:29.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:11:29.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:11:29.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:29.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:29.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:29.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:29.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:29.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:29.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:29.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:29.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:29.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:29.052 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:34.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:34.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:34.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:34.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:34.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:34.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:34.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:34.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:34.064 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:34.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:34.067 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:34.067 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:34.068 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:34.068 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:34.068 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:34.069 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:34.070 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:34.071 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:34.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:34.071 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:34.072 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.072 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:34.072 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:34.073 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:34.073 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:34.073 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:34.073 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:34.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:34.074 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:34.074 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:34.077 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:34.077 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:34.077 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:34.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:34.082 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:34.559 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:34.605 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:34.607 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:34.610 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:34.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:34.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:34.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:11:34.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:11:34.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:34.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:34.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:34.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:34.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:34.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:34.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:34.646 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:34.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:34.646 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:34.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:34.646 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:34.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:34.646 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:34.646 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:34.646 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:34.646 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:34.647 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:34.647 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:39.650 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:39.650 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:39.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:39.651 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:39.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:39.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:39.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:39.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:39.660 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:39.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:39.660 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:39.663 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:39.663 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:39.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:39.664 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:39.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:39.664 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:39.665 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:39.665 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:39.666 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:39.666 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:39.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:39.667 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:39.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:39.667 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:39.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:39.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:39.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:39.668 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:39.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:39.668 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:39.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:39.669 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:39.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:39.669 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:39.671 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:39.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:39.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:39.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:39.671 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:39.672 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:39.672 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:39.672 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:39.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:39.676 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:40.155 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:40.201 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:40.203 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:40.205 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:40.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:40.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:40.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:11:40.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:11:40.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:40.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:40.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:40.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:40.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:40.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:40.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:40.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:40.254 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:40.254 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:40.254 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:40.254 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:40.254 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:40.254 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:40.254 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:40.254 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:40.254 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:40.254 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:40.254 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:40.254 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:40.255 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:45.258 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:45.258 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:45.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:45.258 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:45.258 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:45.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:45.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:45.267 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:45.267 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:45.267 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:45.267 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:45.274 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:45.274 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:45.275 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:45.275 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:45.275 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:45.275 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:45.276 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:45.276 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:45.278 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:45.279 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:45.279 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:45.279 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:45.279 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:45.279 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:45.279 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:45.279 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:45.282 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:45.282 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:45.282 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:45.282 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:45.282 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:45.282 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:45.282 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:45.282 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:45.285 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:45.285 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:45.285 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:45.290 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:45.769 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:45.804 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:45.805 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:45.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.805 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:45.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:11:45.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:11:45.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:11:45.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:45.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:45.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:45.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:45.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:45.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:45.860 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:45.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:45.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:45.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:45.861 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:45.861 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:45.861 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:45.861 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:45.861 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:45.861 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:45.861 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:50.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:50.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:50.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:50.866 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:50.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:50.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:50.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:50.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:50.876 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:50.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:50.877 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:50.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:50.881 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:50.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:50.881 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:50.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:50.882 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:50.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:50.882 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:50.884 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:50.884 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:50.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:50.885 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:50.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:50.885 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:50.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:50.886 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:50.887 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:50.887 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:50.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:50.887 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:50.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:50.887 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:50.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:50.887 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:50.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:50.891 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:50.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:50.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:50.896 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:51.374 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:51.414 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:51.416 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:51.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:51.418 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:51.420 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:11:51.420 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 200
2026-01-29 03:11:51.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:11:51.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:51.849 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:11:51.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:52.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:52.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:52.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:52.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:52.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:52.325 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:11:52.800 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:11:52.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:53.059 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:11:53.059 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 0
2026-01-29 03:11:53.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:11:53.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:53.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:53.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:53.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:53.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:11:53.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:53.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:53.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:53.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:53.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:53.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:53.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:53.068 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:53.068 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:53.068 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:11:53.068 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=469 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:53.068 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=469 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:53.068 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=469 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:53.068 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=469 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:53.068 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=469 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:53.068 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=469 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:53.068 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=469 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:11:58.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:11:58.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:11:58.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:58.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:58.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:58.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:58.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:11:58.084 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:58.084 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:58.084 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:11:58.085 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:11:58.087 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:11:58.087 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:11:58.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:58.087 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:58.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:11:58.088 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:11:58.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:11:58.088 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:11:58.090 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:11:58.090 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:11:58.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:58.090 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:58.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:11:58.090 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:11:58.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:11:58.090 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:11:58.092 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:11:58.092 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:11:58.092 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:58.092 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:11:58.092 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:11:58.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:11:58.092 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:11:58.092 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:11:58.095 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:11:58.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:11:58.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:11:58.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:11:58.095 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:11:58.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:11:58.096 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:11:58.096 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:11:58.096 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:11:58.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:11:58.100 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:11:58.580 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:11:58.616 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:11:58.617 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:11:58.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:58.618 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:11:58.620 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:11:58.620 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 200
2026-01-29 03:11:58.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:11:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:11:59.048 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:11:59.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:59.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:11:59.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:11:59.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:11:59.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:59.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:59.525 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:11:59.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:11:59.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.000 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:12:00.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.256 [DEBUG] fake_trx.py:382 (BTS@172.18.128.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-01-29 03:12:00.256 [INFO] fake_trx.py:385 (BTS@172.18.128.20:5700) Artificial TRXC delay set to 0
2026-01-29 03:12:00.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-01-29 03:12:00.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:00.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:00.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:00.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:00.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:00.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:00.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:00.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:00.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:00.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:00.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:00.268 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:00.268 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:12:00.268 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:00.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:00.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:00.268 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=468 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:00.268 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=468 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:00.268 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=468 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:00.268 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=468 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:00.268 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=468 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:00.268 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=468 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:05.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:05.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:12:05.270 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:05.270 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:05.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:05.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:05.278 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:05.280 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:05.280 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:05.280 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:05.280 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:12:05.283 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:12:05.283 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:12:05.283 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:05.284 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:05.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:05.284 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:12:05.285 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:05.285 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:12:05.287 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:12:05.287 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:12:05.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:05.287 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:05.287 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:05.287 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:12:05.287 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:05.287 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:12:05.290 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:12:05.290 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:12:05.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:05.290 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:05.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:05.290 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:12:05.290 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:05.290 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.295 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:12:05.295 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:12:05.295 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:12:05.296 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:05.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:05.300 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:12:05.779 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:12:05.831 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:12:05.833 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:12:05.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:05.835 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:12:05.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:05.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:05.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:05.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:05.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:05.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:05.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:05.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:05.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:05.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:05.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:05.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:05.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:12:05.878 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:05.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:05.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:10.884 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:10.884 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:12:10.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:10.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:10.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:10.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:10.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:10.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:10.896 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:10.897 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:10.897 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:12:10.902 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:12:10.903 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:12:10.903 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:10.903 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:10.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:10.904 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:12:10.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:10.905 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:12:10.908 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:12:10.908 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:12:10.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:10.909 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:10.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:10.910 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:12:10.910 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:10.910 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:12:10.913 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:12:10.913 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:12:10.913 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:10.913 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:10.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:10.914 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:12:10.914 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:10.914 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:12:10.918 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:12:10.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:12:10.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:12:10.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:12:10.918 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:12:10.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.919 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:12:10.919 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:12:10.919 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:12:10.919 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:10.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:10.924 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:12:11.401 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:12:11.454 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:12:11.456 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:12:11.458 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:12:11.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:11.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:11.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:11.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:11.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:11.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:11.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:11.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:11.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:11.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:11.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:11.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:11.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:11.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:11.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:11.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:12:11.509 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:12:11.509 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:11.510 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:12:16.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:12:16.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:12:16.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:16.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:16.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:16.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:16.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:12:16.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:16.521 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:16.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:12:16.521 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:12:16.528 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:12:16.528 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:12:16.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:16.529 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:16.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:12:16.530 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:12:16.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:12:16.530 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:12:16.534 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:12:16.535 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:12:16.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:16.535 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:16.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:12:16.535 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:12:16.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:12:16.536 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:12:16.540 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:12:16.540 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:12:16.540 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:16.540 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:12:16.541 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:12:16.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:12:16.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:12:16.541 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:12:16.546 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:12:16.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:12:16.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:12:16.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:12:16.546 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:12:16.547 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:12:16.547 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:12:16.547 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:12:16.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:12:16.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:12:16.552 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:12:17.031 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:12:17.083 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:12:17.085 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:12:17.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.087 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:12:17.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:17.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:17.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:17.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.118 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:17.118 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:17.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:17.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:17.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:17.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:17.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:17.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.185 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:17.185 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:17.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:17.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:17.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:17.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:17.501 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:12:17.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:17.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:17.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:17.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:17.974 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:12:18.446 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:12:18.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:18.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:18.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:18.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:18.917 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:12:19.388 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:12:19.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:19.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:19.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:19.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:19.862 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:12:20.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:20.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:20.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:20.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:20.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:20.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:20.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.253 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:20.253 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:20.253 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:20.253 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:20.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:20.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:20.290 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:20.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.334 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:12:20.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:20.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:20.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:20.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:20.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:20.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:20.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:20.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:20.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:20.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:20.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:20.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:20.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:20.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:20.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:20.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:20.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:20.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:20.805 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:12:21.279 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:12:21.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:12:21.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:12:21.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:12:21.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:12:21.751 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:12:22.224 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:12:22.695 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:12:23.165 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:12:23.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:23.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:23.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:23.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:23.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:23.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:23.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:23.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:23.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:23.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:23.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:23.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:23.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:23.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:23.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:23.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:23.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:23.638 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:12:24.111 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:12:24.583 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:12:25.054 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:12:25.527 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:12:26.000 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:12:26.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:26.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:26.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:26.472 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:12:26.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:26.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:26.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:26.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:26.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:26.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:26.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:26.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:26.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:26.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:26.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:26.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:26.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:26.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:26.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:26.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:26.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:26.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:26.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:26.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:26.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:26.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:26.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:26.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:26.943 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:12:27.414 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:12:27.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:27.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:27.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:27.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:27.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:27.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:27.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:27.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:27.639 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:27.639 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:27.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:27.646 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:27.646 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:27.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:27.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:27.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:27.719 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:27.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:27.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:27.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:27.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:27.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:27.741 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:27.741 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:27.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:27.794 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:27.794 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:27.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:27.886 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:12:28.359 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:12:28.831 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:12:29.305 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:12:29.778 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:12:30.251 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:12:30.725 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:12:30.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:30.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:30.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:30.805 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:30.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:30.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:30.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:30.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:30.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:30.831 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:30.831 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:30.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:30.871 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:30.871 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:30.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:30.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:30.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:30.934 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:30.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:30.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:30.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:30.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:30.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:30.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:30.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:30.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:30.958 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:30.958 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:30.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:30.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:31.196 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:12:31.668 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:12:32.142 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:12:32.614 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:12:33.087 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:12:33.560 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:12:33.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:33.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:33.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:33.965 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:33.965 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:33.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:33.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:33.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:33.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:33.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:33.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:33.986 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:33.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:34.032 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:12:34.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:34.040 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:34.040 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:34.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:34.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:34.506 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:12:34.979 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:12:35.452 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:12:35.925 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:12:36.398 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:12:36.870 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:12:37.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:37.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:37.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:37.049 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:37.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:37.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:37.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:37.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:37.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:37.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:37.070 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:37.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:37.111 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:37.111 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:37.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:37.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:37.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:37.196 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:37.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:37.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:37.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:37.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:37.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:37.216 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:37.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:37.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:37.250 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:37.250 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:12:37.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:37.340 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:12:37.814 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:12:38.287 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:12:38.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:38.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:38.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:38.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:38.469 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:38.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:38.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:38.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:38.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:38.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:38.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:38.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:38.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:38.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:38.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:38.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:38.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:38.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:38.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:38.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:38.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:38.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:38.758 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:12:38.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:38.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:38.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:38.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:38.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:38.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:38.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:38.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:38.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:38.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:38.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:38.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:38.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:39.230 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:12:39.703 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:12:40.176 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:12:40.648 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:12:41.119 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:12:41.590 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:12:41.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:41.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:41.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:41.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:41.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:41.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:41.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:41.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:41.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:41.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:41.843 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:41.843 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:41.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:41.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:41.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:41.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:41.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:42.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:42.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:42.062 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:12:42.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:42.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:42.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:42.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:42.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:42.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:42.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:42.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:42.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:42.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:42.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:42.535 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:12:43.007 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:12:43.478 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:12:43.949 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:12:44.422 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:12:44.894 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:12:45.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:45.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:45.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:45.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:45.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:45.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:45.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:45.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:45.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:45.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:45.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:45.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:45.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:45.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:45.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:45.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:45.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:45.367 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:12:45.838 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:12:46.308 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:12:46.782 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:12:47.254 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:12:47.726 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:12:48.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:48.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:48.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:48.197 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:12:48.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:48.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:48.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:48.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:48.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:48.211 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:48.211 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:48.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:48.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:48.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:48.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:48.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:48.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:48.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:48.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:48.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:48.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:48.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:48.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:48.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:48.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:48.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:48.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:48.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:48.668 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:12:49.139 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:12:49.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:49.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:49.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:49.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:49.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:49.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:49.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:49.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:49.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:49.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:49.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:49.238 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:49.238 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:49.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:49.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:49.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:49.296 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:49.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:49.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:49.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:49.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:49.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:49.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:49.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:49.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:49.319 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:49.319 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:49.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:49.609 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:12:50.083 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:12:50.555 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:12:51.027 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:12:51.501 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:12:51.973 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:12:52.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:52.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:52.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:52.326 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:52.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:52.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:52.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:52.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:52.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:52.336 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:52.336 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:52.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:52.346 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:52.346 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:52.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.445 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:12:52.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:52.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:52.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:52.838 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:52.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:52.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:52.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:52.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:52.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:52.856 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:52.856 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:52.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:52.862 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:52.862 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:52.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:52.916 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:12:53.390 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:12:53.862 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:12:54.335 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:12:54.808 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:12:55.281 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:12:55.752 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:12:55.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:55.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:55.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:55.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:55.870 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:55.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:55.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:55.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:55.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:55.890 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:55.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:55.890 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:55.891 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:55.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:55.947 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:55.947 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:55.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:55.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:56.224 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:12:56.698 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:12:57.170 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:12:57.643 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:12:58.116 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:12:58.588 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:12:58.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:58.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:58.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:58.957 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:58.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:58.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:58.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:58.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:58.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:58.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:58.979 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:58.979 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:59.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:59.015 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:59.015 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:59.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.060 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:12:59.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:59.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:59.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:59.443 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:12:59.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:12:59.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:12:59.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:12:59.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:12:59.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:12:59.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:12:59.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:12:59.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:12:59.479 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:12:59.479 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:12:59.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:12:59.533 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:13:00.005 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:13:00.479 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:13:00.951 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 03:13:01.423 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 03:13:01.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:01.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:01.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:01.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:01.877 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:01.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:01.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:01.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:01.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:01.894 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 03:13:01.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:01.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:01.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:01.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:01.898 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:01.898 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:01.898 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:13:01.898 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9795 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:01.898 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9795 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:01.898 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9795 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:01.898 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9795 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:01.898 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9795 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:01.898 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=9795 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:06.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:06.901 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:06.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:06.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:06.901 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:06.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:06.908 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:06.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:06.910 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:06.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:06.911 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:06.914 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:06.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:06.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:06.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:06.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:06.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:06.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:06.917 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:06.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:06.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:06.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:06.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:06.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:06.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:06.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:06.921 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:06.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:06.923 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:06.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:06.923 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:06.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:06.923 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:06.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:06.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:06.926 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:13:06.927 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:13:06.927 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:06.927 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:06.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:06.932 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:07.410 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:07.461 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:07.464 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:07.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.466 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:07.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:07.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:07.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:07.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:07.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:07.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:07.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:07.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:07.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:07.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:07.589 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:07.589 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:07.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.593 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:07.593 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:07.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.690 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:07.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:07.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:07.708 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:07.708 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:07.708 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:07.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:07.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:07.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:07.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:07.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:07.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:07.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:07.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.828 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:07.828 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:07.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.881 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:07.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:07.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:07.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:07.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:07.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:07.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:07.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:07.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:07.968 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:07.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:07.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:07.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:07.978 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:07.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:07.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:07.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:07.982 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:13:07.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:07.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:07.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:07.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=227 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=227 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=227 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=227 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=227 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=227 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=227 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=228 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=228 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:07.984 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=228 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:12.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:12.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:12.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:12.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:12.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:12.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:12.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:12.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:12.996 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:12.997 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:12.997 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:13.000 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:13.001 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:13.001 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:13.001 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:13.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:13.002 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:13.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:13.002 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:13.004 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:13.004 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:13.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:13.004 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:13.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:13.005 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:13.005 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:13.005 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:13.006 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:13.006 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:13.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:13.006 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:13.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:13.006 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:13.007 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:13.007 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:13.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:13:13.010 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:13:13.010 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:13.010 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:13.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:13.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:13.014 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:13.492 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:13.532 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:13.533 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:13.534 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:13.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:13.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:13.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:13.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:13.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:13.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:13.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:13.555 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:13.555 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:13.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:13.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:13.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:13.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:13.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:13.965 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:14.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:14.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:14.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:14.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:14.436 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:13:14.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:14.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:14.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:14.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:14.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:14.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:14.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:14.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:14.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:14.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:14.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:14.480 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:14.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:14.536 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:14.536 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:14.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:14.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:14.909 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:13:15.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:15.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:15.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:15.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:15.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:15.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:15.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:15.177 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:15.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:15.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:15.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:15.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:15.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:15.203 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:15.203 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:15.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:15.240 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:15.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:15.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:15.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:15.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:15.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:15.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:15.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:15.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:15.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:15.363 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:15.363 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:15.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:15.374 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:15.374 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:15.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.380 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:13:15.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:15.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:15.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:15.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:15.778 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:15.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:15.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:15.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:15.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:15.791 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:15.791 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:15.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:15.791 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:15.791 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:15.791 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:15.792 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:13:15.792 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.792 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.792 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.792 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.792 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.792 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.793 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.793 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.793 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.793 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:15.793 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:20.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:20.799 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:20.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:20.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:20.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:20.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:20.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:20.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:20.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:20.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:20.807 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:20.809 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:20.810 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:20.810 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:20.810 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:20.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:20.811 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:20.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:20.811 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:20.813 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:20.813 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:20.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:20.813 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:20.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:20.813 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:20.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:20.813 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:20.816 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:20.816 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:20.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:20.816 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:20.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:20.816 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:20.817 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:20.817 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:20.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:13:20.821 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:13:20.821 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:20.821 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:20.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:20.825 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:21.302 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:21.343 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:21.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:21.347 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:21.349 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:21.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:21.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:21.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:21.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:21.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:21.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:21.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:21.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:21.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:21.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:21.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:21.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:21.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:21.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:21.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:21.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:21.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:21.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:21.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:21.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:21.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:21.639 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:21.639 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:21.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.774 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:21.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:21.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:21.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:21.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:21.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:21.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:21.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:21.921 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:21.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:21.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:21.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:21.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:21.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:21.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:21.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:21.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:21.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:21.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:21.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:21.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:22.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:22.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:22.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:22.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:22.245 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:13:22.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:22.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:22.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:22.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:22.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:22.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:22.259 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:22.259 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:22.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:22.298 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:22.298 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:22.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:22.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:22.717 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:13:22.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:22.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:22.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:22.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:23.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:23.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:23.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:23.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:23.107 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:23.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:23.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:23.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:23.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:23.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:23.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:23.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:23.112 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:13:23.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:23.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:23.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:23.112 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=496 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:23.112 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=496 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:23.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:23.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:23.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:23.113 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:28.118 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:28.118 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:28.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:28.118 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:28.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:28.118 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:28.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:28.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:28.128 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:28.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:28.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:28.133 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:28.133 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:28.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:28.134 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:28.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:28.135 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:28.135 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:28.135 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:28.137 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:28.138 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:28.138 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:28.138 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:28.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:28.139 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:28.139 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:28.139 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:28.141 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:28.141 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:28.141 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:28.141 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:28.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:28.141 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:28.141 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:28.141 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.145 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:13:28.145 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:13:28.145 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:28.145 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:28.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:28.150 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:28.628 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:28.673 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:28.675 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:28.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:28.677 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:28.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:28.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:28.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:28.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:28.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:28.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:28.707 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:28.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:28.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:28.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:28.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:28.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:28.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:28.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:28.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:28.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:28.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:28.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:28.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:28.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:28.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:28.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:28.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:28.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:28.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:28.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:28.965 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:28.965 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:28.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:28.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.100 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:29.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:29.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:29.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:29.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:29.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:29.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:29.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:29.247 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:29.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:29.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:29.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:29.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:29.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:29.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:29.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:29.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:29.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:29.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:29.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:29.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:29.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:29.571 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:13:29.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:29.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:29.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:29.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:29.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:29.583 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:29.583 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:29.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:29.622 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:29.622 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:29.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:29.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:30.042 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:13:30.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:30.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:30.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:30.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:30.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:30.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:30.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:30.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:30.433 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:30.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:30.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:30.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:30.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:30.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:30.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:30.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:30.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:30.444 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:13:30.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:30.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:35.450 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:35.450 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:35.450 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:35.450 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:35.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:35.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:35.458 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:35.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:35.459 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:35.459 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:35.462 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:35.462 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:35.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:35.462 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:35.462 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:35.462 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:35.464 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:35.464 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:35.464 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:35.464 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:35.465 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:35.465 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:35.466 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:35.467 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:35.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:35.467 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:35.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:35.467 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:35.467 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:35.471 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:35.471 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:35.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:13:35.472 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:13:35.472 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:35.472 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:35.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:35.477 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:35.956 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:36.019 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:36.022 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:36.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:36.025 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:36.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:36.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:36.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:36.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:36.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:36.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:36.055 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:36.055 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:36.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:36.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:36.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:36.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:36.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:36.429 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:36.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:36.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:36.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:36.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:36.899 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:13:37.370 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:13:37.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:37.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:37.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:37.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:37.841 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:13:38.312 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:13:38.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:38.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:38.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:38.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:38.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:38.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:38.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:38.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:38.388 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:38.388 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:38.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:38.402 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:38.402 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:38.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:38.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:38.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:38.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:38.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:38.785 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:13:39.258 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:13:39.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:39.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:39.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:39.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:39.731 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:13:40.204 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:13:40.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:40.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:40.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:40.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:40.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:40.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:40.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:40.541 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:40.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:40.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:40.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:40.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:40.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:40.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:40.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:40.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:40.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:40.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:40.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:40.676 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:13:41.148 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:13:41.619 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:13:42.093 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:13:42.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:42.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:42.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:42.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:42.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:42.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:42.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:42.150 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:42.150 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:42.150 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:42.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:42.188 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:42.188 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:42.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:42.565 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:13:43.037 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:13:43.508 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:13:43.982 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:13:44.192 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:44.192 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:44.192 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:44.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:44.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:44.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:44.198 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:44.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:44.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:44.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:44.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:44.200 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:13:44.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:44.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:44.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1886 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:44.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1886 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:44.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1886 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:44.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1886 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:44.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1886 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:44.200 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1886 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:13:49.204 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:13:49.204 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:13:49.204 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:49.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:49.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:49.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:49.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:13:49.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:49.212 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:49.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:13:49.212 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:13:49.214 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:13:49.215 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:13:49.215 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:49.215 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:49.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:13:49.216 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:13:49.216 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:13:49.216 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:13:49.217 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:13:49.217 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:13:49.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:49.218 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:49.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:13:49.218 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:13:49.218 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:13:49.218 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:13:49.220 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:13:49.220 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:13:49.220 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:49.220 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:13:49.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:13:49.220 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:13:49.220 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:13:49.220 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:13:49.223 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:13:49.223 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:13:49.223 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:13:49.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:13:49.228 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:13:49.702 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:13:49.749 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:13:49.752 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:13:49.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:49.754 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:13:49.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:49.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:49.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:49.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:49.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:49.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:49.783 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:49.783 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:49.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:49.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:49.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:49.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:49.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:50.174 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:13:50.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:50.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:50.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:50.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:50.645 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:13:51.116 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:13:51.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:51.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:51.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:51.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:51.589 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:13:51.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:51.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:51.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:51.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:51.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:51.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:51.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:51.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:51.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:51.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:51.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:51.653 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:51.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:51.686 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:51.686 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:13:51.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:51.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:52.062 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:13:52.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:52.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:52.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:52.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:52.534 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:13:53.004 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:13:53.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:53.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:53.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:53.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:53.475 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:13:53.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:53.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:53.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:53.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:53.806 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:13:53.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:53.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:53.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:53.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:53.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:53.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:53.827 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:53.827 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:53.850 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:53.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:53.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:53.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:53.946 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:13:54.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:13:54.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:13:54.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:13:54.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:13:54.417 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:13:54.891 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:13:55.363 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:13:55.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:55.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:55.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:55.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:55.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:13:55.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:13:55.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:13:55.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:55.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:13:55.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:13:55.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:13:55.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:13:55.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:13:55.462 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:13:55.462 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:13:55.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:55.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:13:55.835 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:13:56.306 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:13:56.779 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:13:57.251 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:13:57.722 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:13:58.195 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:13:58.668 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:13:59.135 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:13:59.606 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:14:00.078 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:14:00.551 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:14:01.023 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:14:01.495 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:14:01.968 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:14:02.442 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:14:02.914 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:14:03.387 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:14:03.860 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:14:04.332 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:14:04.806 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:14:05.278 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:14:05.751 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:14:06.224 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:14:06.697 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:14:07.169 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:14:07.642 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:14:08.114 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:14:08.587 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:14:09.061 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:14:09.533 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:14:10.006 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:14:10.479 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:14:10.951 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:14:11.423 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:14:11.895 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:14:12.368 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:14:12.840 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:14:13.312 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:14:13.777 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:14:14.248 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:14:14.722 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:14:15.195 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:14:15.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:15.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:15.426 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:14:15.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:15.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:15.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:15.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:15.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:15.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:15.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:15.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:15.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:15.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:14:15.430 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:14:15.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5663 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:15.430 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5663 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:20.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:20.437 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:14:20.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:20.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:20.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:20.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:20.445 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:20.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:20.446 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:20.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:14:20.446 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:14:20.450 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:14:20.450 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:14:20.450 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:20.450 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:20.450 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:20.450 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:14:20.451 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:14:20.451 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:14:20.455 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:14:20.455 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:14:20.455 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:20.455 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:20.455 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:20.455 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:14:20.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:14:20.456 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:14:20.459 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:14:20.459 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:14:20.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:20.459 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:14:20.460 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:20.460 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:14:20.460 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:14:20.460 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:14:20.465 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:14:20.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:14:20.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:14:20.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:14:20.465 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.466 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:14:20.466 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:14:20.466 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:14:20.466 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:14:20.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:14:20.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:14:20.471 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:14:20.949 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:14:20.995 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:14:20.997 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:14:20.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:20.999 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:14:21.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:21.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:21.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:21.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:21.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:21.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:21.027 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:21.027 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:21.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:21.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:21.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:21.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:21.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:21.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:21.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:21.229 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:21.229 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:21.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:21.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:21.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:21.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:21.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:21.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:21.248 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:21.248 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:21.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:21.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:21.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:21.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:21.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:21.418 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:14:21.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:21.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:21.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:21.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:21.892 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:14:22.364 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:14:22.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:22.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:22.835 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:14:23.308 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:14:23.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:23.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:23.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:23.372 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:23.372 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:23.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:23.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:23.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:23.373 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:23.373 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:23.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:23.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:23.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:23.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:23.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:23.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:23.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:23.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:23.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:23.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:23.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:23.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:23.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:23.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:23.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:23.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:23.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:23.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:23.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:23.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:23.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:23.778 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:14:24.251 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:14:24.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:24.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:24.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:24.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:24.724 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:14:25.194 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:14:25.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:25.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:25.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:25.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:25.665 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:14:25.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:25.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:25.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:25.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:25.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:25.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:25.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:25.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:25.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:25.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:25.769 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:25.769 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:25.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:25.811 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:14:25.811 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:25.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:25.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:26.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:26.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:26.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:26.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:26.079 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:14:26.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:26.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:26.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:26.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:26.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:26.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:26.097 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:26.097 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:26.136 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:14:26.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:26.141 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:14:26.142 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:26.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:26.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:26.609 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:14:27.082 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:14:27.554 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:14:28.025 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:14:28.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:28.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:28.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:28.406 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:14:28.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:28.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:28.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:28.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:28.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:28.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:28.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:28.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:28.450 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:14:28.450 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:28.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.498 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:14:28.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:28.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:28.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:28.724 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:14:28.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:28.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:28.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:28.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:28.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:28.762 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:28.762 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:28.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:28.783 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:14:28.783 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:14:28.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:28.970 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:14:29.443 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:14:29.915 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:14:30.387 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:14:30.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:30.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:30.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:30.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:30.813 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:14:30.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:30.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:30.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:30.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:30.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:30.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:30.832 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:30.832 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:30.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:30.859 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:14:30.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:30.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:30.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:30.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:31.331 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:14:31.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:31.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:31.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:31.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:31.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:31.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:31.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:31.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:31.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:31.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:31.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:31.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:31.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:31.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:31.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:31.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:31.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:31.805 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:14:32.277 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:14:32.750 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:14:33.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:33.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:33.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:33.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:33.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:33.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:33.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:33.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:33.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:33.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:33.208 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:33.208 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:33.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:33.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:33.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:33.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:33.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:33.220 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:14:33.691 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:14:33.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:33.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:33.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:33.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:33.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:33.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:33.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:33.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:33.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:33.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:33.884 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:33.884 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:33.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:33.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:33.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:33.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:33.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:34.164 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:14:34.637 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:14:35.109 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:14:35.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:35.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:35.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:35.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:35.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:35.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:35.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:35.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:35.559 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:35.559 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:35.559 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:35.559 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:35.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:35.580 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:14:35.582 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:14:35.582 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:35.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:35.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:36.052 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:14:36.524 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:14:36.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:36.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:36.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:36.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:36.842 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:14:36.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:36.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:36.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:14:36.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:36.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:14:36.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:14:36.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:14:36.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:14:36.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:14:36.901 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:14:36.901 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:14:36.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:36.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:14:36.996 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:14:37.469 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:14:37.942 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:14:38.415 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:14:38.887 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:14:39.359 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:14:39.832 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:14:40.305 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:14:40.779 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:14:41.251 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:14:41.725 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:14:42.197 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:14:42.670 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:14:43.143 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:14:43.615 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:14:44.088 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:14:44.561 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:14:45.033 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:14:45.505 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:14:45.977 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:14:46.450 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:14:46.922 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:14:47.395 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:14:47.867 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:14:48.341 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:14:48.813 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:14:49.286 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:14:49.759 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:14:50.231 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:14:50.705 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:14:51.178 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:14:51.650 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:14:52.123 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:14:52.596 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:14:53.068 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:14:53.541 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:14:54.013 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:14:54.486 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:14:54.959 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:14:55.432 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:14:55.904 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:14:56.377 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:14:56.850 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:14:56.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:14:56.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:14:56.865 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:14:56.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:14:56.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:14:56.867 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:14:56.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:14:56.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:14:56.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:14:56.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:14:56.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:14:56.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:14:56.868 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:14:56.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:14:56.868 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=7860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:01.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:01.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:01.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:01.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:01.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:01.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:01.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:01.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:01.878 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:01.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:01.879 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:01.879 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:01.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:01.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:01.880 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:01.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:01.880 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:01.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:01.880 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:01.881 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:01.881 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:01.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:01.881 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:01.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:01.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:01.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:01.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:01.882 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:01.882 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:01.882 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:01.882 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:01.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:01.882 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:01.882 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:01.882 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.884 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:15:01.885 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:15:01.885 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:01.885 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:01.889 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:02.367 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:02.409 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:02.411 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:02.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.414 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:02.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:02.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.440 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:02.440 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:02.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:02.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:02.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:02.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:02.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.626 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:02.626 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:02.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.655 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:02.655 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:02.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.727 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:02.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:02.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:02.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:02.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.793 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:02.793 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:02.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.832 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:02.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.880 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:02.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:02.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:02.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:02.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:02.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:02.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:02.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.901 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.901 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.902 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:02.902 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:02.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:02.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:02.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:02.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:02.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:02.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:03.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:03.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:03.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:03.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:03.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:03.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:03.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:03.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:03.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:03.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:03.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:03.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:03.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:03.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:03.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:03.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:03.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:03.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:03.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:03.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:03.300 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:03.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:03.308 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:03.308 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:03.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:03.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:03.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:03.389 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:03.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:03.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:03.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:03.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:03.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:03.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:03.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:03.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:03.445 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:03.445 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:03.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:03.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:03.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:03.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:03.622 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:03.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:03.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:03.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:03.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:03.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:03.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:03.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:03.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:03.636 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:03.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:03.636 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:08.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:08.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:08.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:08.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:08.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:08.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:08.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:08.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:08.650 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:08.651 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:08.651 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:08.657 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:08.658 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:08.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:08.659 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:08.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:08.659 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:08.660 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:08.660 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:08.663 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:08.663 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:08.664 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:08.664 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:08.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:08.664 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:08.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:08.665 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:08.668 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:08.668 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:08.669 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:08.669 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:08.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:08.670 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:08.670 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:08.670 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.675 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:15:08.675 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:15:08.676 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.676 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:08.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:08.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:08.681 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:09.156 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:09.212 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:09.214 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:09.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:09.216 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:09.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:09.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:09.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:09.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:09.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:09.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:09.239 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:09.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:09.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:09.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:09.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:09.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:09.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:09.625 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:09.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:09.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:09.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:09.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:09.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:09.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:09.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:09.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:09.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:09.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:09.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:09.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:09.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:09.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:09.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:09.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:09.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:09.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:09.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:09.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:09.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:10.095 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:10.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:10.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:10.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:10.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:10.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:10.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:10.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:10.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:10.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:10.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:10.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:10.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:10.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:10.138 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:10.138 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:10.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:10.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:10.567 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:10.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:10.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:10.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:10.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:10.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:10.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:10.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:10.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:10.837 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:10.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:10.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:10.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:10.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:10.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:10.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:10.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:10.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:10.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:10.901 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:10.901 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:10.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:10.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.041 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:15:11.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:11.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:11.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:11.322 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:11.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:11.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:11.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:11.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:11.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:11.344 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:11.344 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:11.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:11.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:11.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:11.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:11.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:11.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:11.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:11.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:11.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:11.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:11.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:11.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:11.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:11.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:11.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:11.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:11.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.512 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:15:11.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:11.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:11.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:11.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:11.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:11.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:11.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:11.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:11.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:11.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:11.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:11.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:11.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:11.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:11.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:11.983 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:15:11.983 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:11.983 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:11.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:11.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:12.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:12.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:12.379 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:12.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:12.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:12.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:12.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.399 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:12.399 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:12.399 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:12.399 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:12.454 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:15:12.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:12.456 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:12.456 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:12.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:12.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:12.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:12.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:12.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:12.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:12.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:12.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:12.849 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:12.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:12.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:12.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:12.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:12.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:12.856 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:12.856 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:12.856 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:12.856 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:12.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:12.856 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:17.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:17.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:17.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:17.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:17.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:17.862 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:17.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:17.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:17.874 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:17.874 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:17.874 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:17.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:17.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:17.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:17.881 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:17.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:17.882 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:17.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:17.882 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:17.884 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:17.884 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:17.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:17.885 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:17.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:17.886 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:17.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:17.886 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:17.887 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:17.887 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:17.887 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:17.888 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:17.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:17.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:17.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:17.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:15:17.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:15:17.891 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:17.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:17.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:17.896 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:18.374 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:18.419 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:18.421 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:18.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.423 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:18.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:18.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.451 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:18.451 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:18.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:18.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.557 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:18.557 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:18.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.619 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:18.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:18.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:18.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.700 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:18.700 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:18.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.796 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:18.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:18.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.818 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:18.818 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:18.842 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:18.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.854 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:18.854 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:18.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:18.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:18.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:18.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:18.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.953 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:18.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:18.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:18.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:18.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.969 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:18.969 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:18.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:18.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:18.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:18.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:18.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:19.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:19.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:19.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:19.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:19.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:19.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:19.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:19.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:19.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:19.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:19.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:19.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:19.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:19.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:19.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:19.313 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:19.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:19.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:19.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:19.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:19.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:19.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:19.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:19.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:19.366 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:19.366 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:19.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.784 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:19.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:19.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:19.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:19.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:19.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:19.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:19.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:19.943 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:19.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:19.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:19.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:19.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:19.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:19.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:19.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:19.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:19.965 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:19.965 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:19.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:19.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:20.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:20.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:20.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:20.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:20.176 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:20.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:20.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:20.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:20.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:20.186 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:20.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:20.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:20.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:20.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:20.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:20.187 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:25.192 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:25.192 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:25.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:25.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:25.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:25.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:25.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:25.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:25.206 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:25.207 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:25.207 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:25.211 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:25.212 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:25.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:25.212 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:25.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:25.213 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:25.213 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:25.213 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:25.215 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:25.215 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:25.215 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:25.215 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:25.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:25.215 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:25.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:25.216 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:25.217 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:25.217 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:25.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:25.218 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:25.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:25.218 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:25.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:25.218 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:15:25.221 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:15:25.221 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:25.221 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:25.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:25.226 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:25.704 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:25.748 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:25.750 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:25.752 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:25.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:25.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:25.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:25.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:25.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:25.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:25.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:25.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:25.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:25.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:25.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:25.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:25.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:25.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:26.176 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:26.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:26.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:26.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:26.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:26.647 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:26.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:26.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:26.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:26.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:26.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:26.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:26.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:26.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:26.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:26.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:26.691 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:26.691 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:26.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:26.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:26.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:26.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:26.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:27.120 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:27.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:27.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:27.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:27.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:27.593 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:15:27.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:27.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:27.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:27.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:27.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:27.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:27.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:27.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:27.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:27.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:27.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:27.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:27.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:27.688 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:27.689 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:27.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:27.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.065 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:15:28.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:28.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:28.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:28.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:28.538 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:15:28.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:28.837 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:28.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:28.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:28.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:28.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:28.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:28.859 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:28.859 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:28.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:28.917 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:28.917 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:28.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:28.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:29.011 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:15:29.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:29.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:29.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:29.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:29.483 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:15:29.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:29.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:29.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:29.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:29.803 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:29.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:29.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:29.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:29.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:29.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:29.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:29.824 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:29.824 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:29.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:29.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:29.864 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:29.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:29.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:29.954 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:15:30.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:30.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:30.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:30.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:30.425 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:15:30.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:30.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:30.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:30.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:30.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:30.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:30.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:30.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:30.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:30.484 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:30.484 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:30.484 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:30.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:30.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:30.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:30.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:30.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:30.896 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:15:31.369 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:15:31.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:31.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:31.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:31.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:31.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:31.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:31.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:31.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:31.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:31.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:31.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:31.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:31.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:31.465 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:31.465 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:31.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:31.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:31.841 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:15:32.314 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:15:32.788 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:15:33.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:33.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:33.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:33.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:33.248 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:33.259 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:15:33.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:33.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:33.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:33.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:33.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:33.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:33.269 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:33.269 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:33.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:33.314 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:33.314 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:33.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:33.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:33.731 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:15:34.205 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:15:34.678 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:15:35.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:35.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:35.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:35.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:35.136 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:35.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:35.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:35.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:35.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:35.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:35.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:35.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:35.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:35.148 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:35.148 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:35.148 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:35.148 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2144 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:35.148 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2144 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:35.148 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2144 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:35.148 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2144 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:35.148 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2144 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:40.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:40.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:40.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:40.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:40.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:40.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:40.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:40.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:40.163 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:40.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:40.163 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:40.165 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:40.166 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:40.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:40.166 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:40.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:40.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:40.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:40.167 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:40.168 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:40.169 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:40.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:40.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:40.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:40.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:40.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:40.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:40.171 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:40.171 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:40.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:40.171 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:40.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:40.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:40.172 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:40.172 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:40.174 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:40.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:40.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:40.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:40.174 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:15:40.175 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:15:40.175 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:40.175 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:40.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:40.180 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:40.657 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:40.700 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:40.701 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:40.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:40.703 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:40.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:40.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:40.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:40.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:40.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:40.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:40.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:40.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:40.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:40.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:40.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:40.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:40.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:40.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:40.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:40.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:40.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:40.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:40.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:40.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:40.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:40.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:40.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:40.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:40.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:40.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:40.892 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:40.892 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:40.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:40.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:41.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:41.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:41.043 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:41.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:41.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:41.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:41.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:41.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:41.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:41.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:41.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:41.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:41.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:41.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.127 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:41.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:41.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:41.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:41.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:41.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:41.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:41.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:41.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:41.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:41.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:41.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:41.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:41.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:41.375 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:41.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:41.435 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:41.435 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:41.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:41.600 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:42.072 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:42.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:42.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:42.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:42.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:42.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:42.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:42.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:42.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:42.229 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:42.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:42.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:42.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:42.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:42.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:42.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:42.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:42.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:42.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:42.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:42.241 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:47.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:47.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:47.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:47.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:47.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:47.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:47.253 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:47.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:47.254 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:47.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:47.254 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:47.256 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:47.256 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:47.257 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:47.257 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:47.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:47.257 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:47.258 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:47.258 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:47.259 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:47.259 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:47.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:47.259 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:47.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:47.260 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:47.260 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:47.260 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:47.261 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:47.261 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:47.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:47.262 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:47.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:47.262 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:47.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:47.262 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:47.264 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:47.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:47.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:47.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:47.264 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:15:47.265 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:15:47.265 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:47.265 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:47.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:47.270 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:47.748 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:47.788 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:47.788 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:47.791 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:47.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:47.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:47.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:47.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:47.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:47.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:47.820 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:47.820 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:47.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:47.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:47.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:47.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:47.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:47.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:47.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:47.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:47.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:47.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:47.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:47.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:47.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:47.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:47.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:47.971 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:47.971 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:47.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:47.982 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:47.982 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:47.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:47.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:48.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:48.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:48.135 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:48.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:48.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:48.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:48.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:48.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:48.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:48.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:48.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:48.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:48.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:48.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.215 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:48.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:48.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:48.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:48.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:48.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:48.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:48.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:48.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:48.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:48.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:48.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.466 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:48.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:48.466 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:48.466 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:48.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:48.505 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:48.505 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:48.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:48.687 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:49.160 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:49.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:49.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:49.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:49.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:49.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:49.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:49.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:49.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:49.314 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:49.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:49.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:49.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:49.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:49.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:49.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:49.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:49.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:49.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:49.323 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:15:49.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:49.323 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:49.323 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=446 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:49.323 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=446 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:15:54.329 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:54.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:54.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:54.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:54.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:54.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:54.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:54.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:54.339 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:54.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:15:54.339 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:15:54.342 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:15:54.343 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:15:54.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:54.343 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:54.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:54.344 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:15:54.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:15:54.344 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:15:54.345 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:15:54.346 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:15:54.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:54.346 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:54.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:54.346 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:15:54.346 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:15:54.346 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:15:54.348 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:15:54.348 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:15:54.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:54.348 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:15:54.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:54.348 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:15:54.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:15:54.348 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:15:54.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:15:54.352 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:15:54.352 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:15:54.352 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:15:54.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:15:54.356 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:15:54.834 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:15:54.878 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:15:54.881 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:15:54.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:54.883 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:15:54.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:54.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:54.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:54.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:54.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:54.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:54.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:54.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:54.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:54.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:54.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:54.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:54.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:55.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:55.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:55.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:55.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:55.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:55.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:55.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:55.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:55.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:55.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:55.069 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:55.069 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:15:55.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:55.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:55.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:55.218 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:55.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:55.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:55.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:55.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:55.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:55.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:55.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:55.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:55.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:55.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:55.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.304 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:15:55.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:55.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:55.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:55.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:55.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:55.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:55.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:55.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:55.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:55.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:15:55.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:15:55.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:15:55.543 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:15:55.543 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:15:55.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:55.591 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:15:55.591 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:15:55.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:55.775 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:15:56.248 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:15:56.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:56.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:56.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:56.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:56.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:15:56.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:15:56.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:15:56.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:15:56.407 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:15:56.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:15:56.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:15:56.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:15:56.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:15:56.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:15:56.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:15:56.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:15:56.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:15:56.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:15:56.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:15:56.415 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:01.422 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:01.422 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:01.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:01.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:01.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:01.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:01.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:01.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:01.432 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:01.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:01.433 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:01.436 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:01.436 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:01.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:01.436 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:01.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:01.437 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:01.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:01.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:01.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:01.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:01.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:01.440 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:01.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:01.440 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:01.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:01.440 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:01.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:01.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:01.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:01.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:01.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:01.442 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:01.443 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:01.443 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:01.445 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:01.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:01.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:01.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:01.445 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:01.446 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:01.446 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:01.446 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:01.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:01.451 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:01.930 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:01.970 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:01.971 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:01.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:01.975 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:01.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:01.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:01.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:02.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:02.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:02.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:02.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:02.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:02.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:02.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:02.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:02.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:02.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:02.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:02.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:02.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:02.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:02.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:02.154 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:02.154 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:02.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:02.164 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:02.164 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:02.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:02.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:02.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:02.316 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:02.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:02.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:02.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:02.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:02.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:02.337 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:02.337 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:02.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:02.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:02.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:02.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.402 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:02.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:02.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:02.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:02.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:02.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:02.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:02.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:02.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:02.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:02.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:02.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:02.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:02.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:02.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:02.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:02.692 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:02.692 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:02.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:02.873 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:03.347 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:03.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:03.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:03.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:03.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:03.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:03.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:03.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:03.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:03.502 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:03.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:03.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:03.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:03.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:03.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:03.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:03.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:03.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:03.515 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:03.515 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:03.515 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:03.516 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:03.516 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:03.516 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:03.516 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:03.516 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:03.516 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:08.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:08.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:08.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:08.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:08.518 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:08.518 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:08.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:08.528 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:08.529 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:08.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:08.529 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:08.535 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:08.535 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:08.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:08.536 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:08.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:08.537 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:08.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:08.537 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:08.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:08.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:08.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:08.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:08.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:08.541 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:08.541 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:08.541 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:08.543 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:08.543 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:08.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:08.544 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:08.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:08.544 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:08.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:08.544 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:08.547 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:08.548 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:08.548 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:08.548 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:08.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:08.553 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:09.031 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:09.079 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:09.081 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:09.082 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:09.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:09.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:09.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:09.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:09.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:09.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:09.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:09.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:09.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:09.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:09.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:09.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:09.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:09.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:09.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:09.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:09.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:09.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:09.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:09.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:09.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:09.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:09.510 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:09.511 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:09.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:09.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:09.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:09.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:09.975 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:09.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:09.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:09.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:09.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:09.991 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:10.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:10.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:10.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:10.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:10.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:10.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:10.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:10.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:10.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:10.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:10.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:10.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:10.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:10.449 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:10.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:10.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:10.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:10.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:10.921 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:11.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:11.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:11.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:11.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:11.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:11.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:11.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:11.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:11.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:11.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:11.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:11.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:11.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:11.159 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:11.159 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:11.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:11.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:11.392 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:11.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:11.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:11.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:11.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:11.865 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:12.338 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:16:12.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:12.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:12.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:12.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:12.810 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:13.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:13.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:13.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:13.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:13.130 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:13.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:13.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:13.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:13.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:13.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:13.143 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:13.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:13.143 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:13.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:13.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:13.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:13.143 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:13.143 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:13.143 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:13.143 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:13.143 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:13.143 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:18.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:18.147 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:18.147 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:18.147 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:18.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:18.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:18.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:18.156 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:18.156 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:18.156 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:18.156 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:18.159 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:18.160 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:18.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:18.160 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:18.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:18.161 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:18.161 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:18.161 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:18.162 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:18.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:18.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:18.163 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:18.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:18.163 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:18.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:18.163 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:18.165 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:18.165 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:18.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:18.165 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:18.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:18.165 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:18.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:18.165 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:18.168 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:18.168 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:18.168 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:18.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:18.173 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:18.651 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:18.691 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:18.692 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:18.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:18.694 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:18.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:18.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:18.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:18.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:18.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:18.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:18.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:18.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:18.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:18.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:18.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:18.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:18.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:19.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:19.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:19.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:19.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:19.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:19.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:19.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:19.090 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:19.090 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:19.124 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:19.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:19.131 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:19.131 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:19.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:19.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:19.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:19.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:19.597 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:19.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:19.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:19.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:19.611 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:19.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:19.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:19.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:19.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.632 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:19.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:19.632 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:19.632 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:19.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:19.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:19.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:19.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:19.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:20.069 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:20.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:20.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:20.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:20.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:20.541 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:20.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:20.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:20.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:20.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:20.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:20.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:20.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:20.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:20.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:20.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:20.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:20.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:20.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:20.784 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:20.784 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:20.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:20.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:21.013 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:21.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:21.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:21.486 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:21.958 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:16:22.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:22.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:22.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:22.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:22.430 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:22.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:22.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:22.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:22.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:22.751 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:22.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:22.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:22.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:22.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:22.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:22.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:22.759 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:22.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:22.759 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:22.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:22.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:27.766 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:27.766 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:27.766 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:27.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:27.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:27.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:27.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:27.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:27.775 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:27.776 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:27.776 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:27.778 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:27.779 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:27.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:27.779 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:27.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:27.780 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:27.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:27.780 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:27.781 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:27.782 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:27.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:27.782 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:27.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:27.782 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:27.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:27.782 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:27.784 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:27.784 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:27.784 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:27.784 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:27.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:27.784 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:27.784 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:27.784 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:27.787 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:27.787 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:27.787 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:27.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:27.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:27.792 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:28.269 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:28.315 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:28.317 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:28.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:28.319 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:28.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:28.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:28.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:28.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:28.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:28.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:28.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:28.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:28.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:28.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:28.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:28.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:28.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:28.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:28.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:28.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:28.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:28.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:28.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:28.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:28.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:28.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:28.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:28.707 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:28.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:28.736 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:28.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:28.747 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:28.747 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:28.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:28.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:28.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:28.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:28.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:28.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:29.207 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:29.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:29.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:29.223 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:29.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:29.223 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:29.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:29.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:29.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:29.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:29.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:29.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:29.245 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:29.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:29.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:29.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:29.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:29.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:29.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:29.678 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:29.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:29.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:29.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:29.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:30.149 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:30.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:30.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:30.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:30.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:30.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:30.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:30.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:30.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:30.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:30.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:30.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:30.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:30.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:30.392 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:30.392 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:30.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:30.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:30.620 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:30.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:30.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:30.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:30.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:31.094 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:31.566 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:16:31.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:31.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:31.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:31.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:32.039 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:32.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:32.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:32.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:32.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:32.359 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:32.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:32.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:32.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:32.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:32.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:32.371 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:32.371 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:32.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:32.371 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:32.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:32.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:32.371 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:32.372 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:32.372 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:32.372 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:32.372 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:32.372 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:37.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:37.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:37.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:37.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:37.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:37.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:37.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:37.384 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:37.385 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:37.385 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:37.385 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:37.388 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:37.389 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:37.389 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:37.389 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:37.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:37.390 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:37.390 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:37.390 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:37.392 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:37.392 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:37.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:37.392 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:37.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:37.392 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:37.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:37.392 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:37.394 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:37.394 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:37.394 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:37.394 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:37.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:37.394 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:37.395 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:37.395 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.399 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:37.399 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:37.399 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:37.400 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:37.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:37.404 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:37.882 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:37.933 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:37.935 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:37.937 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:37.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:37.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:37.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:37.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:37.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:37.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:37.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:37.968 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:37.968 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:37.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:37.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:37.977 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:37.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:37.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:38.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:38.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:38.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:38.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:38.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:38.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:38.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:38.303 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:38.303 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:38.351 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:16:38.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:38.361 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:38.362 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:16:38.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:38.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:38.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:38.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:38.824 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:16:38.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:38.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:38.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:38.838 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:38.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:38.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:38.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:38.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:38.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:38.856 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:38.856 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:38.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:38.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:38.864 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:38.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:38.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:39.296 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:16:39.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:39.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:39.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:39.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:39.768 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:16:39.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:39.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:39.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:39.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:39.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:39.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:39.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:39.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:39.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:16:39.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:16:39.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:16:39.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:16:40.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:40.007 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:16:40.007 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:16:40.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:40.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:40.239 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:16:40.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:40.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:40.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:40.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:40.712 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:16:41.185 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:16:41.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:41.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:41.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:41.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:41.657 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:16:41.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:41.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:16:41.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:41.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:41.977 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:16:41.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:41.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:41.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:41.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:41.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:41.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:41.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:41.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:41.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:41.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:41.983 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:46.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:46.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:46.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:46.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:46.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:46.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:46.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:46.994 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:46.994 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:46.994 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:46.995 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:46.997 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:46.997 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:46.998 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:46.998 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:46.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:46.999 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:46.999 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:46.999 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:47.001 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:47.001 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:47.002 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:47.002 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:47.002 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:47.002 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:47.002 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:47.002 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:47.004 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:47.004 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:47.004 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:47.005 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:47.005 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:47.005 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:47.005 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:47.005 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:47.009 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:47.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:47.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:47.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:47.009 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:47.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:47.010 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:47.010 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:47.010 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:47.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:47.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:47.015 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:47.492 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:47.542 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:47.545 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:47.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:47.549 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:47.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:47.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:47.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:47.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:47.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:47.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:47.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:47.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:47.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:47.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:47.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:47.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:47.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:47.594 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:47.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:47.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:47.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:47.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:47.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:47.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:47.594 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:52.598 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:52.598 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:52.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:52.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:52.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:52.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:52.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:52.607 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:52.607 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:52.607 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:52.607 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:52.609 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:52.610 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:52.610 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:52.610 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:52.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:52.611 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:52.611 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:52.611 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:52.612 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:52.612 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:52.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:52.612 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:52.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:52.613 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:52.613 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:52.613 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:52.614 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:52.614 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:52.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:52.615 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:52.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:52.615 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:52.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:52.615 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:52.617 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:52.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:52.617 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:52.617 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:52.617 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:52.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:52.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:52.618 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:52.618 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:52.618 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:52.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:52.622 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:53.101 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:53.141 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:53.144 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:53.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:53.146 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:53.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:53.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:53.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:53.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:53.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:53.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:53.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:53.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:53.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:53.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:53.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:53.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:53.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:53.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:53.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:53.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:53.202 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:53.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:58.208 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:58.208 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:58.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:58.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:58.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:58.209 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:58.217 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:58.219 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:58.219 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:58.219 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:16:58.219 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:16:58.224 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:16:58.225 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:16:58.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:58.225 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:58.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:58.226 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:16:58.226 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:16:58.226 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:16:58.228 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:16:58.228 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:16:58.228 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:58.228 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:58.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:58.228 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:16:58.229 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:16:58.229 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:16:58.231 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:16:58.231 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:16:58.231 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:58.231 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:16:58.231 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:58.231 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:16:58.232 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:16:58.232 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:16:58.235 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:16:58.235 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:16:58.235 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.235 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:16:58.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:16:58.240 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:16:58.717 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:16:58.767 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:16:58.770 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:16:58.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:16:58.772 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:16:58.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:16:58.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:16:58.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:16:58.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:16:58.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:16:58.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:16:58.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:16:58.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:16:58.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:16:58.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:16:58.811 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:16:58.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:16:58.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:16:58.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:16:58.811 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:17:03.818 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:03.818 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:17:03.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:03.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:03.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:03.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:03.826 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:03.826 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:03.826 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:03.826 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:03.826 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:17:03.828 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:17:03.828 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:17:03.828 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:03.828 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:03.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:03.829 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:17:03.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:03.829 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:17:03.830 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:17:03.830 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:17:03.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:03.830 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:03.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:03.830 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:17:03.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:03.830 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:17:03.831 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:17:03.831 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:17:03.831 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:03.831 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:03.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:03.832 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:17:03.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:03.832 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:17:03.833 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:17:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:17:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:17:03.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:17:03.833 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:17:03.834 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:17:03.834 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:17:03.834 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:03.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:17:03.835 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:03.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:08.843 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:08.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:17:08.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:08.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:08.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:08.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:08.851 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:08.852 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:08.852 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:08.852 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:08.852 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:17:08.857 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:17:08.857 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:17:08.857 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:08.857 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:08.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:08.857 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:17:08.858 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:08.858 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:17:08.861 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:17:08.861 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:17:08.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:08.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:08.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:08.862 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:17:08.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:08.862 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:17:08.865 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:17:08.865 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:17:08.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:08.865 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:08.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:08.865 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:17:08.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:08.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:17:08.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:17:08.870 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:17:08.870 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:17:08.870 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:08.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:08.874 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:17:09.350 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:17:09.393 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:17:09.394 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:17:09.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:09.396 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:17:09.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:09.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:09.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:09.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:09.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:09.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:09.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:09.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:09.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:09.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:09.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:09.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:09.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:09.821 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:17:09.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:09.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:09.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:09.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:10.293 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:17:10.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:10.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:10.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:10.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:10.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:10.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:10.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:10.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:10.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:10.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:10.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:10.428 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:10.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:10.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:10.764 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:17:10.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:10.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:10.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:10.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:11.238 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:17:11.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:11.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:11.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:11.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:11.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:11.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:11.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:11.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:11.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:11.375 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:11.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:11.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:11.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:11.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:11.710 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:17:11.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:11.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:11.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:11.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:12.182 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:17:12.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:12.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:12.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:12.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:12.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:12.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:12.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:12.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:12.361 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:12.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:12.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:12.419 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:12.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:12.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:12.653 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:17:12.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:12.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:12.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:12.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:13.127 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:17:13.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:13.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:13.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:13.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:13.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:13.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:13.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:13.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:13.323 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:13.323 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:13.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:13.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:13.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:13.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.599 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:17:13.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:13.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:13.878 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:13.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:13.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:13.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:13.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:13.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:13.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:13.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:13.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:13.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:13.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:13.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:13.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:13.980 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:13.980 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:17:13.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:13.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:14.072 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:17:14.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:14.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:14.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:14.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:14.520 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:14.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:14.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:14.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:14.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:14.542 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:14.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:14.542 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:14.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:14.545 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:17:14.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:14.594 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:14.594 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-01-29 03:17:14.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:14.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.017 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:17:15.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:15.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:15.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:15.149 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:15.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:15.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:15.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:15.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:15.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:15.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:15.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:15.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:15.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:15.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:15.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:15.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.489 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:17:15.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:15.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:15.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:15.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:15.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:15.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:15.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:15.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:15.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:15.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:15.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:15.869 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:15.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:15.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:15.961 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:17:16.434 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:17:16.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:16.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:16.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:16.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:16.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:16.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:16.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:16.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:16.466 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:16.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:16.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:16.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:16.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:16.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:16.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:16.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:16.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:16.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:16.906 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:17:17.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:17.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:17.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:17.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:17.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:17.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:17.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:17.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:17.055 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:17.055 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:17.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:17.108 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:17.108 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:17:17.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.378 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:17:17.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:17.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:17.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:17.689 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:17.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:17.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:17.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:17.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:17.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:17.710 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:17.710 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:17.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:17.759 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:17.759 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:17:17.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:17.851 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:17:18.324 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:17:18.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:18.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:18.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:18.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:18.378 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:18.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:18.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:18.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:18.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:18.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:18.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:18.388 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:18.388 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:18.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:18.424 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:18.424 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:18.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:18.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:18.797 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:17:19.270 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:17:19.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:19.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:19.278 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:19.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:19.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:19.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:19.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:19.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:19.301 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:19.301 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:19.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:19.311 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:19.311 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:19.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:19.742 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:17:20.214 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:17:20.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:20.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:20.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:20.244 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:20.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:20.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:20.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:20.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:20.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:20.258 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:20.258 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:20.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:20.312 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:20.313 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:20.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:20.686 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:17:21.160 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:17:21.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:21.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:21.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:21.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:21.209 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:21.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:21.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:21.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:21.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:21.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:21.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:21.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:21.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:21.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:21.260 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:21.260 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:21.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:21.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:21.631 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:17:22.103 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:17:22.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:22.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:22.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:22.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:22.170 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:22.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:22.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:22.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:22.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:22.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:22.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:22.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:22.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:22.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:22.248 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:22.249 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:22.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:22.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:22.576 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:17:23.048 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:17:23.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:23.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:23.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:23.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:23.134 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:23.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:23.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:23.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:23.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:23.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:23.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:23.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:23.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:23.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:23.194 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:23.194 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:23.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:23.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:23.520 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:17:23.992 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:17:24.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:24.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:24.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:24.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:24.095 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:24.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:24.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:24.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:24.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:24.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:24.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:24.104 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:24.104 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:24.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:24.134 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:24.135 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:24.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:24.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:24.464 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:17:24.937 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:17:25.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:25.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:25.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:25.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:25.061 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:25.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:25.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:25.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:25.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:25.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:25.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:25.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:25.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:25.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:25.125 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:17:25.125 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:17:25.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:25.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:25.410 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:17:25.883 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:17:26.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:26.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:26.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:26.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:26.020 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:17:26.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:26.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:26.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:26.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:26.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:26.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:26.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:26.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:17:26.028 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:17:26.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:26.028 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:31.035 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:31.035 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:17:31.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:31.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:31.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:31.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:31.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:31.044 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:31.044 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:31.044 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:31.044 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:17:31.047 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:17:31.048 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:17:31.048 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:31.048 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:31.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:31.049 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:17:31.049 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:31.049 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:17:31.050 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:17:31.050 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:17:31.050 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:31.050 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:31.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:31.050 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:17:31.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:31.051 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:17:31.052 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:17:31.053 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:17:31.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:31.053 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:31.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:31.053 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:17:31.053 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:31.053 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:17:31.055 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:17:31.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:17:31.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:17:31.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:17:31.055 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:17:31.056 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:17:31.056 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:17:31.056 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:31.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:31.061 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:17:31.540 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:17:31.583 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:17:31.584 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:17:31.587 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:17:31.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:31.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:31.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:31.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:31.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:31.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:31.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:31.617 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:31.617 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:31.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:31.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:31.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:31.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:31.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:31.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:31.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:31.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:31.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:31.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:31.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:31.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:31.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:31.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:31.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:31.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:31.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:31.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:31.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:31.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:31.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:31.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.011 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:17:32.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:32.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:32.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:32.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:32.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:32.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:32.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:32.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:32.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:32.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:32.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:32.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:32.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:32.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:32.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:32.205 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:32.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:32.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:32.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:32.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:32.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:32.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:32.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:17:32.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:32.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:32.427 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:17:32.427 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:17:32.483 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:17:32.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:32.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:17:32.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:17:32.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:17:32.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:17:32.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:17:32.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:17:32.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:17:32.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:17:32.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:17:32.667 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:17:32.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:32.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:32.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:32.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:17:32.669 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:17:32.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:32.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:37.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:17:37.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:17:37.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:37.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:37.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:37.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:37.680 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:17:37.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:37.681 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:37.682 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:17:37.682 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:17:37.685 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:17:37.685 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:17:37.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:37.686 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:37.686 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:17:37.687 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:17:37.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:17:37.687 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:17:37.689 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:17:37.689 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:17:37.689 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:37.690 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:37.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:17:37.690 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:17:37.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:17:37.690 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:17:37.692 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:17:37.692 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:17:37.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:37.692 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:17:37.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:17:37.692 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:17:37.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:17:37.692 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:17:37.696 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:17:37.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:17:37.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:17:37.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:17:37.696 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:17:37.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:17:37.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:17:37.697 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:17:37.697 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:17:37.697 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:17:37.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:17:37.702 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:17:38.180 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:17:38.648 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:17:39.112 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:17:39.575 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:17:40.038 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:17:40.501 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:17:40.974 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:17:41.446 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:17:41.920 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:17:42.392 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:17:42.864 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:17:43.338 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:17:43.810 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:17:44.282 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:17:44.756 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:17:45.228 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:17:45.700 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:17:46.174 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:17:46.646 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:17:47.112 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:17:47.576 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:17:48.039 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:17:48.503 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:17:48.966 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:17:49.429 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:17:49.901 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:17:50.373 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:17:50.847 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:17:51.319 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:17:51.791 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:17:52.267 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:17:52.739 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:17:53.213 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:17:53.685 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:17:54.157 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:17:54.628 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:17:55.102 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:17:55.574 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:17:56.046 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:17:56.520 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:17:56.992 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:17:57.464 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:17:57.938 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:17:58.410 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:17:58.882 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:17:59.357 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:17:59.829 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:18:00.303 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:18:00.775 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:18:01.247 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:18:01.723 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:18:01.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:01.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:01.728 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:01.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:01.729 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:18:01.729 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:18:01.729 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:18:06.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:18:06.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:18:06.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:06.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:06.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:06.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:06.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:06.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:18:06.745 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:06.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:18:06.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:18:06.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:18:06.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:18:06.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:18:06.749 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:06.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:06.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:18:06.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:18:06.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:18:06.752 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:18:06.753 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:18:06.753 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:18:06.753 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:06.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:06.753 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:18:06.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:18:06.754 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:18:06.757 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:18:06.757 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:18:06.757 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:18:06.757 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:06.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:06.758 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:18:06.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:18:06.758 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:18:06.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:18:06.764 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:18:06.764 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:18:06.764 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:06.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:06.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:06.769 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:18:07.246 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:18:07.715 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:18:08.181 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:18:08.647 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:18:09.116 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:18:09.581 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:18:10.044 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:18:10.513 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:18:10.986 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:18:11.456 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:18:11.928 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:18:12.400 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:18:12.874 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:18:13.346 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:18:13.818 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:18:14.289 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:18:14.758 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:18:15.231 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:18:15.703 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:18:16.178 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:18:16.650 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:18:17.118 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:18:17.585 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:18:18.058 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:18:18.522 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:18:18.986 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:18:19.449 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:18:19.912 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:18:20.375 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:18:20.839 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:18:21.302 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:18:21.774 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:18:22.237 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:18:22.701 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:18:23.174 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:18:23.645 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:18:24.109 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:18:24.573 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:18:25.037 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:18:25.500 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:18:25.963 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:18:26.426 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:18:26.890 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:18:27.353 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:18:27.816 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:18:28.289 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:18:28.761 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:18:29.236 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:18:29.700 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:18:30.163 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:18:30.636 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:18:31.108 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:18:31.583 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:18:32.055 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:18:32.530 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:18:33.002 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:18:33.476 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:18:33.948 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:18:34.412 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:18:34.886 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:18:35.358 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:18:35.832 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:18:36.304 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:18:36.776 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:18:37.250 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:18:37.717 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:18:38.180 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:18:38.644 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:18:39.117 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:18:39.589 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:18:40.063 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:18:40.535 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:18:41.007 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:18:41.470 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:18:41.938 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:18:42.410 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:18:42.889 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:18:43.363 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:18:43.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:43.835 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:18:44.304 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:18:44.767 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:18:44.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:45.239 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:18:45.711 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:18:45.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:46.186 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:18:46.657 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:18:46.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:47.129 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:18:47.603 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:18:47.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:48.075 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:18:48.547 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:18:48.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:48.808 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:48.808 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:48.808 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:48.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:48.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:18:48.809 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:18:48.809 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:18:53.814 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:18:53.814 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:18:53.814 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:53.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:53.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:53.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:53.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:18:53.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:18:53.824 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:53.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:18:53.824 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:18:53.828 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:18:53.828 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:18:53.828 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:18:53.828 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:53.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:18:53.829 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:18:53.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:18:53.829 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:18:53.833 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:18:53.833 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:18:53.833 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:18:53.834 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:53.834 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:18:53.834 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:18:53.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:18:53.834 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:18:53.838 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:18:53.838 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:18:53.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:18:53.838 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:18:53.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:18:53.838 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:18:53.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:18:53.838 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:18:53.844 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:18:53.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:18:53.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:18:53.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:18:53.844 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:18:53.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.845 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:18:53.845 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:18:53.845 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:18:53.845 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:18:53.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:18:53.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:18:53.850 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:18:54.328 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:18:54.379 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:18:54.381 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:54.383 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:18:54.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:54.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:18:54.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:18:54.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:54.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:54.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:54.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:18:54.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:18:54.469 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:54.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:54.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:54.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:54.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:54.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:54.800 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:18:54.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:54.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:54.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:54.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:55.272 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:18:55.745 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:18:55.766 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:18:55.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:55.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:55.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:55.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:56.218 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:18:56.691 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:18:56.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:56.853 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:56.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:56.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:57.164 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:18:57.637 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:18:57.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:57.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:57.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:57.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:58.109 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:18:58.583 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:18:58.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:58.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:58.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:58.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:18:58.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:18:58.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:18:58.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:18:58.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:58.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:18:58.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:18:58.682 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:18:58.682 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:18:58.717 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:18:58.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:18:58.732 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:18:58.732 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:18:58.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:58.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:18:58.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:18:58.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:18:58.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:18:58.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:18:59.055 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:18:59.527 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:19:00.000 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:19:00.473 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:19:00.945 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:19:01.419 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:19:01.891 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:19:02.364 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:19:02.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:02.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:02.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:02.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:02.764 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:19:02.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:02.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:02.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:02.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:02.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:02.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:02.786 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:02.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:02.835 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:02.837 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:19:02.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:02.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:02.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:02.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:02.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:03.270 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:19:03.309 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:19:03.781 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:19:04.252 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:19:04.723 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:19:05.196 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:19:05.669 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:19:06.141 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:19:06.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:06.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:06.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:06.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:06.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:06.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:06.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:06.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:06.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:06.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:06.598 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:06.598 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:06.607 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:06.611 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:19:06.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:06.615 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:19:06.615 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:19:06.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:06.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:07.083 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:19:07.556 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:19:07.941 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:19:08.029 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:19:08.501 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:19:08.890 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:19:08.974 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:19:09.360 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:19:09.446 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:19:09.919 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:19:10.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:10.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:10.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:10.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:10.313 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:19:10.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:10.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:10.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:10.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:10.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:10.329 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:10.329 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:19:10.330 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:19:10.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:10.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:10.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:10.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3559 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:10.330 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3559 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:10.331 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3559 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:10.331 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3559 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:10.331 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3559 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:10.331 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3559 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:15.333 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:15.333 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:19:15.333 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:15.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:15.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:15.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:15.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:15.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:15.339 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:15.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:15.339 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:19:15.342 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:19:15.342 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:19:15.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:15.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:15.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:15.343 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:19:15.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:15.343 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:19:15.347 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:19:15.347 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:19:15.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:15.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:15.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:15.348 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:19:15.348 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:15.348 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:19:15.351 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:19:15.351 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:19:15.352 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:15.352 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:15.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:15.352 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:19:15.352 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:15.352 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:19:15.357 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:19:15.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:19:15.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.358 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:19:15.358 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:19:15.358 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:19:15.358 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:15.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:15.363 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:19:15.841 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:19:15.891 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:19:15.893 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:15.895 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:19:15.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:15.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:15.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:15.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:15.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:15.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:15.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:15.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:15.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:15.981 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:15.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:15.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:15.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:15.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:15.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:16.314 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:19:16.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:16.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:16.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:16.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:16.787 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:19:16.799 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:17.260 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:19:17.285 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:17.287 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:19:17.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:17.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:17.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:17.366 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:17.733 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:19:17.765 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:18.206 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:19:18.245 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:18.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:18.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:18.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:18.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:18.679 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:19:18.732 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:19.151 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:19:19.212 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:19.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:19.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:19.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:19.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:19.625 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:19:19.692 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:20.097 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:19:20.178 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:20.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:20.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:20.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:20.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:20.570 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:19:20.658 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:21.043 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:19:21.138 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:21.516 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:19:21.624 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:21.988 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:19:22.104 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:22.459 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:19:22.584 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:22.932 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:19:23.064 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:23.405 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:19:23.550 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:23.877 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:19:24.030 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:24.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:24.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:24.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:24.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:24.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:24.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:24.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:24.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:24.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:24.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:24.055 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:24.055 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:24.057 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:24.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:24.060 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:19:24.060 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:19:24.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:24.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:24.350 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:19:24.750 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:24.823 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:19:25.236 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:25.295 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:19:25.716 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:25.768 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:19:26.196 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:26.241 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:19:26.682 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:26.713 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:19:27.162 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:27.184 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:19:27.642 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:27.657 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:19:28.122 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:28.130 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:19:28.603 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:19:28.608 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:29.077 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:19:29.093 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:29.550 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:19:29.574 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:30.023 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:19:30.053 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:30.496 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:19:30.540 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:30.968 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:19:31.020 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:31.442 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:19:31.499 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:31.914 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:19:31.985 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:31.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:31.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:31.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:31.991 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:19:31.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:31.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:31.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:31.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:31.999 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:31.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:31.999 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:31.999 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:32.003 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:32.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:32.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:32.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:32.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:32.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:32.350 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:32.386 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:19:32.821 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:32.823 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:19:32.857 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:19:33.291 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:33.330 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:19:33.762 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:33.803 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:19:34.239 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:34.275 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:19:34.709 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:34.746 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:19:35.180 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:35.217 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:19:35.651 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:35.690 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:19:36.122 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:36.163 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:19:36.598 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:36.635 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:19:37.069 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:37.106 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:19:37.540 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:37.577 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:19:38.011 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:38.047 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:19:38.481 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:38.518 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:19:38.952 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:38.989 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:19:39.423 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:39.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:39.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:39.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:39.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:39.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:39.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:39.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:39.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:39.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:39.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:39.449 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:39.449 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:39.454 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:39.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:39.459 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:19:39.459 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:19:39.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:39.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:39.461 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:19:39.849 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:39.934 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:19:40.324 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:40.326 [DEBUG] fake_trx.py:269 (MS@172.18.128.22:6700) Recv SETTA cmd
2026-01-29 03:19:40.407 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:19:40.795 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:40.880 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:19:41.265 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:41.352 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:19:41.742 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:41.824 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:19:42.212 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:42.297 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:19:42.683 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:42.769 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:19:43.160 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:43.241 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:19:43.630 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:43.714 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:19:44.101 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:44.187 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:19:44.577 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:44.660 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:19:45.048 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:45.133 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:19:45.518 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:45.605 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:19:45.996 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:46.078 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:19:46.466 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:46.551 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:19:46.938 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:46.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:46.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:46.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:46.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:46.946 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:19:46.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:46.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:46.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:46.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:46.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:46.964 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:46.964 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:19:46.964 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:19:46.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:46.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:46.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:46.965 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:46.965 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:46.965 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:46.965 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:46.965 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:46.965 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:19:51.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:51.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:19:51.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:51.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:51.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:51.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:51.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:51.975 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:51.975 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:51.975 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:19:51.976 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:19:51.978 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:19:51.978 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:19:51.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:51.978 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:51.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:51.979 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:19:51.979 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:19:51.979 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:19:51.983 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:19:51.983 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:19:51.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:51.983 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:51.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:51.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:19:51.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:19:51.984 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:19:51.989 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:19:51.989 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:19:51.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:51.989 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:19:51.990 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:51.990 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:19:51.990 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:19:51.990 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:19:51.997 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:19:51.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:19:51.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:19:51.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:19:51.997 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:19:51.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:51.998 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:19:51.998 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:19:51.998 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:19:51.998 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:51.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:19:52.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:19:52.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:19:52.003 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:19:52.480 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:19:52.535 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:19:52.538 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:19:52.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:52.540 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:19:52.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:52.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:52.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:52.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:52.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:52.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:52.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:52.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:52.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:52.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:52.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:52.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:52.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:52.950 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:19:53.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:53.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:53.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:53.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:53.423 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:19:53.896 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:19:54.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:54.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:54.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:54.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:54.369 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:19:54.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:54.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:54.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:54.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:54.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:54.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:54.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:54.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:54.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:54.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:54.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:54.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:54.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:54.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:54.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:54.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:54.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:54.841 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:19:55.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:55.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:55.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:55.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:55.314 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:19:55.787 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:19:56.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:56.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:56.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:56.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:56.260 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:19:56.732 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:19:56.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:56.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:56.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:56.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:56.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:56.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:56.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:19:56.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:56.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:56.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:56.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:19:56.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:19:56.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:56.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:19:56.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:19:56.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:56.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:57.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:57.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:57.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:57.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:57.203 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:19:57.675 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:19:58.148 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:19:58.621 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:19:59.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:19:59.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:19:59.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:19:59.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:19:59.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:19:59.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:19:59.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:19:59.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:19:59.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:19:59.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:19:59.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:19:59.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:19:59.093 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:19:59.093 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:19:59.093 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:04.119 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:04.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:04.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:04.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:04.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:04.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:04.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:04.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:04.129 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:04.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:04.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:04.132 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:04.132 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:04.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:04.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:04.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:04.133 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:04.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:04.134 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:04.136 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:04.136 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:04.136 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:04.137 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:04.137 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:04.137 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:04.137 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:04.137 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:04.139 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:04.139 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:04.139 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:04.139 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:04.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:04.140 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:04.140 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:04.140 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:04.142 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:04.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:04.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:04.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:04.142 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:20:04.143 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:20:04.143 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:04.143 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:04.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:04.148 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:04.625 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:04.670 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:04.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:04.673 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:04.676 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:04.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:04.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:04.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:04.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:04.704 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:04.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:04.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:04.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:04.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:04.726 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:20:04.726 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:04.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:04.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:05.097 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:05.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:05.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:05.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:05.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:05.571 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:06.044 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:06.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:06.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:06.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:06.148 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:06.516 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:06.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:06.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:06.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:06.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:06.830 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:20:06.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:06.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:06.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:06.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:06.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:06.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:06.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:06.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:06.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:06.900 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:20:06.900 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:06.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:06.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:06.987 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:20:07.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:07.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:07.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:07.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:07.459 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:20:07.933 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:20:08.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:08.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:08.151 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:08.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:08.406 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:20:08.880 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:20:08.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:08.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:09.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:09.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:09.004 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:20:09.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:09.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:09.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:09.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:09.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:09.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:09.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:09.016 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:09.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:09.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:09.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:09.016 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1051 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.016 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1051 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.016 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1051 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.016 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1051 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.016 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1051 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.016 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1051 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:09.016 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1051 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:14.020 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:14.020 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:14.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:14.020 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:14.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:14.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:14.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:14.029 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:14.029 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.030 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:14.030 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:14.035 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:14.035 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:14.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:14.035 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:14.036 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:14.036 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:14.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:14.040 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:14.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:14.040 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:14.040 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:14.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:14.044 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:14.045 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:14.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:14.045 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:14.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:14.045 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:14.045 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:20:14.052 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:20:14.052 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:14.052 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:14.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:14.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:14.057 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:14.534 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:14.580 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:14.582 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:14.583 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:14.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:14.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:14.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:14.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:14.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:14.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:14.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:14.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:14.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:14.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:14.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:14.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:14.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:14.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:15.004 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:15.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:15.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:15.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:15.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:15.477 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:15.949 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:16.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:16.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:16.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:16.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:16.420 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:16.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:16.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:16.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:16.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:16.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:16.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:16.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:16.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:16.740 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:16.740 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:16.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:16.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:16.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:16.890 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:20:17.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:17.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:17.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:17.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:17.362 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:20:17.836 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:20:18.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:18.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:18.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:18.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:18.308 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:20:18.780 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:20:18.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:18.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:18.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:18.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:18.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:18.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:18.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:18.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:18.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:18.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:18.824 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:18.824 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:18.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:18.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:18.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:18.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:18.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:19.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:19.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:19.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:19.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:19.251 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:20:19.725 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:20:20.197 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:20:20.670 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:20:20.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:20.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:20.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:20.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:20.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:20.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:20.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:20.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:20.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:20.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:20.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:20.982 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:20.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:20.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:20.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:20.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:20.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:20.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:20.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:20.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:20.983 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:25.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:25.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:25.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:25.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:25.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:25.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:26.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:26.004 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:26.005 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:26.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:26.005 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:26.007 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:26.007 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:26.007 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:26.007 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:26.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:26.008 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:26.008 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:26.008 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:26.009 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:26.009 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:26.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:26.010 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:26.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:26.010 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:26.010 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:26.010 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:26.011 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:26.011 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:26.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:26.011 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:26.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:26.011 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:26.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:26.011 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:26.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:20:26.014 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:20:26.014 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:26.014 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:26.018 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:26.494 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:26.525 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:26.526 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:26.526 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:26.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:26.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:26.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:26.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:26.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:26.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:26.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:26.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:26.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:26.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:26.597 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:20:26.597 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:26.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:26.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:26.965 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:27.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:27.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:27.017 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:27.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:27.438 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:27.912 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:28.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:28.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:28.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:28.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:28.384 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:28.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:28.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:28.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:28.722 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:20:28.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:28.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:28.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:28.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:28.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:28.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:28.737 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:28.737 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:28.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:28.761 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:20:28.761 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:28.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:28.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:28.855 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:20:29.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:29.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:29.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:29.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:29.328 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:20:29.801 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:20:30.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:30.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:30.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:30.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:30.273 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:20:30.747 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:20:30.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:30.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:30.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:30.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:30.872 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:20:30.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:30.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:30.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:30.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:30.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:30.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:30.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:30.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:30.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:30.885 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:30.885 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:35.894 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:35.894 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:35.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:35.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:35.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:35.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:35.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:35.915 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:35.915 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:35.915 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:35.915 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:35.919 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:35.920 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:35.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:35.920 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:35.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:35.920 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:35.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:35.920 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:35.924 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:35.924 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:35.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:35.924 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:35.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:35.924 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:35.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:35.924 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:35.927 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:35.927 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:35.927 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:35.927 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:35.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:35.927 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:35.927 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:35.927 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:20:35.930 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:20:35.930 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:35.930 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:35.935 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:36.413 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:36.458 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:36.460 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:36.462 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:36.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:36.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:36.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:36.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:36.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:36.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:36.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:36.486 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:36.486 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:36.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:36.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:36.518 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:36.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:36.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:36.883 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:36.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:36.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:36.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:36.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:37.357 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:37.829 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:37.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:37.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:37.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:37.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:38.300 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:38.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:38.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:38.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:38.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:38.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:38.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:38.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:38.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:38.707 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:38.707 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:38.707 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:38.707 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:38.707 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:38.707 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:38.707 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:43.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:43.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:43.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:43.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:43.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:43.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:43.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:43.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:43.728 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:43.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:43.729 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:43.731 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:43.731 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:43.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:43.731 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:43.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:43.732 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:43.732 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:43.732 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:43.733 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:43.733 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:43.733 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:43.733 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:43.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:43.733 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:43.733 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:43.733 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:43.735 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:43.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:43.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:43.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:43.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:43.735 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:43.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:43.735 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:43.737 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:43.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:43.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:43.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:43.737 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:20:43.738 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:20:43.738 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:43.738 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:43.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:43.742 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:44.214 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:44.259 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:44.261 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:44.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:44.263 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:44.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:44.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:44.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:44.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:44.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:44.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:44.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:44.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:44.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:44.318 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:20:44.318 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:20:44.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:44.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:44.681 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:44.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:44.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:44.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:44.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:45.154 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:45.627 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:20:45.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:45.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:45.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:45.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:46.100 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:20:46.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:46.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:46.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:46.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:46.515 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:20:46.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:46.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:46.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:46.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:46.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:46.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:46.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:46.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:46.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:46.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:46.527 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:46.527 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:51.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:51.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:51.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:51.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:51.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:51.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:51.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:51.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:51.544 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:51.544 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:51.544 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:51.549 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:51.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:51.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:51.550 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:51.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:51.551 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:51.551 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:51.551 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:51.553 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:51.553 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:51.553 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:51.553 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:51.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:51.554 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:51.554 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:51.554 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:51.556 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:51.556 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:51.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:51.556 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:51.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:51.557 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:51.557 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:51.557 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.560 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:20:51.560 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:20:51.560 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:51.561 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:51.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:51.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:51.565 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:52.043 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:52.089 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:52.091 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:52.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:52.094 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:52.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:52.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:52.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:52.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:52.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:52.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:52.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:52.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:52.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:52.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:52.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.515 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:52.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:52.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:52.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:52.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:52.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:52.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:52.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:52.585 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:52.585 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:52.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:52.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:52.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:52.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:52.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:52.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:52.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:52.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:52.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:52.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:52.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:52.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:52.986 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:20:52.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:52.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:52.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:52.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:53.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:53.002 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:53.002 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:53.002 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:53.003 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:53.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:53.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:53.003 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:53.003 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:53.003 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:53.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:53.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:53.004 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:58.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:58.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:58.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:58.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:58.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:58.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:58.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:58.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:58.020 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:58.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:20:58.021 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:20:58.023 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:20:58.023 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:20:58.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:58.023 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:58.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:58.024 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:20:58.024 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:20:58.024 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:20:58.025 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:20:58.025 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:20:58.026 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:58.026 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:58.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:58.026 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:20:58.026 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:20:58.026 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:20:58.027 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:20:58.027 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:20:58.027 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:58.027 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:20:58.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:58.027 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:20:58.027 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:20:58.027 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.029 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:20:58.029 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:20:58.029 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:20:58.029 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:20:58.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:20:58.034 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:20:58.512 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:20:58.553 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:20:58.554 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:20:58.555 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:20:58.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:58.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:58.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:58.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:58.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:58.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:58.589 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:58.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:58.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:58.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:58.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:58.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:58.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:58.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:58.984 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:20:58.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:58.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:58.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:58.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:59.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:59.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:59.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:20:59.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:59.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:59.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:59.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:20:59.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:20:59.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:59.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:20:59.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:20:59.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:59.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:59.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:59.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:59.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:59.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:59.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:20:59.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:20:59.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:20:59.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:20:59.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:20:59.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:20:59.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:20:59.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:20:59.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:20:59.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:20:59.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:20:59.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:20:59.411 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:20:59.411 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:20:59.411 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:20:59.412 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=298 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:59.412 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=298 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:59.412 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=298 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:59.412 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=298 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:59.412 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=298 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:20:59.412 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=298 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:04.413 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:04.413 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:04.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:04.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:04.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:04.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:04.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:04.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:04.421 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:04.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:04.422 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:04.424 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:04.424 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:04.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:04.425 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:04.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:04.425 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:04.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:04.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:04.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:04.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:04.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:04.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:04.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:04.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:04.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:04.427 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:04.429 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:04.429 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:04.429 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:04.429 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:04.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:04.430 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:04.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:04.430 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:04.432 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:04.432 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:04.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:04.433 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:04.433 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:04.433 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:04.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:04.437 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:04.915 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:04.952 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:04.954 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:04.956 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:04.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:04.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:04.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:04.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:05.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.018 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:05.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:05.018 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:05.018 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:05.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:05.060 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:05.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:05.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.383 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:05.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:05.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:05.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:05.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:05.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:05.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:05.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:05.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:05.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:05.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:05.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:05.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:05.462 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:05.462 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:05.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:05.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:05.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:05.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.853 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:05.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:05.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:05.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:05.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:05.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:05.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:05.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:05.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:05.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:05.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:05.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:05.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:05.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:05.907 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:05.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:10.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:10.911 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:10.911 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:10.911 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:10.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:10.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:10.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:10.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:10.920 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:10.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:10.920 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:10.922 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:10.922 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:10.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:10.922 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:10.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:10.923 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:10.923 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:10.923 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:10.925 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:10.925 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:10.925 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:10.925 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:10.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:10.925 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:10.925 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:10.925 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:10.927 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:10.927 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:10.927 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:10.927 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:10.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:10.927 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:10.927 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:10.927 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:10.930 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:10.930 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:10.930 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:10.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:10.935 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:11.411 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:11.448 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:11.449 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:11.451 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:11.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:11.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:11.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:11.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:11.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:11.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:11.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:11.513 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:11.513 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:11.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:11.556 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:21:11.556 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:21:11.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:11.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:11.879 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:11.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:11.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:11.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:11.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:12.350 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:12.820 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:21:12.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:12.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:12.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:12.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:13.292 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:21:13.765 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:21:13.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:13.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:13.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:13.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:14.237 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:21:14.709 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:21:14.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:14.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:14.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:14.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:15.182 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:21:15.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:15.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:15.562 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:21:15.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:15.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:15.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:15.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:15.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:15.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:15.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:15.567 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:15.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:15.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:15.567 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:15.567 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1003 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.567 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1003 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.567 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1003 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.567 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.567 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:15.568 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1004 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:20.572 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:20.572 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:20.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:20.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:20.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:20.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:20.578 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:20.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:20.580 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:20.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:20.580 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:20.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:20.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:20.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:20.585 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:20.585 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:20.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:20.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:20.586 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:20.592 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:20.592 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:20.593 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:20.593 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:20.593 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:20.593 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:20.593 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:20.593 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:20.597 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:20.597 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:20.597 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:20.597 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:20.598 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:20.598 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:20.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:20.598 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:20.604 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:20.604 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:20.604 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:20.605 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:20.608 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:21.086 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:21.135 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:21.138 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:21.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:21.140 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:21.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:21.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:21.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:21.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:21.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:21.207 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:21.207 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:21.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:21.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:21.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:21.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:21.449 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:21.449 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:21.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:21.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:21.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:21.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:21.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:21.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:21.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:21.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:21.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:21.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:21.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.555 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:21.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:21.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:21.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:21.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:21.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:21.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:21.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:21.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:21.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:21.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:21.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:21.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:21.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:21.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:21.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:21.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:21.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:21.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:21.735 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:26.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:26.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:26.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:26.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:26.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:26.741 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:26.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:26.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:26.748 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:26.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:26.748 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:26.751 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:26.752 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:26.752 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:26.752 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:26.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:26.753 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:26.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:26.753 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:26.755 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:26.755 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:26.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:26.755 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:26.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:26.755 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:26.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:26.755 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:26.757 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:26.757 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:26.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:26.758 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:26.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:26.758 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:26.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:26.758 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:26.761 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:26.761 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:26.761 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:26.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:26.766 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:27.244 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:27.283 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:27.284 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:27.285 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:27.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:27.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:27.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:27.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:27.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:27.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:27.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:27.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:27.348 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:27.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:27.390 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:21:27.390 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:21:27.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:27.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:27.717 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:27.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:27.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:27.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:27.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:28.191 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:28.663 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:21:28.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:28.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:28.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:28.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:29.137 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:21:29.609 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:21:29.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:29.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:29.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:29.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:30.081 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:21:30.554 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:21:30.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:30.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:30.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:30.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:31.027 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:21:31.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:31.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:31.396 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:31.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:31.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:31.399 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:31.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:36.405 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:36.405 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:36.405 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:36.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:36.405 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:36.405 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:36.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:36.415 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:36.415 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:36.415 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:36.415 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:36.418 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:36.418 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:36.419 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:36.419 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:36.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:36.420 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:36.420 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:36.420 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:36.421 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:36.421 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:36.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:36.422 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:36.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:36.422 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:36.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:36.422 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:36.424 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:36.424 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:36.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:36.424 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:36.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:36.424 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:36.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:36.424 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:36.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:36.428 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:36.428 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:36.428 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:36.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:36.432 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:36.909 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:36.955 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:36.957 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:36.959 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:36.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:36.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:36.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:36.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:37.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:37.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:37.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:37.022 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:37.022 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:37.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:37.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:37.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:37.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:37.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:37.382 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:37.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:37.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:37.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:37.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:37.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:37.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:37.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:37.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:37.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:37.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:37.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:37.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:37.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:37.787 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:37.787 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:37.787 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:37.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:37.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:37.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:37.787 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:37.787 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:37.787 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:37.787 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:37.787 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:37.787 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:42.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:42.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:42.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:42.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:42.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:42.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:42.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:42.799 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:42.799 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:42.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:42.800 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:42.802 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:42.802 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:42.802 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:42.802 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:42.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:42.803 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:42.803 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:42.803 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:42.804 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:42.804 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:42.804 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:42.804 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:42.804 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:42.804 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:42.804 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:42.804 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:42.806 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:42.806 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:42.806 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:42.806 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:42.806 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:42.806 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:42.806 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:42.807 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:42.809 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:42.809 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:42.809 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:42.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:42.814 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:43.292 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:43.329 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:43.330 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:43.331 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:43.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:43.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:43.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:43.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:43.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:43.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:43.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:43.389 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:43.389 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:43.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:43.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:43.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:43.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:43.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:43.763 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:43.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:43.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:43.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:43.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:44.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:44.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:44.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:44.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:44.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:44.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:44.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:44.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:44.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:44.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:44.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:44.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:44.168 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:44.168 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:44.169 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:49.172 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:49.172 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:49.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:49.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:49.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:49.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:49.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:49.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:49.181 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:49.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:49.182 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:49.185 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:49.185 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:49.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:49.186 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:49.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:49.187 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:49.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:49.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:49.189 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:49.189 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:49.190 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:49.190 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:49.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:49.191 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:49.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:49.191 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:49.192 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:49.192 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:49.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:49.193 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:49.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:49.193 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:49.193 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:49.193 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:49.196 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:49.196 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:49.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:49.197 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:49.197 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:49.197 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:49.202 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:49.676 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:49.727 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:49.729 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:49.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:49.731 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:49.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:49.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:49.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:49.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:49.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:49.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:49.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:49.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:49.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:49.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:49.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:49.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:49.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:50.149 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:50.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:50.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:50.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:50.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:50.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:50.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:50.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:50.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:50.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:50.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:50.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:50.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:50.557 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:50.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:50.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:50.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:50.558 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:50.558 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:50.558 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:50.558 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:50.558 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:50.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:50.559 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:21:55.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:55.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:55.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:55.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:55.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:55.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:55.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:55.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:55.565 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:55.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:21:55.565 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:21:55.568 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:21:55.568 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:21:55.569 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:55.569 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:55.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:55.569 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:21:55.569 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:21:55.570 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:21:55.571 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:21:55.571 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:21:55.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:55.571 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:55.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:55.571 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:21:55.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:21:55.571 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:21:55.573 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:21:55.573 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:21:55.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:55.573 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:21:55.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:21:55.573 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:21:55.574 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:21:55.574 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:21:55.576 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:21:55.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:21:55.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:21:55.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:21:55.576 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:21:55.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:21:55.577 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:21:55.577 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:21:55.577 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:21:55.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:21:55.581 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:21:56.060 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:21:56.105 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:21:56.108 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:21:56.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:56.111 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:21:56.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:56.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:56.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:21:56.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:56.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:21:56.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:21:56.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:21:56.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:21:56.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:56.204 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:21:56.204 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:21:56.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:56.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:56.531 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:21:56.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:56.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:56.580 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:56.580 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:57.004 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:21:57.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:21:57.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:21:57.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:21:57.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:21:57.059 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:21:57.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:21:57.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:21:57.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:21:57.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:21:57.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:21:57.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:21:57.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:21:57.068 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:21:57.068 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:21:57.068 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:21:57.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:02.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:02.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:02.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:02.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:02.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:02.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:02.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:02.084 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:02.085 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:02.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:02.085 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:02.088 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:02.089 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:02.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:02.089 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:02.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:02.090 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:02.090 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:02.090 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:02.092 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:02.092 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:02.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:02.093 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:02.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:02.093 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:02.093 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:02.093 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:02.095 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:02.095 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:02.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:02.095 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:02.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:02.095 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:02.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:02.095 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:02.098 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:02.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:02.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:02.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:02.098 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:02.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:22:02.099 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:22:02.099 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:02.099 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:02.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:02.104 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:02.582 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:02.622 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:02.623 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:02.624 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:02.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:02.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:02.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:02.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:22:02.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:02.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:02.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:02.688 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:22:02.688 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:22:02.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:02.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:02.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:02.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:02.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:03.053 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:03.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:03.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:03.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:03.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:03.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:03.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:03.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:03.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:03.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:03.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:03.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:03.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:03.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:03.457 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:03.457 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:03.457 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:03.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:03.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:03.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:03.457 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:03.457 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:03.457 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:03.457 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:03.458 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:03.458 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:08.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:08.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:08.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:08.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:08.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:08.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:08.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:08.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:08.473 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:08.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:08.473 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:08.475 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:08.475 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:08.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:08.476 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:08.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:08.476 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:08.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:08.476 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:08.478 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:08.478 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:08.478 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:08.478 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:08.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:08.478 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:08.478 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:08.478 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:08.480 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:08.480 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:08.480 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:08.480 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:08.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:08.481 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:08.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:08.481 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.484 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:22:08.484 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:22:08.484 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:08.484 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:08.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:08.489 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:08.967 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:09.008 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:09.009 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:09.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:09.011 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:09.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:09.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:09.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:22:09.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:09.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:09.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:09.072 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:22:09.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:22:09.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:09.111 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:22:09.111 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:22:09.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:09.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:09.435 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:09.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:09.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:09.488 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:09.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:09.908 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:09.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:09.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:09.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:09.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:09.963 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:22:09.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:09.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:09.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:09.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:09.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:09.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:09.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:09.974 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:09.974 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:09.974 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:09.974 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:09.974 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:22:14.980 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:14.980 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:14.980 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:14.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:14.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:14.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:14.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:14.991 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:14.991 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:14.992 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:14.992 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:14.996 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:14.996 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:14.997 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:14.997 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:14.997 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:14.998 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:14.998 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:14.998 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:15.000 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:15.000 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:15.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:15.001 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:15.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:15.001 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:15.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:15.001 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:15.003 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:15.003 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:15.003 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:15.003 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:15.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:15.003 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:15.004 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:15.004 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.007 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:22:15.007 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:22:15.007 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:15.007 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:15.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:15.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:15.012 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:15.489 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:15.530 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:15.531 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:15.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:15.533 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:15.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:15.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:15.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:22:15.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:15.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:15.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:15.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:22:15.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:22:15.961 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:16.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:16.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:16.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:16.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:16.433 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:16.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:16.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:16.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:16.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:16.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:16.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:16.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:22:16.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:16.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:16.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:16.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:22:16.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:22:16.904 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:17.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:17.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:17.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:17.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:17.376 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:17.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:17.849 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:17.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:17.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:17.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:17.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:17.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:17.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:17.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:17.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:17.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:17.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:17.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:17.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:17.895 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:17.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:22.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:22.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:22.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:22.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:22.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:22.907 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:22.908 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:22.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:22.908 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:22.910 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:22.910 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:22.910 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:22.910 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:22.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:22.910 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:22.911 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:22.911 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:22.912 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:22.912 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:22.913 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:22.913 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:22.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:22.913 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:22.913 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:22.913 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:22.915 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:22.915 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:22.915 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:22.915 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:22.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:22.915 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:22.915 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:22.915 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:22.919 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:22.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:22.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:22.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:22.919 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:22.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:22:22.920 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:22:22.920 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:22.920 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:22.925 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:23.404 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:23.453 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:23.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:23.456 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:23.458 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:23.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:23.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:23.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:22:23.876 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:23.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:23.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:23.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:23.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:24.351 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:24.823 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:24.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:24.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:24.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:24.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:25.298 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:25.770 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:25.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:25.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:25.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:25.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:26.246 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:22:26.717 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:22:26.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:26.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:26.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:26.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:27.194 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:22:27.665 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:22:27.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:27.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:27.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:27.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:28.141 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:22:28.613 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:22:29.088 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:22:29.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:29.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:29.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:29.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:22:29.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:22:29.560 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:22:29.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:29.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:29.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:29.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:29.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:30.034 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:22:30.507 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:22:30.981 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:22:31.455 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:22:31.929 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:22:32.400 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:22:32.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:32.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:32.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:32.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:32.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:32.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:32.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:32.551 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:32.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:32.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:32.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:32.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:32.551 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:37.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:37.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:37.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:37.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:37.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:37.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:37.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:37.569 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:37.569 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:37.569 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:37.569 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:37.573 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:37.573 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:37.574 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:37.574 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:37.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:37.575 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:37.575 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:37.575 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:37.577 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:37.577 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:37.577 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:37.577 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:37.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:37.578 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:37.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:37.578 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:37.579 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:37.579 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:37.580 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:37.580 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:37.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:37.580 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:37.580 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:37.580 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.583 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:22:37.583 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:22:37.583 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:37.583 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:37.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:37.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:37.588 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:38.066 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:38.111 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:38.113 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:38.115 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:38.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:38.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:38.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:38.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:22:38.538 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:38.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:38.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:38.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:38.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:39.013 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:39.485 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:39.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:39.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:39.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:39.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:39.960 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:40.432 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:40.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:40.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:40.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:40.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:40.908 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:22:41.379 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:22:41.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:41.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:41.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:41.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:41.855 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:22:42.327 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:22:42.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:42.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:42.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:42.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:42.802 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:22:43.274 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:22:43.750 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:22:44.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:44.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:44.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:44.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:22:44.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:22:44.222 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:22:44.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:44.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:44.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:44.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:44.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:44.696 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:22:45.168 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:22:45.643 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:22:46.115 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:22:46.590 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:22:47.062 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:22:47.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:47.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:47.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:47.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:47.214 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:47.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:47.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:47.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:47.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:47.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:47.214 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:22:47.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:47.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:52.221 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:22:52.221 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:22:52.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:52.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:52.221 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:52.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:52.229 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:22:52.230 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:52.230 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:52.230 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:22:52.230 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:22:52.234 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:22:52.235 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:22:52.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:52.235 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:52.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:22:52.236 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:22:52.237 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:22:52.237 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:22:52.239 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:22:52.239 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:22:52.239 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:52.240 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:52.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:22:52.240 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:22:52.240 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:22:52.240 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:22:52.242 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:22:52.242 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:22:52.242 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:52.243 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:22:52.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:22:52.243 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:22:52.243 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:22:52.243 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:22:52.246 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:22:52.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:22:52.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:22:52.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:22:52.246 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:22:52.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:22:52.247 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:22:52.247 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:22:52.247 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:22:52.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:22:52.252 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:22:52.730 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:22:52.776 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:22:52.778 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:22:52.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:22:52.780 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:22:52.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:22:52.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:22:52.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:22:53.202 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:22:53.250 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:53.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:53.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:53.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:53.677 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:22:54.149 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:22:54.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:54.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:54.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:54.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:54.624 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:22:55.096 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:22:55.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:55.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:55.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:55.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:55.571 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:22:56.043 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:22:56.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:56.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:56.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:56.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:56.517 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:22:56.989 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:22:57.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:22:57.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:22:57.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:22:57.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:22:57.461 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:22:57.935 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:22:58.407 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:22:58.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:58.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:58.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:58.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:22:58.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:22:58.879 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:22:58.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:22:58.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:22:58.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:22:58.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:58.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:22:59.353 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:22:59.825 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:00.297 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:00.771 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:23:01.244 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:23:01.716 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:23:01.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:01.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:23:01.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:01.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:01.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:01.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:01.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:01.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:01.871 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:01.871 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:01.871 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:01.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:01.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:06.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:06.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:06.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:06.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:06.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:06.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:06.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:06.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:06.887 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:06.888 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:06.888 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:06.890 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:06.891 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:06.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:06.891 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:06.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:06.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:06.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:06.892 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:06.893 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:06.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:06.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:06.893 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:06.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:06.893 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:06.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:06.894 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:06.895 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:06.896 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:06.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:06.896 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:06.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:06.896 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:06.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:06.896 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:06.898 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:23:06.899 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:23:06.899 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:06.899 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:06.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:06.904 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:23:07.381 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:23:07.428 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:23:07.431 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:23:07.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:23:07.433 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:23:07.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:07.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:23:07.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:23:07.853 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:23:07.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:07.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:07.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:07.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:08.327 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:23:08.799 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:23:08.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:08.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:08.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:08.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:09.271 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:23:09.745 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:23:09.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:09.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:09.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:09.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:10.217 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:23:10.689 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:23:10.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:10.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:10.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:10.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:11.160 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:23:11.635 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:23:11.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:11.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:11.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:11.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:12.108 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:23:12.582 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:23:13.054 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:23:13.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:13.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:13.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:13.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:23:13.468 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:23:13.529 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:23:13.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:23:13.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:13.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:13.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:13.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:14.001 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:23:14.472 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:14.947 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:15.419 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:23:15.888 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:23:16.362 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:23:16.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:16.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:23:16.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:16.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:16.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:16.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:16.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:16.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:16.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:16.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:16.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:16.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:16.521 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:16.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2076 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:16.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2076 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:16.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2076 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:16.521 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2076 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:21.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:21.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:21.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:21.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:21.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:21.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:21.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:21.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:21.536 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:21.537 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:21.537 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:21.541 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:21.541 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:21.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:21.542 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:21.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:21.542 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:21.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:21.543 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:21.546 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:21.546 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:21.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:21.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:21.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:21.547 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:21.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:21.547 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:21.550 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:21.550 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:21.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:21.551 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:21.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:21.551 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:21.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:21.551 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.555 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:23:21.555 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:23:21.555 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:21.556 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:21.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:21.560 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:23:22.036 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:23:22.087 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:23:22.089 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:23:22.091 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:23:22.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:23:22.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:22.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:23:22.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:23:22.508 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:23:22.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:22.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:22.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:22.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:22.984 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:23:23.455 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:23:23.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:23.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:23.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:23.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:23.930 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:23:24.402 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:23:24.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:24.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:24.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:24.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:24.878 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:23:25.350 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:23:25.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:25.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:25.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:25.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:25.825 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:23:26.297 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:23:26.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:26.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:26.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:26.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:26.772 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:23:27.244 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:23:27.719 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:23:28.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:28.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:28.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:28.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:23:28.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:23:28.191 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:23:28.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD NOHANDOVER
2026-01-29 03:23:28.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:28.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:28.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:28.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:28.665 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:23:29.136 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:29.608 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:30.079 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:23:30.552 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:23:31.026 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:23:31.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:31.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:23:31.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:31.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:31.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:31.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:31.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:31.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:31.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:31.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:31.192 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:31.192 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:31.192 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:36.197 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:36.197 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:36.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:36.197 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:36.197 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:36.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:36.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:36.208 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:36.208 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:36.208 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:36.208 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:36.212 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:36.212 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:36.212 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:36.213 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:36.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:36.213 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:36.214 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:36.214 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:36.215 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:36.216 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:36.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:36.216 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:36.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:36.216 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:36.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:36.217 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:36.218 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:36.218 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:36.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:36.218 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:36.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:36.219 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:36.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:36.219 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:23:36.222 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:23:36.222 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:36.222 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:36.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:36.227 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:23:36.704 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:23:36.750 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:23:36.752 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:23:36.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:23:36.754 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:23:37.176 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:23:37.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:37.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:37.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:37.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:37.651 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:23:38.123 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:23:38.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:38.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:38.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:38.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:38.598 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:23:39.070 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:23:39.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:39.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:39.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:39.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:39.544 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:23:40.016 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:23:40.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:40.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:40.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:40.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:40.488 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:23:40.962 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:23:41.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:41.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:41.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:41.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:41.434 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:23:41.906 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:23:42.382 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:23:42.854 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:23:43.329 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:23:43.801 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:23:44.275 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:23:44.747 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:23:45.219 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:23:45.694 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:23:46.166 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:23:46.642 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:23:46.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:46.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:46.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:46.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:46.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:46.767 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:46.767 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:46.767 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:46.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:46.767 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:46.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:46.767 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2273 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:46.767 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2273 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:46.767 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2273 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:46.767 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2273 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:46.767 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2273 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:46.767 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2273 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:46.767 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2273 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:23:51.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:51.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:51.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:51.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:51.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:51.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:51.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:51.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:51.783 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:51.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:51.783 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:51.788 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:51.788 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:51.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:51.788 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:51.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:51.789 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:51.789 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:51.789 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:51.793 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:51.793 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:51.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:51.793 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:51.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:51.794 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:51.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:51.794 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:51.798 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:51.798 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:51.798 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:51.798 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:51.798 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:51.798 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:51.798 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:51.798 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:51.804 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:51.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:51.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:51.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:51.804 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:51.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:23:51.805 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:23:51.805 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:51.805 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:51.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:51.808 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:51.808 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:51.808 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:56.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:23:56.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:23:56.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:56.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:56.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:56.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:56.824 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:23:56.825 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:56.825 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:56.826 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:23:56.826 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:23:56.830 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:23:56.831 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:23:56.831 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:56.831 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:56.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:23:56.831 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:23:56.831 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:23:56.831 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:23:56.835 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:23:56.835 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:23:56.836 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:56.836 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:56.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:23:56.836 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:23:56.836 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:23:56.836 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:23:56.840 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:23:56.840 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:23:56.840 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:56.840 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:23:56.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:23:56.840 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:23:56.840 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:23:56.840 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:23:56.846 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:23:56.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:23:56.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:23:56.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:23:56.846 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:23:56.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:23:56.847 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:23:56.847 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:23:56.847 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:23:56.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:23:56.852 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:23:57.328 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:23:57.383 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:23:57.385 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:23:57.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:23:57.387 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:23:57.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:23:57.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:23:57.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:23:57.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:23:57.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:23:57.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:23:57.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:23:57.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:23:57.799 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:23:57.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:57.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:57.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:57.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:58.272 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:23:58.743 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:23:58.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:58.853 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:58.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:58.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:23:59.215 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:23:59.688 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:23:59.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:23:59.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:23:59.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:23:59.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:00.160 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:24:00.632 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:24:00.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:00.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:00.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:00.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:01.103 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:24:01.577 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:24:01.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:01.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:01.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:01.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:02.049 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:24:02.522 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:24:02.995 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:24:03.468 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:24:03.940 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:24:04.411 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:24:04.884 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:24:05.357 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:24:05.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:05.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:24:05.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:05.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:05.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:05.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:05.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:05.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:05.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:05.436 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:05.436 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:05.436 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:05.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:05.436 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:05.437 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:05.437 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:05.437 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:05.437 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:05.437 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:05.437 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:10.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:10.437 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:10.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:10.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:10.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:10.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:10.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:10.448 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:10.449 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:10.449 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:10.449 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:10.455 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:10.455 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:10.455 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:10.456 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:10.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:10.456 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:10.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:10.457 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:10.459 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:10.460 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:10.460 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:10.460 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:10.460 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:10.461 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:10.461 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:10.461 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:10.463 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:10.463 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:10.463 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:10.463 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:10.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:10.463 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:10.464 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:10.464 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:10.467 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:24:10.467 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:24:10.467 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:10.468 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:10.469 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:10.469 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:10.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:10.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.481 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:15.481 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:15.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:15.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:15.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:15.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:15.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:15.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:15.492 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:15.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:15.493 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:15.496 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:15.497 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:15.497 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:15.497 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:15.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:15.498 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:15.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:15.498 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:15.500 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:15.501 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:15.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:15.501 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:15.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:15.501 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:15.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:15.502 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:15.503 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:15.503 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:15.503 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:15.503 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:15.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:15.504 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:15.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:15.504 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.507 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:24:15.507 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:24:15.508 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:15.508 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:15.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:15.512 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:24:15.990 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:24:16.039 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:24:16.041 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:24:16.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:24:16.043 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:24:16.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:16.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:24:16.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:24:16.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:24:16.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:24:16.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:24:16.049 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:24:16.049 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:24:16.462 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:24:16.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:16.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:16.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:16.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:16.934 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:24:17.407 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:24:17.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:17.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:17.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:17.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:17.879 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:24:18.352 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:24:18.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:18.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:18.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:18.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:18.823 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:24:19.296 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:24:19.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:19.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:19.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:19.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:19.769 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:24:20.241 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:24:20.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:20.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:20.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:20.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:20.714 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:24:21.187 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:24:21.658 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:24:22.130 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:24:22.600 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:24:23.074 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:24:23.546 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:24:24.018 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:24:24.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:24.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:24:24.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:24.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:24.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:24.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:24.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:24.093 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:24.093 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:24.093 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:24.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:24.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:24.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:24.093 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:24.093 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:24.093 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:24.093 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:24.093 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:24.093 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:29.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:29.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:29.103 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:29.103 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:29.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:29.103 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:29.116 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:29.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:29.117 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:29.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:29.118 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:29.121 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:29.121 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:29.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:29.121 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:29.122 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:29.122 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:29.122 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:29.122 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:29.124 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:29.124 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:29.124 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:29.124 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:29.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:29.124 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:29.125 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:29.125 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:29.126 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:29.126 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:29.126 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:29.126 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:29.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:29.126 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:29.126 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:29.126 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:24:29.129 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:24:29.129 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:29.129 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:29.131 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:29.131 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:29.131 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:34.138 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:34.138 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:34.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:34.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:34.138 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:34.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:34.146 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:34.147 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:34.147 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:34.147 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:34.148 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:34.150 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:34.150 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:34.151 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:34.151 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:34.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:34.151 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:34.152 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:34.152 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:34.153 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:34.153 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:34.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:34.154 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:34.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:34.154 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:34.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:34.155 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:34.156 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:34.156 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:34.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:34.156 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:34.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:34.156 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:34.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:34.156 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.159 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:24:34.159 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:24:34.159 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:34.159 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:34.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:34.164 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:24:34.643 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:24:34.680 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:24:34.682 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:24:34.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:24:34.684 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:24:34.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:34.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:24:34.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:24:34.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:24:34.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:24:34.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:24:34.687 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:24:34.687 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:24:35.114 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:24:35.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:35.162 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:35.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:35.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:35.586 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:24:36.057 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:24:36.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:36.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:36.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:36.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:36.530 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:24:37.003 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:24:37.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:37.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:37.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:37.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:37.475 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:24:37.948 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:24:38.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:38.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:38.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:38.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:38.421 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:24:38.893 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:24:39.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:39.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:39.167 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:39.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:39.364 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:24:39.837 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:24:40.310 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:24:40.782 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:24:41.253 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:24:41.726 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:24:42.199 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:24:42.671 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:24:42.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:42.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:24:42.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:42.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:42.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:42.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:42.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:42.744 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:42.744 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:42.744 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:42.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:42.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:42.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:42.745 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:24:47.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:47.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:47.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:47.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:47.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:47.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:47.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:47.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:47.760 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:47.761 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:47.761 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:47.765 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:47.766 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:47.766 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:47.766 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:47.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:47.767 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:47.768 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:47.768 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:47.769 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:47.770 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:47.770 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:47.770 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:47.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:47.770 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:47.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:47.771 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:47.773 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:47.773 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:47.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:47.773 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:47.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:47.773 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:47.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:47.774 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:24:47.777 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:24:47.777 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:47.777 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:47.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:47.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:47.779 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:47.779 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:47.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:24:52.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:24:52.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:52.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:52.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:52.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:52.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:24:52.796 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:52.796 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:52.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:24:52.797 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:24:52.800 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:24:52.801 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:24:52.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:52.801 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:52.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:24:52.802 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:24:52.803 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:24:52.803 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:24:52.805 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:24:52.805 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:24:52.805 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:52.805 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:52.806 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:24:52.806 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:24:52.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:24:52.806 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:24:52.808 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:24:52.808 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:24:52.808 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:52.808 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:24:52.808 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:24:52.808 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:24:52.808 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:24:52.808 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:24:52.812 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:24:52.812 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:24:52.812 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:24:52.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:24:52.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:24:52.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:24:52.817 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:24:53.295 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:24:53.336 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:24:53.338 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:24:53.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:24:53.339 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:24:53.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:24:53.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:24:53.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:24:53.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:24:53.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:24:53.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:24:53.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:24:53.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:24:53.767 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:24:53.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:53.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:53.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:53.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:54.238 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:24:54.709 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:24:54.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:54.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:54.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:54.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:55.180 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:24:55.653 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:24:55.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:55.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:55.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:55.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:56.125 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:24:56.597 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:24:56.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:56.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:56.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:56.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:57.068 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:24:57.542 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:24:57.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:24:57.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:24:57.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:24:57.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:24:58.014 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:24:58.486 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:24:58.959 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:24:59.432 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:24:59.904 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:25:00.375 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:25:00.848 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:25:01.321 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:25:01.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:01.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:25:01.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:01.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:01.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:01.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:01.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:01.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:01.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:01.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:01.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:01.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:01.399 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.400 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:01.401 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:25:06.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:06.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:06.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:06.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:06.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:06.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:06.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:06.409 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:06.409 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:06.410 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:06.410 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:06.414 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:06.415 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:06.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:06.415 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:06.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:06.417 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:06.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:06.417 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:06.420 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:06.420 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:06.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:06.421 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:06.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:06.421 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:06.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:06.422 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:06.424 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:06.424 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:06.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:06.425 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:06.425 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:06.425 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:06.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:06.425 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.429 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:25:06.429 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:25:06.429 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:06.429 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:06.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:06.432 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:06.432 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:06.432 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:06.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:06.432 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:11.438 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:11.438 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:11.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:11.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:11.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:11.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:11.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:11.448 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:11.448 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:11.448 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:11.448 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:11.451 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:11.451 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:11.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:11.452 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:11.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:11.452 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:11.453 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:11.453 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:11.454 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:11.454 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:11.454 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:11.454 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:11.454 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:11.454 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:11.455 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:11.455 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:11.456 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:11.457 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:11.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:11.457 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:11.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:11.457 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:11.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:11.457 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.461 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:25:11.461 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:25:11.462 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:11.462 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:11.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:11.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:25:11.943 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:25:11.989 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:25:11.991 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:25:11.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:25:11.993 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:25:11.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:11.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:25:11.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:25:11.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:25:11.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:25:11.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:25:11.997 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:25:11.998 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:25:12.415 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:25:12.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:12.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:12.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:12.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:12.887 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:25:13.360 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:25:13.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:13.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:13.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:13.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:13.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:25:14.305 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:25:14.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:14.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:14.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:14.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:14.776 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:25:15.249 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:25:15.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:15.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:15.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:15.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:15.722 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:25:16.194 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:25:16.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:16.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:16.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:16.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:16.665 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:25:17.138 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:25:17.610 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:25:18.083 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:25:18.553 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:25:19.024 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:25:19.495 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:25:19.969 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:25:20.441 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:25:20.913 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:25:21.384 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:25:21.857 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:25:22.330 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:25:22.802 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:25:23.273 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:25:23.746 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:25:24.219 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:25:24.691 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:25:25.162 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:25:25.633 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:25:26.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:26.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:25:26.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:26.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:26.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:26.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:26.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:26.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:26.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:26.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:26.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:26.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:26.043 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:31.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:31.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:31.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:31.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:31.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:31.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:31.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:31.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:31.059 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:31.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:31.060 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:31.062 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:31.062 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:31.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:31.063 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:31.063 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:31.063 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:31.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:31.064 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:31.065 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:31.065 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:31.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:31.066 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:31.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:31.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:31.067 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:31.067 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:31.068 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:31.068 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:31.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:31.068 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:31.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:31.068 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:31.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:31.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:25:31.071 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:25:31.071 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:31.071 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:31.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:31.073 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:31.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:31.073 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:36.081 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:36.081 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:36.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:36.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:36.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:36.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:36.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:36.088 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:36.088 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:36.088 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:36.088 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:36.091 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:36.091 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:36.092 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:36.092 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:36.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:36.092 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:36.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:36.093 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:36.094 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:36.094 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:36.095 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:36.095 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:36.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:36.095 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:36.095 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:36.095 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:36.097 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:36.097 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:36.097 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:36.097 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:36.097 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:36.097 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:36.097 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:36.097 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:25:36.101 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:25:36.101 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:36.101 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:36.105 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:25:36.583 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:25:36.625 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:25:36.627 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:25:36.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:25:36.628 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:25:36.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:36.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:25:36.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:25:36.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:25:36.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:25:36.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:25:36.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:25:36.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:25:37.055 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:25:37.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:37.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:37.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:37.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:37.527 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:25:37.998 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:25:38.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:38.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:38.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:38.471 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:25:38.944 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:25:39.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:39.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:39.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:39.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:39.416 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:25:39.887 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:25:40.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:40.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:40.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:40.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:40.360 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:25:40.832 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:25:41.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:41.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:41.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:41.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:41.304 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:25:41.775 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:25:42.246 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:25:42.719 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:25:43.192 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:25:43.663 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:25:44.135 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:25:44.608 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:25:44.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:44.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:25:44.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:44.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:44.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:44.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:44.686 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:44.686 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:44.686 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:44.686 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:44.686 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:44.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:44.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:49.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:49.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:49.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:49.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:49.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:49.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:49.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:49.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:49.694 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:49.694 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:49.694 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:49.695 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:49.695 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:49.695 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:49.695 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:49.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:49.695 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:49.695 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:49.696 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:49.696 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:49.696 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:49.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:49.696 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:49.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:49.697 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:49.697 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:49.697 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:49.698 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:49.698 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:49.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:49.698 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:49.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:49.698 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:49.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:49.698 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:25:49.700 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:25:49.700 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:49.700 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:49.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:49.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:49.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:49.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:49.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:49.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:49.702 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:25:54.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:25:54.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:25:54.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:54.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:54.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:54.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:54.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:25:54.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:54.721 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:54.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:25:54.722 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:25:54.726 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:25:54.726 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:25:54.727 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:54.727 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:54.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:25:54.728 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:25:54.728 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:25:54.728 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:25:54.730 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:25:54.730 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:25:54.730 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:54.730 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:54.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:25:54.731 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:25:54.731 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:25:54.731 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:25:54.733 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:25:54.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:25:54.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:54.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:25:54.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:25:54.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:25:54.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:25:54.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:25:54.737 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:25:54.737 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:25:54.737 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:25:54.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:25:54.742 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:25:55.220 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:25:55.259 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:25:55.260 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:25:55.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:25:55.262 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:25:55.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:25:55.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:25:55.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:25:55.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:25:55.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:25:55.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:25:55.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:25:55.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:25:55.692 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:25:55.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:55.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:55.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:55.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:56.163 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:25:56.634 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:25:56.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:56.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:56.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:56.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:57.108 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:25:57.580 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:25:57.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:57.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:57.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:57.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:58.052 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:25:58.523 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:25:58.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:58.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:58.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:58.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:58.997 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:25:59.469 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:25:59.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:25:59.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:25:59.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:25:59.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:25:59.941 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:26:00.412 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:26:00.885 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:26:01.358 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:26:01.830 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:26:02.301 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:26:02.774 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:26:03.246 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:26:03.719 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:26:04.189 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:26:04.663 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:26:05.135 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:26:05.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:05.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:26:05.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:05.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:05.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:05.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:05.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:05.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:05.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:05.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:05.324 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:05.324 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:05.324 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:10.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:10.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:10.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:10.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:10.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:10.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:10.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:10.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:10.338 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:10.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:10.338 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:10.341 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:10.341 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:10.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:10.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:10.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:10.342 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:10.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:10.343 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:10.344 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:10.344 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:10.345 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:10.345 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:10.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:10.345 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:10.345 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:10.345 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:10.347 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:10.347 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:10.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:10.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:10.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:10.347 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:10.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:10.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:10.350 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:26:10.350 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:26:10.350 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:10.350 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:10.352 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:10.352 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:10.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:15.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:15.358 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:15.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:15.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:15.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:15.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:15.368 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:15.368 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:15.369 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:15.369 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:15.372 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:15.372 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:15.373 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:15.373 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:15.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:15.374 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:15.374 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:15.374 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:15.376 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:15.376 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:15.377 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:15.377 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:15.377 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:15.377 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:15.377 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:15.377 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:15.379 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:15.379 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:15.379 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:15.379 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:15.379 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:15.380 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:15.380 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:15.380 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.383 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:26:15.383 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:26:15.383 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:15.384 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:15.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:15.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:15.388 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:26:15.867 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:26:15.908 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:26:15.910 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:26:15.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:26:15.912 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:26:15.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:15.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:26:15.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:26:15.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:26:15.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:26:15.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:26:15.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:26:15.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:26:16.340 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:26:16.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:16.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:16.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:16.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:16.813 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:26:17.285 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:26:17.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:17.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:17.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:17.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:17.757 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:26:18.228 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:26:18.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:18.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:18.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:18.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:18.702 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:26:19.174 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:26:19.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:19.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:19.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:19.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:19.646 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:26:20.119 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:26:20.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:20.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:20.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:20.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:20.592 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:26:21.064 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:26:21.538 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:26:22.010 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:26:22.482 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:26:22.953 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:26:23.426 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:26:23.898 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:26:24.371 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:26:24.844 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:26:25.316 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:26:25.788 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:26:26.260 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:26:26.733 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:26:26.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:26.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:26:26.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:26.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:26.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:26.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:26.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:26.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:26.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:26.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:26.972 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:26.972 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:26.972 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:26.972 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2502 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:26.972 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:26.972 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:26.972 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:26.972 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:26.973 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:31.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:31.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:31.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:31.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:31.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:31.974 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:31.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:31.982 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:31.982 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:31.982 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:31.982 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:31.987 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:31.987 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:31.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:31.987 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:31.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:31.987 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:31.988 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:31.988 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:31.991 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:31.991 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:31.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:31.992 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:31.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:31.992 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:31.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:31.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:31.995 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:31.996 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:31.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:31.996 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:31.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:31.996 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:31.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:31.996 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:32.002 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:32.002 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:32.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:32.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:26:32.003 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:26:32.003 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:32.003 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:32.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:32.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:32.006 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:32.006 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:32.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:37.013 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:37.013 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:37.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:37.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:37.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:37.022 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:37.022 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:37.023 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:26:37.023 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:26:37.027 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:26:37.027 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:26:37.027 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:37.027 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:37.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:37.027 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:26:37.028 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:26:37.028 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:26:37.031 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:26:37.031 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:26:37.032 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:37.032 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:37.032 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:37.032 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:26:37.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:26:37.033 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:26:37.034 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:26:37.034 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:26:37.035 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:37.035 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:26:37.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:37.035 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:26:37.035 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:26:37.035 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:26:37.038 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:26:37.039 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:26:37.039 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:26:37.039 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:26:37.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:26:37.044 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:26:37.522 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:26:37.561 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:26:37.562 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:26:37.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:26:37.564 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:26:37.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:37.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:26:37.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:26:37.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:26:37.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:26:37.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:26:37.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:26:37.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:26:37.994 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:26:38.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:38.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:38.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:38.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:38.465 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:26:38.936 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:26:39.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:39.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:39.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:39.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:39.410 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:26:39.882 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:26:40.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:40.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:40.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:40.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:40.354 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:26:40.825 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:26:41.045 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:41.299 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:26:41.771 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:26:42.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:42.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:42.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:42.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:42.242 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:26:42.714 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:26:43.185 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:26:43.656 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:26:44.129 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:26:44.601 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:26:45.074 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:26:45.547 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:26:46.019 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:26:46.491 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:26:46.962 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:26:47.436 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:26:47.908 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:26:48.380 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:26:48.851 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:26:49.325 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:26:49.797 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:26:50.269 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:26:50.740 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:26:51.214 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:26:51.686 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:26:52.158 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:26:52.629 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:26:53.102 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:26:53.575 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:26:54.047 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:26:54.518 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:26:54.991 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:26:55.463 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:26:55.936 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:26:56.409 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:26:56.881 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:26:57.354 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:26:57.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:26:57.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:26:57.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:26:57.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:26:57.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:26:57.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:26:57.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:26:57.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:26:57.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:26:57.633 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:26:57.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:26:57.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:26:57.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:26:57.634 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:57.634 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:57.634 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:57.634 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:57.635 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:57.635 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:26:57.635 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4448 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:02.635 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:02.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:02.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:02.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:02.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:02.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:02.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:02.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:02.650 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:02.650 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:02.650 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:02.652 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:02.653 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:02.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:02.653 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:02.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:02.653 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:02.654 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:02.654 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:02.655 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:02.655 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:02.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:02.655 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:02.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:02.655 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:02.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:02.655 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:02.657 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:02.657 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:02.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:02.657 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:02.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:02.657 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:02.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:02.657 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:27:02.659 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:27:02.659 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:02.659 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:02.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:02.661 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:02.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:07.668 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:07.668 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:07.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:07.668 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:07.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:07.668 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:07.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:07.671 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:07.671 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:07.672 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:07.672 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:07.672 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:07.672 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:07.673 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:07.673 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:07.673 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:07.673 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:07.673 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:07.673 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:07.674 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:07.674 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:07.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:07.674 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:07.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:07.674 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:07.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:07.674 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:07.675 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:07.675 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:07.675 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:07.675 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:07.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:07.675 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:07.675 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:07.675 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:27:07.677 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:27:07.677 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:07.677 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:07.682 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:27:08.159 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:27:08.198 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:27:08.200 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:27:08.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:27:08.202 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:27:08.631 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:27:08.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:08.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:08.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:08.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:09.107 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:27:09.579 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:27:09.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:09.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:09.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:09.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:10.054 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:27:10.528 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:27:10.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:10.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:10.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:10.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:11.002 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:27:11.474 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:27:11.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:11.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:11.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:11.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:11.949 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:27:12.421 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:27:12.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:12.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:12.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:12.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:12.896 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:27:13.368 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:27:13.844 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:27:14.316 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:27:14.791 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:27:15.263 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:27:15.739 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:27:16.211 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:27:16.686 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:27:17.157 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:27:17.633 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:27:18.105 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:27:18.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:18.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:18.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:18.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:18.212 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:18.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:18.212 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:18.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:18.212 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:18.212 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:18.212 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:23.218 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:23.218 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:23.218 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:23.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:23.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:23.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:23.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:23.229 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:23.229 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:23.229 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:23.229 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:23.233 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:23.234 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:23.234 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:23.234 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:23.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:23.235 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:23.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:23.236 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:23.237 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:23.238 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:23.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:23.238 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:23.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:23.238 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:23.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:23.238 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:23.240 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:23.240 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:23.240 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:23.240 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:23.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:23.241 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:23.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:23.241 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:23.244 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:23.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:23.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:23.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:27:23.245 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:27:23.245 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:23.245 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:23.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:23.247 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:23.247 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:23.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.253 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:28.253 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:28.253 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:28.253 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:28.253 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:28.253 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:28.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:28.262 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:28.262 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:28.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:28.263 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:28.266 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:28.266 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:28.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:28.266 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:28.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:28.267 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:28.267 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:28.267 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:28.268 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:28.268 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:28.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:28.269 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:28.269 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:28.269 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:28.269 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:28.269 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:28.271 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:28.271 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:28.271 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:28.271 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:28.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:28.271 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:28.271 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:28.271 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:28.273 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:28.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:28.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:28.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:27:28.274 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:27:28.274 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:28.274 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:28.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:28.279 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:27:28.756 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:27:28.800 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:27:28.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:27:28.803 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:27:28.807 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:27:29.228 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:27:29.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:29.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:29.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:29.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:29.703 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:27:30.175 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:27:30.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:30.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:30.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:30.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:30.650 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:27:31.122 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:27:31.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:31.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:31.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:31.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:31.598 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:27:32.070 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:27:32.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:32.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:32.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:32.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:32.545 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:27:33.017 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:27:33.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:33.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:33.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:33.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:33.492 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:27:33.964 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:27:34.440 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:27:34.913 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:27:35.387 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:27:35.859 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:27:36.334 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:27:36.806 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:27:37.282 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:27:37.754 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:27:38.229 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:27:38.707 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:27:39.183 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:27:39.655 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:27:40.130 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:27:40.602 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:27:40.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:40.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:40.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:40.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:40.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:40.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:40.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:40.823 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:40.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:40.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:40.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:40.823 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2702 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:40.823 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2702 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:40.823 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2702 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:40.823 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2702 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:40.823 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2702 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:40.823 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2702 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:45.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:45.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:45.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:45.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:45.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:45.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:45.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:45.839 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:45.840 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:45.840 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:45.840 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:45.846 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:45.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:45.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:45.847 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:45.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:45.847 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:45.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:45.847 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:45.852 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:45.852 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:45.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:45.852 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:45.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:45.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:45.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:45.853 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:45.856 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:45.856 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:45.856 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:45.856 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:45.856 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:45.856 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:45.857 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:45.857 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:27:45.861 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:27:45.861 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:45.861 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:45.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:45.863 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:45.863 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:45.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:50.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:50.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:50.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:50.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:50.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:50.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:50.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:50.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:50.881 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:50.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:27:50.882 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:27:50.887 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:27:50.887 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:27:50.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:50.888 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:50.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:50.888 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:27:50.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:27:50.889 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:27:50.891 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:27:50.892 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:27:50.892 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:50.892 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:50.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:50.892 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:27:50.892 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:27:50.892 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:27:50.895 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:27:50.895 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:27:50.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:50.895 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:27:50.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:50.895 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:27:50.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:27:50.895 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:27:50.899 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:27:50.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:27:50.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:27:50.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:27:50.900 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:27:50.900 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:27:50.900 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:27:50.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:27:50.905 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:27:51.383 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:27:51.432 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:27:51.434 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:27:51.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:27:51.436 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:27:51.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:27:51.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:27:51.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:27:51.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:51.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:27:51.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:27:51.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:27:51.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:27:51.473 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:27:51.473 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:27:51.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:51.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:27:51.855 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:27:51.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:51.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:51.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:51.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:52.328 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:27:52.801 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:27:52.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:52.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:52.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:52.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:53.274 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:27:53.747 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:27:53.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:53.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:53.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:53.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:54.220 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:27:54.692 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:27:54.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:54.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:54.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:54.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:55.165 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:27:55.638 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:27:55.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:55.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:55.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:55.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:56.110 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:27:56.583 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:27:57.055 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:27:57.527 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:27:57.999 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:27:58.472 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:27:58.945 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:27:59.417 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:27:59.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:27:59.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:27:59.478 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:27:59.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:27:59.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:27:59.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:27:59.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:27:59.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:27:59.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:27:59.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:27:59.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:27:59.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:27:59.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:27:59.485 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:27:59.485 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:04.489 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:04.489 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:04.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:04.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:04.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:04.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:04.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:04.500 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:04.501 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:04.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:04.501 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:04.506 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:04.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:04.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:04.507 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:04.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:04.508 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:04.509 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:04.509 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:04.511 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:04.511 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:04.511 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:04.512 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:04.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:04.512 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:04.513 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:04.513 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:04.514 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:04.514 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:04.514 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:04.514 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:04.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:04.515 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:04.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:04.515 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:04.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:28:04.519 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:28:04.519 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:04.519 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:04.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:04.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:04.520 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:04.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:04.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:09.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:09.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:09.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:09.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:09.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:09.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:09.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:09.533 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:09.533 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:09.533 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:09.533 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:09.536 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:09.536 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:09.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:09.536 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:09.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:09.537 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:09.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:09.537 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:09.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:09.539 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:09.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:09.539 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:09.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:09.539 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:09.539 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:09.539 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:09.541 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:09.541 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:09.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:09.541 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:09.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:09.541 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:09.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:09.541 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:09.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:28:09.545 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:28:09.545 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:09.545 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:09.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:09.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:09.549 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:28:10.028 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:28:10.065 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:28:10.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:28:10.068 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:28:10.072 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:28:10.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:10.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:28:10.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:28:10.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:10.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:28:10.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:28:10.074 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:28:10.075 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:28:10.119 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:28:10.119 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:28:10.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:10.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:10.500 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:28:10.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:10.973 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:28:11.446 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:28:11.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:11.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:11.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:11.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:11.918 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:28:12.390 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:28:12.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:12.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:12.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:12.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:12.863 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:28:13.336 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:28:13.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:13.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:13.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:13.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:13.815 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:28:14.287 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:28:14.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:14.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:14.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:14.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:14.761 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:28:15.233 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:28:15.705 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:28:16.179 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:28:16.651 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:28:17.123 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:28:17.594 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:28:18.068 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:28:18.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:18.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:28:18.123 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:28:18.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:18.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:18.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:18.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:18.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:18.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:18.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:18.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:18.133 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:18.133 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:18.133 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1852 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1852 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1852 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1852 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1852 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.134 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.135 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.135 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:18.135 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:23.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:23.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:23.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:23.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:23.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:23.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:23.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:23.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:23.138 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:23.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:23.138 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:23.139 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:23.139 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:23.139 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:23.139 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:23.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:23.140 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:23.140 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:23.140 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:23.140 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:23.140 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:23.140 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:23.140 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:23.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:23.140 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:23.141 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:23.141 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:23.142 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:23.142 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:23.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:23.142 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:23.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:23.142 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:23.142 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:23.142 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:28:23.144 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:28:23.144 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:23.144 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:23.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:23.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:23.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:23.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:23.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:23.145 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:23.145 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:23.145 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:28.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:28.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:28.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:28.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:28.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:28.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:28.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:28.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:28.162 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:28.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:28.163 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:28.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:28.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:28.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:28.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:28.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:28.168 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:28.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:28.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:28.171 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:28.171 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:28.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:28.172 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:28.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:28.172 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:28.173 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:28.173 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:28.175 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:28.175 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:28.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:28.176 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:28.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:28.176 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:28.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:28.176 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:28.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:28:28.182 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:28:28.182 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:28.182 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:28.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:28.187 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:28:28.665 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:28:28.719 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:28:28.722 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:28:28.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:28:28.724 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:28:28.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:28.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:28:28.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:28:28.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:28.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:28:28.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:28:28.728 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:28:28.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:28:28.755 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:28:28.755 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:28:28.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:28.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:29.137 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:28:29.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:29.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:29.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:29.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:29.608 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:28:30.082 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:28:30.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:30.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:30.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:30.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:30.554 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:28:31.025 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:28:31.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:31.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:31.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:31.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:31.498 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:28:31.971 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:28:32.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:32.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:32.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:32.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:32.443 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:28:32.915 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:28:33.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:33.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:33.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:33.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:33.389 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:28:33.863 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:28:34.336 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:28:34.808 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:28:35.280 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:28:35.751 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:28:36.225 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:28:36.697 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:28:36.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:36.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:28:36.760 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:28:36.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:36.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:36.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:36.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:36.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:36.770 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:36.770 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:36.770 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:36.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:36.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:36.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:36.771 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:36.771 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:36.771 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:36.771 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:36.772 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:36.772 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:36.772 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1853 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:28:41.772 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:41.772 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:41.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:41.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:41.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:41.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:41.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:41.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:41.775 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:41.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:41.775 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:41.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:41.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:41.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:41.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:41.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:41.776 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:41.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:41.776 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:41.777 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:41.778 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:41.778 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:41.778 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:41.778 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:41.778 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:41.778 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:41.778 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:41.779 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:41.779 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:41.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:41.779 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:41.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:41.779 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:41.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:41.779 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:28:41.781 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:28:41.781 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:41.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:41.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:41.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:41.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:41.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:41.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:41.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:41.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:41.783 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:28:46.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:46.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:46.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:46.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:46.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:46.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:46.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:46.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:46.800 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:46.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:28:46.800 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:28:46.803 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:28:46.804 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:28:46.804 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:46.804 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:46.804 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:46.805 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:28:46.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:28:46.805 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:28:46.806 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:28:46.807 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:28:46.807 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:46.807 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:46.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:46.807 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:28:46.807 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:28:46.807 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:28:46.809 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:28:46.809 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:28:46.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:46.809 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:28:46.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:46.809 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:28:46.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:28:46.809 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:28:46.812 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:28:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:28:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:28:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:28:46.812 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:28:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:28:46.813 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:28:46.813 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:28:46.813 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:28:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:28:46.818 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:28:47.296 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:28:47.339 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:28:47.341 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:28:47.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:28:47.344 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:28:47.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:47.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:28:47.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:28:47.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:47.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:28:47.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:28:47.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:28:47.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:28:47.386 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:28:47.386 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:28:47.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:47.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:28:47.768 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:28:47.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:47.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:47.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:47.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:48.239 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:28:48.713 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:28:48.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:48.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:48.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:48.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:49.184 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:28:49.656 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:28:49.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:49.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:49.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:49.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:50.129 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:28:50.600 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:28:50.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:50.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:50.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:50.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:51.073 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:28:51.545 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:28:51.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:51.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:51.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:51.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:52.018 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:28:52.491 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:28:52.963 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:28:53.437 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:28:53.909 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:28:54.381 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:28:54.853 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:28:55.326 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:28:55.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:28:55.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:28:55.390 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:28:55.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:28:55.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:28:55.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:28:55.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:28:55.397 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:28:55.397 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:28:55.397 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:28:55.397 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:28:55.397 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:28:55.397 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:28:55.397 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:00.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:00.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:00.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:00.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:00.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:00.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:00.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:00.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:00.413 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:00.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:00.413 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:00.416 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:00.417 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:00.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:00.417 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:00.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:00.418 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:00.418 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:00.419 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:00.420 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:00.420 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:00.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:00.421 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:00.421 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:00.421 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:00.421 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:00.421 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:00.423 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:00.423 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:00.423 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:00.423 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:00.423 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:00.424 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:00.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:00.424 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.427 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:29:00.427 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:29:00.427 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:00.427 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:00.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:00.429 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:00.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:05.436 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:05.436 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:05.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:05.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:05.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:05.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:05.448 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:05.449 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:05.449 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:05.449 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:05.449 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:05.452 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:05.452 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:05.453 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:05.453 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:05.453 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:05.453 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:05.453 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:05.453 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:05.455 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:05.456 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:05.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:05.456 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:05.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:05.456 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:05.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:05.456 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:05.458 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:05.458 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:05.458 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:05.458 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:05.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:05.458 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:05.458 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:05.458 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:05.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:29:05.462 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:29:05.462 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:05.462 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:05.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:05.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:29:05.943 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:29:05.987 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:29:05.989 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:29:05.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:29:05.991 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:29:05.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:05.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:29:05.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:29:05.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:05.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:29:05.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:29:05.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:29:05.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:29:06.033 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:29:06.033 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:29:06.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:06.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:06.415 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:29:06.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:06.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:06.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:06.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:06.886 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:29:07.358 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:29:07.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:07.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:07.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:07.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:07.831 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:29:08.304 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:29:08.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:08.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:08.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:08.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:08.777 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:29:09.249 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:29:09.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:09.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:09.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:09.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:09.722 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:29:10.193 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:29:10.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:10.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:10.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:10.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:10.665 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:29:11.138 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:29:11.610 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:29:12.083 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:29:12.556 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:29:13.028 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:29:13.499 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:29:13.972 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:29:14.441 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:29:14.914 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:29:15.386 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:29:15.858 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:29:16.330 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:29:16.803 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:29:17.276 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:29:17.747 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:29:18.220 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:29:18.693 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:29:19.166 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:29:19.639 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:29:20.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:20.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:29:20.038 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:29:20.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:20.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:20.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:20.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:20.045 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:20.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:20.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:20.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:20.045 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:20.045 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:20.046 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:25.051 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:25.051 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:25.051 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:25.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:25.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:25.051 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:25.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:25.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:25.061 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:25.061 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:25.061 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:25.064 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:25.064 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:25.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:25.065 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:25.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:25.066 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:25.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:25.066 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:25.067 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:25.068 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:25.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:25.068 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:25.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:25.068 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:25.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:25.068 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:25.070 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:25.070 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:25.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:25.070 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:25.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:25.070 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:25.070 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:25.070 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:25.073 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:29:25.073 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:29:25.073 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:25.074 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:25.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:25.075 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:25.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:30.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:30.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:30.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:30.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:30.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:30.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:30.092 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:30.092 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:30.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:30.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:30.096 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:30.097 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:30.097 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:30.097 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:30.097 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:30.098 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:30.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:30.098 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:30.099 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:30.099 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:30.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:30.100 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:30.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:30.100 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:30.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:30.100 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:30.102 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:30.102 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:30.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:30.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:30.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:30.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:30.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:30.102 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:29:30.105 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:29:30.105 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:30.105 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:30.110 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:29:30.588 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:29:30.630 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:29:30.633 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:29:30.635 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:29:30.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:29:30.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:30.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:29:30.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:29:30.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:30.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:29:30.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:29:30.641 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:29:30.641 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:29:30.678 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:29:30.678 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:29:30.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:30.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:31.059 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:29:31.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:31.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:31.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:31.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:31.531 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:29:32.005 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:29:32.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:32.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:32.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:32.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:32.476 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:29:32.948 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:29:33.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:33.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:33.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:33.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:33.420 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:29:33.894 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:29:34.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:34.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:34.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:34.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:34.366 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:29:34.838 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:29:35.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:35.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:35.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:35.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:35.312 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:29:35.784 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:29:36.258 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:29:36.730 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:29:37.202 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:29:37.675 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:29:38.148 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:29:38.621 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:29:38.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:38.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:29:38.683 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:29:38.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:38.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:38.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:38.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:38.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:38.690 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:38.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:38.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:38.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:38.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:38.691 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:43.694 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:43.694 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:43.694 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:43.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:43.694 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:43.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:43.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:43.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:43.705 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:43.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:43.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:43.711 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:43.711 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:43.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:43.712 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:43.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:43.713 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:43.713 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:43.713 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:43.716 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:43.716 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:43.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:43.717 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:43.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:43.718 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:43.718 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:43.718 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:43.721 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:43.721 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:43.721 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:43.721 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:43.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:43.722 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:43.722 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:43.722 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:43.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:29:43.728 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:29:43.728 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:43.728 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:43.731 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:43.731 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:43.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:48.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:48.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:48.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:48.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:48.738 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:48.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:48.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:48.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:48.748 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:48.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:29:48.748 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:29:48.751 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:29:48.751 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:29:48.752 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:48.752 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:48.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:48.753 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:29:48.753 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:29:48.753 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:29:48.754 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:29:48.754 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:29:48.754 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:48.754 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:48.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:48.755 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:29:48.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:29:48.755 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:29:48.757 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:29:48.757 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:29:48.757 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:48.757 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:29:48.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:48.757 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:29:48.757 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:29:48.757 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.760 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:29:48.760 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:29:48.760 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:29:48.761 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:29:48.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:29:48.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:29:48.765 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:29:49.241 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:29:49.283 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:29:49.284 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:29:49.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:29:49.286 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:29:49.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:49.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:29:49.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:29:49.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:29:49.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:29:49.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:29:49.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:29:49.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:29:49.713 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:29:49.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:49.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:49.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:49.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:50.185 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:29:50.658 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:29:50.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:50.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:50.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:50.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:51.131 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:29:51.603 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:29:51.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:51.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:51.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:51.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:52.074 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:29:52.547 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:29:52.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:52.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:52.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:52.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:53.020 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:29:53.492 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:29:53.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:53.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:53.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:53.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:53.963 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:29:54.436 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:29:54.909 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:29:55.381 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:29:55.852 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:29:56.325 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:29:56.797 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:29:57.269 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:29:57.740 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:29:58.211 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:29:58.684 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:29:59.157 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:29:59.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:29:59.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:29:59.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:29:59.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:29:59.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:29:59.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:29:59.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:29:59.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:29:59.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:29:59.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:29:59.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:29:59.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:29:59.348 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:29:59.348 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:59.348 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:59.348 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:59.348 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:59.348 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:29:59.348 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:04.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:04.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:04.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:04.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:04.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:04.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:04.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:04.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:04.362 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:04.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:04.362 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:04.364 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:04.364 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:04.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:04.365 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:04.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:04.365 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:04.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:04.365 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:04.366 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:04.366 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:04.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:04.366 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:04.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:04.367 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:04.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:04.367 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:04.368 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:04.368 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:04.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:04.368 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:04.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:04.368 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:04.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:04.368 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:30:04.370 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:30:04.370 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:04.370 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:04.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:04.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:04.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:04.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:04.372 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:04.372 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:04.372 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:09.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:09.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:09.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:09.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:09.381 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:09.381 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:09.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:09.387 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:09.387 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:09.388 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:09.388 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:09.390 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:09.391 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:09.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:09.391 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:09.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:09.391 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:09.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:09.391 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:09.394 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:09.394 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:09.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:09.394 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:09.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:09.394 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:09.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:09.394 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:09.397 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:09.397 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:09.397 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:09.397 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:09.397 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:09.397 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:09.397 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:09.397 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:09.401 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:09.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:09.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:09.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:09.401 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:09.401 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:30:09.402 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:30:09.402 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:09.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:09.407 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:30:09.870 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:30:09.924 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:30:09.925 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:30:09.927 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:30:09.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:30:09.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:30:09.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:30:09.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:30:09.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:30:09.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:30:09.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:30:09.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:30:09.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:30:09.960 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:30:09.960 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-01-29 03:30:09.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:30:09.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:30:10.335 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:30:10.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:10.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:10.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:10.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:10.801 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:30:11.275 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:30:11.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:11.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:11.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:11.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:11.746 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:30:12.219 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:30:12.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:12.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:12.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:12.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:12.688 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:30:13.159 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:30:13.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:13.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:13.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:13.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:13.631 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:30:14.100 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:30:14.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:14.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:14.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:14.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:14.566 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:30:15.032 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:30:15.499 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:30:15.968 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:30:16.433 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:30:16.896 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:30:17.359 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:30:17.822 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:30:18.286 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:30:18.756 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:30:19.228 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:30:19.698 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:30:20.162 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:30:20.628 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:30:20.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:30:20.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:30:20.962 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:30:20.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:20.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:20.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:20.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:20.964 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:20.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:20.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:20.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:20.964 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:20.964 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:20.964 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:20.964 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2523 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:30:25.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:25.966 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:25.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:25.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:25.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:25.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:25.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:25.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:25.970 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:25.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:25.970 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:25.971 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:25.971 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:25.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:25.971 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:25.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:25.971 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:25.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:25.971 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:25.972 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:25.972 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:25.972 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:25.972 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:25.972 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:25.972 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:25.972 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:25.972 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:25.973 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:25.973 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:25.973 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:25.973 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:25.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:25.973 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:25.973 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:25.973 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:25.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:30:25.976 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:30:25.976 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:25.976 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:25.977 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:25.977 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:25.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:30.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:30.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:30.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:30.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:30.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:30.984 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:30.991 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:30.992 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:30.992 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:30.992 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:30.992 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:30.996 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:30.996 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:30.996 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:30.996 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:30.996 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:30.996 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:30.997 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:30.997 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:31.000 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:31.000 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:31.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:31.000 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:31.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:31.000 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:31.001 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:31.001 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:31.003 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:31.003 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:31.003 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:31.003 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:31.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:31.004 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:31.004 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:31.004 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.007 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:30:31.007 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:30:31.007 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:31.008 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:31.008 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:31.012 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:30:31.481 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:30:31.539 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:30:31.542 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:30:31.543 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:30:31.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:30:31.945 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:30:32.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:32.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:32.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:32.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:32.412 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:30:32.875 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:30:33.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:33.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:33.339 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:30:33.805 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:30:34.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:34.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:34.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:34.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:34.270 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:30:34.735 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:30:35.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:35.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:35.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:35.199 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:30:35.663 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:30:36.015 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:36.016 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:36.016 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:36.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:36.127 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:30:36.591 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:30:37.057 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:30:37.520 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:30:37.990 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:30:38.461 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:30:38.934 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:30:39.407 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:30:39.879 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:30:40.349 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:30:40.824 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:30:41.296 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:30:41.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:41.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:41.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:41.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:41.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:41.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:41.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:41.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:41.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:41.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:41.558 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:46.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:46.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:46.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:46.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:46.562 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:46.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:46.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:46.577 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:46.578 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:46.578 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:46.578 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:46.581 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:46.581 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:46.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:46.582 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:46.582 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:46.582 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:46.582 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:46.582 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:46.585 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:46.585 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:46.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:46.586 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:46.586 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:46.586 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:46.586 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:46.586 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:46.589 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:46.589 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:46.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:46.589 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:46.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:46.590 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:46.590 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:46.590 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:46.594 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:46.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:46.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:46.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.595 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:30:46.595 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:30:46.595 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:46.595 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:46.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:46.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:46.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:46.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:46.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:46.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:46.599 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:30:46.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:46.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:30:51.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:30:51.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:51.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:51.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:51.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:51.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:30:51.612 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:51.612 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:51.612 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:30:51.612 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:30:51.614 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:30:51.614 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:30:51.614 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:51.614 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:51.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:30:51.614 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:30:51.614 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:30:51.614 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:30:51.616 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:30:51.616 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:30:51.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:51.617 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:51.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:30:51.617 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:30:51.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:30:51.617 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:30:51.620 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:30:51.620 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:30:51.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:51.620 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:30:51.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:30:51.620 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:30:51.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:30:51.620 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:30:51.626 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:30:51.626 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:30:51.626 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:30:51.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:30:51.631 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:30:52.099 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:30:52.160 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:30:52.162 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:30:52.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:30:52.164 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:30:52.570 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:30:52.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:52.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:52.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:52.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:53.050 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:30:53.521 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:30:53.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:53.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:53.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:53.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:53.991 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:30:54.455 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:30:54.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:54.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:54.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:54.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:54.929 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:30:55.403 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:30:55.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:55.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:55.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:55.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:55.867 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:30:56.332 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:30:56.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:30:56.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:30:56.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:30:56.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:30:56.795 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:30:57.260 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:30:57.731 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:30:58.202 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:30:58.676 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:30:59.152 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:30:59.624 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:31:00.087 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:31:00.552 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:31:01.015 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:31:01.489 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:31:01.964 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:31:02.438 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:31:02.913 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:31:03.387 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:31:03.862 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:31:04.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:04.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:04.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:04.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:04.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:04.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:04.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:04.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:04.173 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:04.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:04.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:09.180 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:09.180 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:09.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:09.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:09.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:09.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:09.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:09.192 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:09.192 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:09.192 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:09.192 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:09.197 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:09.198 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:09.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:09.198 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:09.198 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:09.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:09.198 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:09.198 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:09.203 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:09.204 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:09.204 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:09.204 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:09.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:09.204 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:09.204 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:09.204 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:09.207 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:09.207 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:09.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:09.208 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:09.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:09.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:09.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:09.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.212 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:31:09.212 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:31:09.212 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:09.213 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:09.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:09.217 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:09.695 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:09.739 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:09.742 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:09.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:09.744 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:09.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:09.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:09.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:09.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:09.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:09.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:09.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:09.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:10.167 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:31:10.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:10.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:10.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:10.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:10.638 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:31:11.109 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:31:11.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:11.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:11.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:11.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:11.581 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:31:12.053 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:31:12.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:12.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:12.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:12.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:12.525 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:31:12.997 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:31:13.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:13.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:13.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:13.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:13.468 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:31:13.941 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:31:14.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:14.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:14.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:14.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:14.414 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:31:14.885 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:31:15.357 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:31:15.827 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:31:16.301 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:31:16.773 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:31:17.244 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:31:17.714 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:31:18.185 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:31:18.657 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:31:19.129 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:31:19.600 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:31:20.074 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:31:20.546 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:31:20.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:20.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:20.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:20.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:20.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:20.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:20.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:20.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:20.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:20.797 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:20.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:20.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:20.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:20.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2504 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:20.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2504 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:20.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2504 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:20.798 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2504 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:20.798 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2504 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:20.798 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2504 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:25.803 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:25.803 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:25.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:25.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:25.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:25.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:25.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:25.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:25.812 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:25.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:25.812 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:25.813 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:25.813 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:25.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:25.813 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:25.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:25.813 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:25.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:25.813 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:25.815 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:25.815 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:25.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:25.815 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:25.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:25.815 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:25.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:25.815 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:25.817 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:25.817 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:25.817 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:25.817 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:25.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:25.817 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:25.818 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:25.818 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:31:25.821 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:31:25.821 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:25.821 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:25.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:25.826 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:26.291 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:26.352 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:26.353 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:26.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:26.356 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:26.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:26.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:26.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:26.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:26.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:26.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:26.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:26.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:26.763 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:31:26.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:26.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:26.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:26.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:27.234 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:31:27.707 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:31:27.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:27.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:27.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:27.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:28.176 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:31:28.641 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:31:28.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:28.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:28.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:28.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:29.113 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:31:29.583 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:31:29.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:29.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:29.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:29.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:30.051 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:31:30.524 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:31:30.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:30.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:30.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:30.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:30.996 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:31:31.467 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:31:31.933 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:31:32.404 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:31:32.875 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:31:33.348 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:31:33.820 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:31:34.292 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:31:34.763 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:31:35.234 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:31:35.705 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:31:36.171 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:31:36.637 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:31:37.104 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:31:37.577 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:31:38.043 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:31:38.509 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:31:38.982 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:31:39.454 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:31:39.924 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:31:40.391 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:31:40.862 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:31:41.333 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:31:41.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:41.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:41.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:41.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:41.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:41.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:41.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:41.394 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:41.394 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:41.394 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:41.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:41.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:41.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:41.394 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3381 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:41.394 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3381 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:41.394 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3381 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:41.394 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:41.394 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:41.394 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:41.394 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:46.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:46.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:46.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:46.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:46.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:46.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:46.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:46.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:46.411 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:46.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:46.411 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:46.413 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:46.413 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:46.413 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:46.413 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:46.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:46.413 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:46.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:46.414 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:46.416 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:46.416 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:46.416 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:46.416 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:46.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:46.416 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:46.416 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:46.416 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:46.418 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:46.418 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:46.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:46.418 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:46.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:46.418 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:46.418 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:46.418 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.422 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:31:46.422 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:31:46.422 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:46.423 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:46.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:46.427 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:46.899 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:46.952 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:46.954 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:46.956 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:46.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:46.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:46.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:46.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:46.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:46.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:46.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:46.970 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:46.970 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:46.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:46.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:47.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:47.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:47.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:47.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:47.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:47.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:47.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:47.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:47.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:47.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:47.006 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:47.006 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:47.007 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:47.007 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:47.007 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:47.007 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:47.007 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:47.007 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:52.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:52.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:52.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:52.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:52.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:52.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:52.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:52.017 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:52.017 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:52.017 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:52.017 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:52.021 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:52.021 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:52.021 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:52.021 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:52.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:52.022 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:52.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:52.022 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:52.025 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:52.025 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:52.025 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:52.025 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:52.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:52.026 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:52.026 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:52.026 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:52.028 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:52.029 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:52.029 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:52.029 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:52.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:52.029 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:52.029 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:52.029 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:52.034 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:52.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:52.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:52.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:52.034 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:52.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:31:52.035 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:31:52.035 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:52.035 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:52.040 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:52.503 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:52.570 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:52.572 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:52.573 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:52.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:52.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:52.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:52.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:52.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:52.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:52.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:52.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:52.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:52.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:52.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:52.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:52.613 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:52.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:52.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:52.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:52.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:52.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:52.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:52.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:52.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:52.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:52.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:52.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:52.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:52.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:52.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:52.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:52.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:52.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:52.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:52.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:52.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:52.832 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:31:52.832 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:31:52.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:52.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:52.968 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:31:53.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:53.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:53.016 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:31:53.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:53.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:53.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:53.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:53.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:53.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:53.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:53.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:53.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:53.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:53.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:53.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:53.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:53.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:53.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:53.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:53.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:53.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:53.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:53.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:53.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:53.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:53.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:53.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:53.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:53.387 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:53.387 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:53.436 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:31:53.437 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:31:53.437 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:31:53.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:53.907 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:31:54.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:54.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:54.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:54.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:54.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:54.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:54.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:54.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:54.230 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:31:54.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:31:54.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:31:54.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:31:54.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:31:54.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:54.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:54.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:54.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:54.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:54.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:54.247 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:31:54.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=483 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:54.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=483 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:54.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=483 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:54.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=483 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:54.247 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=483 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:54.248 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=483 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:31:59.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:31:59.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:31:59.247 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:59.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:59.247 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:59.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:59.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:31:59.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:59.257 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:59.258 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:31:59.258 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:31:59.260 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:31:59.260 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:31:59.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:59.260 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:59.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:31:59.260 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:31:59.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:31:59.260 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:31:59.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:31:59.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:31:59.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:59.263 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:59.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:31:59.263 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:31:59.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:31:59.263 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:31:59.264 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:31:59.264 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:31:59.264 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:59.264 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:31:59.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:31:59.265 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:31:59.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:31:59.265 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:31:59.267 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:31:59.267 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:31:59.267 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:31:59.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:31:59.272 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:31:59.743 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:31:59.779 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:31:59.780 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:31:59.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:59.780 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:31:59.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:59.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:59.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:59.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:31:59.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:31:59.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:31:59.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:31:59.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:59.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:59.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:59.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:31:59.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:31:59.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:31:59.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:31:59.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:31:59.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:00.209 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:32:00.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:00.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:00.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:00.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:00.681 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:32:01.154 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:32:01.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:01.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:01.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:01.271 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:01.627 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:32:02.098 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:32:02.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:02.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:02.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:02.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:02.566 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:32:03.037 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:32:03.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:03.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:03.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:03.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:03.503 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:32:03.974 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:32:04.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:04.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:04.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:04.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:04.447 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:32:04.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:04.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:04.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:04.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:04.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:04.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:04.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:04.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:04.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:04.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:04.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:04.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:04.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:04.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:04.874 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:04.874 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:04.914 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:32:04.914 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:32:04.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:04.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:04.915 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:32:05.384 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:32:05.853 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:32:06.322 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:32:06.793 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:32:07.266 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:32:07.739 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:32:08.211 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:32:08.684 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:32:09.152 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:32:09.620 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:32:09.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:09.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:09.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:09.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:09.923 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:32:09.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:09.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:09.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:09.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:09.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:09.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:09.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:09.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:09.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:09.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:09.950 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:09.950 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:09.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:09.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:09.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:09.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:10.091 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:32:10.564 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:32:11.037 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:32:11.510 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:32:11.982 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:32:12.455 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:32:12.925 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:32:13.396 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:32:13.868 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:32:14.340 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:32:14.813 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:32:14.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:14.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:15.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:15.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:15.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:15.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:15.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:15.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:15.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:15.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:15.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:15.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:15.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:15.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:15.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:15.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:15.046 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:32:15.046 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:32:15.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:15.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:15.284 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:32:15.756 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:32:16.224 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:32:16.688 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:32:17.153 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:32:17.618 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:32:18.087 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:32:18.558 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:32:19.029 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:32:19.495 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:32:19.969 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:32:20.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:20.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:20.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:20.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:20.054 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:32:20.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:20.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:20.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:20.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:20.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:20.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:20.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:20.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:20.069 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:20.069 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:32:20.069 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:32:25.074 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:25.074 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:32:25.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:25.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:25.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:25.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:25.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:25.082 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:25.082 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:25.082 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:25.082 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:32:25.084 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:32:25.084 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:32:25.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:25.084 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:25.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:25.085 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:32:25.085 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:25.085 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:32:25.088 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:32:25.088 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:32:25.088 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:25.088 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:25.088 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:25.088 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:32:25.088 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:25.088 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:32:25.091 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:32:25.091 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:32:25.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:25.091 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:25.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:25.091 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:32:25.091 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:25.091 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:32:25.096 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:32:25.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:32:25.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:32:25.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:32:25.096 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:32:25.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:32:25.097 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:32:25.097 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:32:25.097 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:25.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:25.102 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:32:25.574 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:32:25.629 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:32:25.630 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:32:25.631 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:32:25.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:25.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:25.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:25.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:25.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:25.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:25.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:25.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:25.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:25.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:25.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:25.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:25.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:25.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:25.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:25.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:25.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:26.045 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:32:26.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:26.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:26.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:26.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:26.517 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:32:26.988 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:32:27.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:27.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:27.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:27.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:27.461 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:32:27.934 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:32:28.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:28.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:28.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:28.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:28.406 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:32:28.877 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:32:29.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:29.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:29.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:29.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:29.348 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:32:29.821 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:32:30.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:30.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:30.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:30.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:30.294 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:32:30.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:30.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:30.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:30.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:30.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:30.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:30.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:30.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:30.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:30.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:30.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:30.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:30.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:30.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:30.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:30.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:30.763 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:32:30.763 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:32:30.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:30.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:30.765 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:32:31.237 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:32:31.707 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:32:32.178 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:32:32.643 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:32:33.115 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:32:33.588 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:32:34.060 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:32:34.529 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:32:35.002 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:32:35.475 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:32:35.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:35.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:35.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:35.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:35.770 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:32:35.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:35.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:35.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:35.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:35.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:35.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:35.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:35.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:35.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:35.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:35.795 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:35.795 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:35.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:35.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:35.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:35.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:35.941 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:32:36.413 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:32:36.879 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:32:37.350 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:32:37.818 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:32:38.283 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:32:38.753 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:32:39.224 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:32:39.695 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:32:40.162 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:32:40.632 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:32:40.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:40.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:40.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:40.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:40.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:40.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:40.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:40.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:40.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:40.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:40.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:40.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:40.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:40.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:40.831 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:40.831 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:40.865 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:32:40.866 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:32:40.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:40.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:41.099 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:32:41.569 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:32:42.034 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:32:42.501 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:32:42.972 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:32:43.446 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:32:43.918 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:32:44.390 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:32:44.862 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:32:45.334 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:32:45.806 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:32:45.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:45.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:45.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:45.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:45.874 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:32:45.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:45.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:45.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:45.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:45.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:45.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:45.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:45.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:45.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:45.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:32:45.893 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:32:45.894 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4508 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:45.894 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4508 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:45.894 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4508 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:45.894 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4508 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:45.894 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4508 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:45.894 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4508 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:32:50.894 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:32:50.894 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:32:50.894 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:50.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:50.894 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:50.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:50.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:32:50.905 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:50.905 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:50.906 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:32:50.906 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:32:50.909 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:32:50.909 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:32:50.910 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:50.910 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:50.910 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:32:50.910 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:32:50.910 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:32:50.910 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:32:50.915 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:32:50.915 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:32:50.916 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:50.916 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:50.916 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:32:50.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:32:50.916 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:32:50.916 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:32:50.921 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:32:50.921 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:32:50.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:50.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:32:50.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:32:50.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:32:50.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:32:50.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:32:50.929 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:32:50.929 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:32:50.929 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:32:50.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:32:50.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:32:50.934 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:32:51.402 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:32:51.466 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:32:51.468 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:32:51.470 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:32:51.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:51.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:51.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:51.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:51.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:51.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:51.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:51.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:51.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:51.496 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:51.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:51.496 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:51.496 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:51.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:51.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:51.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:51.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:51.873 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:32:51.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:51.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:51.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:51.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:52.346 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:32:52.813 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:32:52.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:52.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:52.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:52.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:53.281 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:32:53.755 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:32:53.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:53.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:53.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:53.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:54.227 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:32:54.700 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:32:54.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:54.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:54.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:54.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:55.173 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:32:55.645 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:32:55.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:32:55.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:32:55.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:32:55.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:32:56.118 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:32:56.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:56.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:56.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:56.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:56.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:56.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:56.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:56.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:32:56.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:32:56.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:32:56.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:32:56.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:56.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:32:56.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:32:56.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:32:56.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:32:56.581 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:32:56.581 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:32:56.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:56.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:32:56.588 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:32:57.054 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:32:57.520 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:32:57.994 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:32:58.465 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:32:58.938 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:32:59.412 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:32:59.883 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:33:00.357 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:33:00.829 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:33:01.302 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:33:01.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:01.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:01.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:01.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:01.589 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:33:01.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:01.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:01.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:01.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:01.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:01.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:01.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:01.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:01.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:01.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:01.615 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:01.615 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:01.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:01.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:01.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:01.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:01.773 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:33:02.247 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:33:02.719 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:33:03.189 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:33:03.660 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:33:04.131 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:33:04.602 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:33:05.073 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:33:05.544 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:33:06.015 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:33:06.485 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:33:06.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:06.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:06.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:06.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:06.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:06.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:06.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:06.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:06.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:06.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:06.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:06.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:06.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:06.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:06.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:06.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:06.666 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:33:06.666 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:33:06.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:06.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:06.956 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:33:07.429 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:33:07.901 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:33:08.373 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:33:08.840 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:33:09.311 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:33:09.783 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:33:10.251 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:33:10.719 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:33:11.189 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:33:11.660 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:33:11.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:11.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:11.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:11.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:11.675 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:33:11.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:11.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:11.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:11.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:11.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:11.690 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:11.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:11.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:11.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:11.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:33:11.691 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:33:16.692 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:16.692 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:33:16.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:16.692 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:16.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:16.692 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:16.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:16.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:16.699 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:16.699 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:16.699 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:33:16.702 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:33:16.702 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:33:16.702 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:16.703 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:16.703 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:33:16.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:16.703 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:16.703 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:33:16.709 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:33:16.709 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:33:16.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:16.709 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:16.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:16.710 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:33:16.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:16.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:33:16.714 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:33:16.715 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:33:16.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:16.715 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:16.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:16.715 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:33:16.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:16.715 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:33:16.722 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:33:16.722 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:33:16.722 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:16.726 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:33:17.201 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:33:17.253 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:33:17.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:17.256 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:33:17.259 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:33:17.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:17.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:17.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:17.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:17.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:17.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:17.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:17.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:17.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:17.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:17.312 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:17.312 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:17.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:17.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:17.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:17.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:17.674 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:33:17.725 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:17.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:17.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:17.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:18.144 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:33:18.615 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:33:18.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:18.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:18.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:18.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:19.087 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:33:19.560 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:33:19.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:19.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:19.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:19.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:20.032 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:33:20.504 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:33:20.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:20.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:20.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:20.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:20.974 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:33:21.445 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:33:21.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:21.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:21.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:21.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:21.915 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:33:22.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:22.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:22.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:22.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:22.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:22.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:22.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:22.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:22.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:22.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:22.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:22.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:22.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:22.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:22.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:22.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:22.381 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:33:22.384 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:33:22.384 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:33:22.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:22.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:22.852 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:33:23.317 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:33:23.782 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:33:24.249 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:33:24.722 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:33:25.194 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:33:25.665 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:33:26.138 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:33:26.611 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:33:27.084 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:33:27.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:27.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:27.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:27.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:27.392 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:33:27.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:27.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:27.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:27.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:27.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:27.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:27.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:27.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:27.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:27.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:27.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:27.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:27.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:27.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:27.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:27.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:27.554 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:33:28.025 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:33:28.496 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:33:28.967 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:33:29.440 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:33:29.911 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:33:30.384 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:33:30.856 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:33:31.326 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:33:31.797 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:33:32.268 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:33:32.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:32.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:32.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:32.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:32.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:32.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:32.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:32.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:32.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:32.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:32.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:32.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:32.499 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:33:32.500 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:33:32.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:32.741 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:33:33.213 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:33:33.686 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:33:34.159 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:33:34.631 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:33:35.095 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:33:35.560 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:33:36.029 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:33:36.502 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:33:36.973 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:33:37.439 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:33:37.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:37.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:37.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:37.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:37.509 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:33:37.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:37.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:37.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:37.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:37.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:37.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:37.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:33:37.527 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:33:37.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:37.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:37.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:37.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4509 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:37.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4509 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:37.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4509 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:37.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4509 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:37.529 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4509 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:37.529 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4509 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:37.529 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4509 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:42.534 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:42.534 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:33:42.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:42.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:42.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:42.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:42.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:42.547 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:42.547 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:42.547 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:42.547 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:33:42.549 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:33:42.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:33:42.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:42.549 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:42.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:42.550 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:33:42.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:42.550 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:33:42.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:33:42.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:33:42.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:42.552 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:42.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:42.552 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:33:42.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:42.552 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:33:42.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:33:42.554 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:33:42.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:42.554 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:42.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:42.554 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:33:42.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:42.554 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.556 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:33:42.556 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:33:42.556 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:33:42.557 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:42.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:42.561 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:33:43.024 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:33:43.087 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:33:43.091 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:33:43.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:43.092 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:33:43.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:43.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:43.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:43.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:43.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:43.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:43.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:43.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:43.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:43.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:43.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:43.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:43.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:43.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:43.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:43.435 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:43.435 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:43.441 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:33:43.441 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:33:43.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.490 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:33:43.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:43.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:43.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:43.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:43.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:43.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.820 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:33:43.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:43.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:43.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:43.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:43.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:43.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.846 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:43.846 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:43.846 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:43.846 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:43.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:43.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:43.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:43.963 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:33:44.430 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:33:44.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:44.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:44.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:44.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:44.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:44.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:44.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:44.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:44.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:44.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:44.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:44.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:44.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:44.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:44.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:44.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:44.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:44.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:44.616 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:44.616 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:44.666 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:33:44.666 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:33:44.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:44.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:44.901 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:33:45.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:45.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:45.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:45.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:45.223 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:33:45.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:45.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:45.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:45.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:45.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:45.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:45.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:45.236 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:45.236 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:33:45.237 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:33:45.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:45.237 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=585 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:33:50.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:33:50.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:33:50.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:50.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:50.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:50.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:50.244 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:33:50.244 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:50.244 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:50.244 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:33:50.244 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:33:50.245 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:33:50.245 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:33:50.245 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:50.246 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:50.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:33:50.246 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:33:50.246 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:33:50.246 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:33:50.247 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:33:50.247 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:33:50.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:50.247 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:50.247 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:33:50.247 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:33:50.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:33:50.247 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:33:50.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:33:50.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:33:50.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:50.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:33:50.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:33:50.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:33:50.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:33:50.248 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.250 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:33:50.250 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:33:50.250 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:33:50.250 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:33:50.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:33:50.255 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:33:50.730 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:33:50.764 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:33:50.764 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:33:50.764 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:33:50.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:50.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:50.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:50.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:50.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:33:50.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:33:50.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:33:50.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:33:50.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:50.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:50.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:50.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:33:50.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:33:50.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:33:50.819 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:33:50.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:50.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:33:51.199 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:33:51.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:51.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:51.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:51.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:51.673 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:33:52.145 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:33:52.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:52.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:52.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:52.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:52.616 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:33:53.086 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:33:53.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:53.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:53.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:53.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:53.557 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:33:54.030 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:33:54.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:54.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:54.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:54.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:54.503 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:33:54.976 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:33:55.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:33:55.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:33:55.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:33:55.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:33:55.447 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:33:55.917 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:33:56.388 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:33:56.859 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:33:57.330 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:33:57.798 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:33:58.268 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:33:58.741 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:33:59.214 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:33:59.685 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:34:00.158 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:34:00.631 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:34:01.103 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:34:01.576 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:34:02.049 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:34:02.519 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:34:02.987 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:34:03.454 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:34:03.923 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:34:04.390 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:34:04.860 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:34:05.325 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:34:05.798 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:34:06.265 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:34:06.737 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:34:07.209 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:34:07.679 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:34:08.153 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:34:08.625 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:34:09.096 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:34:09.566 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:34:10.033 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:34:10.504 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:34:10.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:10.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:10.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:10.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:10.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:10.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:10.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:34:10.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:10.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:10.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:34:10.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:10.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:10.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:34:10.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:34:10.852 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:34:10.852 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:34:10.874 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:34:10.874 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:34:10.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:10.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:10.975 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:34:11.444 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:34:11.916 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:34:12.387 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:34:12.857 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:34:13.328 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:34:13.799 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:34:14.269 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:34:14.741 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:34:15.212 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:34:15.678 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:34:16.146 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:34:16.613 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:34:17.081 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:34:17.552 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:34:18.023 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:34:18.490 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:34:18.955 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:34:19.426 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:34:19.898 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:34:20.366 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:34:20.832 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:34:21.303 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:34:21.774 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:34:22.245 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:34:22.715 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:34:23.180 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:34:23.645 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:34:24.110 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:34:24.580 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:34:25.049 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:34:25.514 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:34:25.985 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:34:26.454 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:34:26.925 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:34:27.397 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:34:27.866 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:34:28.332 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:34:28.801 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:34:29.265 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:34:29.731 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:34:30.201 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:34:30.674 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:34:30.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:30.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:30.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:30.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:30.888 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:34:30.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:30.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:30.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:34:30.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:30.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:30.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:34:30.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:30.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:30.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:34:30.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:34:30.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:34:30.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:34:30.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:34:30.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:34:30.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:30.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:31.143 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:34:31.614 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:34:32.085 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:34:32.556 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:34:33.027 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:34:33.498 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:34:33.968 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:34:34.437 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 03:34:34.905 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 03:34:35.376 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 03:34:35.847 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 03:34:36.318 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 03:34:36.789 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 03:34:37.262 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 03:34:37.734 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 03:34:38.207 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 03:34:38.675 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 03:34:39.147 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 03:34:39.619 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 03:34:40.090 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 03:34:40.559 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 03:34:41.031 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 03:34:41.503 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 03:34:41.973 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 03:34:42.439 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 03:34:42.906 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 03:34:43.372 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 03:34:43.838 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 03:34:44.307 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 03:34:44.780 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 03:34:45.252 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 03:34:45.723 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 03:34:46.193 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 03:34:46.667 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 03:34:47.139 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 03:34:47.611 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 03:34:48.082 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 03:34:48.553 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 03:34:49.023 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 03:34:49.491 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 03:34:49.959 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 03:34:50.425 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 03:34:50.890 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 03:34:50.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:50.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:50.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:50.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:50.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:50.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:50.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:34:50.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:34:50.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:34:50.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:34:50.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:34:50.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:50.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:34:50.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:34:50.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:34:50.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:34:51.024 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:34:51.024 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:34:51.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:51.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:34:51.354 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 03:34:51.819 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 03:34:52.287 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 03:34:52.753 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 03:34:53.224 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 03:34:53.697 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 03:34:54.169 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 03:34:54.642 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 03:34:55.116 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 03:34:55.588 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 03:34:56.057 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 03:34:56.530 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 03:34:57.002 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 03:34:57.470 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 03:34:57.937 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 03:34:58.410 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 03:34:58.880 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 03:34:59.345 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 03:34:59.809 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 03:35:00.279 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 03:35:00.748 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 03:35:01.221 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 03:35:01.688 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 03:35:02.155 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 03:35:02.620 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 03:35:03.084 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 03:35:03.557 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 03:35:04.029 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 03:35:04.502 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 03:35:04.975 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 03:35:05.447 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 03:35:05.921 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 03:35:06.393 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 03:35:06.865 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 03:35:07.337 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 03:35:07.810 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 03:35:08.282 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 03:35:08.753 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 03:35:09.222 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 03:35:09.693 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 03:35:10.166 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 03:35:10.634 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 03:35:11.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:11.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:11.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:11.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:11.034 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:11.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:11.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:11.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:11.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:11.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:11.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:11.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:11.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:11.055 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:11.055 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:35:11.055 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:35:11.055 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17535 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:11.055 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17535 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:11.055 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17535 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:11.055 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17535 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:11.056 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17535 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:11.056 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=17535 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:16.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:16.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:35:16.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:16.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:16.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:16.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:16.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:16.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:16.066 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:16.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:16.066 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:35:16.070 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:35:16.070 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:35:16.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:16.070 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:16.071 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:35:16.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:16.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:16.071 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:35:16.074 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:35:16.074 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:35:16.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:16.074 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:16.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:16.074 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:35:16.075 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:16.075 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:35:16.077 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:35:16.077 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:35:16.078 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:16.078 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:16.078 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:16.078 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:35:16.078 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:16.078 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:35:16.081 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:35:16.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:35:16.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:35:16.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:35:16.081 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:35:16.082 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:35:16.082 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:35:16.082 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:16.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:35:16.084 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:16.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:21.092 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:21.092 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:35:21.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:21.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:21.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:21.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:21.100 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:21.101 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:21.101 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:21.101 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:21.101 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:35:21.105 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:35:21.105 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:35:21.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:21.105 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:21.106 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:35:21.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:21.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:21.106 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:35:21.110 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:35:21.110 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:35:21.110 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:21.110 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:21.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:21.111 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:35:21.111 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:21.111 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:35:21.115 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:35:21.115 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:35:21.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:21.115 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:21.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:21.115 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:35:21.115 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:21.115 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:35:21.122 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:35:21.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:35:21.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:35:21.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:35:21.122 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:35:21.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.123 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:35:21.123 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:35:21.123 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:35:21.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:21.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:21.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:21.128 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:35:21.601 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:35:21.647 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:35:21.648 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:35:21.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:21.648 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:35:21.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:21.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:21.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:21.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:21.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:21.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:21.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:21.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:21.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:21.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:21.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:21.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:21.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:21.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:21.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:21.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:21.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:21.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:21.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:21.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:21.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:21.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:21.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:21.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:21.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:21.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:21.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:21.900 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:21.900 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:21.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:21.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:21.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:21.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.063 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:35:22.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:22.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:22.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:22.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:22.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.131 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:22.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:22.131 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:22.131 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:22.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:22.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:22.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:22.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:22.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:22.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:22.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:22.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:22.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:22.386 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:22.386 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:22.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.526 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:35:22.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.662 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:22.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:22.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:22.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:22.684 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:22.685 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:22.707 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:22.708 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:22.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.984 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:22.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:22.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:22.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:22.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:22.999 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:35:22.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:22.999 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:22.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:23.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:23.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:23.042 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:23.042 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:23.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:23.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:23.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:23.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:23.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:23.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:23.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:23.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:23.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:23.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:23.345 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:23.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:23.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:23.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:23.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:23.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:23.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:23.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:23.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:23.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:23.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:23.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:23.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:23.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:23.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:23.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:23.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:23.469 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:35:23.942 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:35:24.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:24.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:24.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:24.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:24.414 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:35:24.885 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:35:25.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:25.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:25.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:25.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:25.356 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:35:25.829 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:35:25.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:25.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:25.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:25.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:26.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:26.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:26.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:26.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:26.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:26.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:26.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:26.007 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:26.007 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:26.060 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:26.060 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:26.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:26.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:26.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:26.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:26.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:26.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:26.301 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:35:26.773 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:35:27.244 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:35:27.718 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:35:28.190 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:35:28.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:28.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:28.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:28.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:28.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:28.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:28.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:28.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:28.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:28.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:28.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:28.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:28.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:28.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:28.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:28.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:28.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:28.661 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:35:29.133 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:35:29.604 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:35:30.077 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:35:30.547 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:35:31.012 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:35:31.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:31.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:31.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:31.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:31.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:31.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:31.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:31.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:31.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:31.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:31.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:31.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:31.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:31.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:31.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:31.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:31.246 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:31.246 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:31.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:31.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:31.477 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:35:31.944 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:35:32.410 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:35:32.876 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:35:33.347 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:35:33.818 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:35:33.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:33.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:33.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:33.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:33.904 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:33.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:33.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:33.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:33.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:33.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:33.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:33.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:33.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:33.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:33.953 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:33.953 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:33.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:33.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:34.289 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:35:34.756 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:35:35.221 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:35:35.692 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:35:36.165 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:35:36.638 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:35:36.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:36.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:36.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:36.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:36.725 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:36.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:36.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:36.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:36.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:36.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:36.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:36.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:36.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:36.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:36.777 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:36.777 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:36.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:36.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:37.107 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:35:37.574 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:35:38.041 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:35:38.508 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:35:38.974 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:35:39.444 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:35:39.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:39.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:39.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:39.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:39.533 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:39.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:39.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:39.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:39.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:39.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:39.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:39.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:39.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:39.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:39.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:35:39.551 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:35:39.551 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4002 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.551 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4002 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.551 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4002 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4002 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4002 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4002 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.552 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:39.553 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4003 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:35:44.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:44.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:35:44.551 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:44.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:44.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:44.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:44.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:44.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:44.560 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:44.561 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:35:44.561 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:35:44.564 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:35:44.564 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:35:44.565 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:44.565 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:44.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:44.565 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:35:44.565 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:35:44.565 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:35:44.569 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:35:44.569 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:35:44.569 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:44.569 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:44.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:44.569 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:35:44.569 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:35:44.569 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:35:44.573 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:35:44.573 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:35:44.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:44.573 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:35:44.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:44.573 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:35:44.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:35:44.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:35:44.578 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:35:44.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:35:44.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:35:44.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:35:44.579 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:35:44.579 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:35:44.579 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:35:44.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:35:44.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:35:44.584 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:35:45.051 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:35:45.113 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:35:45.114 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:35:45.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:45.116 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:35:45.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:45.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:45.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:45.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:45.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:45.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:45.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:45.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:45.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:45.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:45.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:45.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:45.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:45.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:45.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:45.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:45.518 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:35:45.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:45.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:45.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:45.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:45.986 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:35:46.458 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:35:46.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:46.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:46.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:46.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:46.929 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:35:47.400 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:35:47.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:47.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:47.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:47.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:47.873 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:35:48.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:48.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:48.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:48.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:48.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:48.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:48.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:48.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:48.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:48.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:48.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:48.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:48.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:48.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:48.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:48.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:48.340 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:48.340 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:35:48.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:48.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:48.344 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:35:48.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:48.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:48.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:48.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:48.809 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:35:49.281 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:35:49.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:49.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:49.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:49.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:49.754 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:35:50.224 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:35:50.696 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:35:51.170 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:35:51.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:51.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:51.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:51.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:51.547 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:51.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:51.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:51.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:51.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:51.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:51.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:51.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:51.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:51.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:51.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:51.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:51.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:51.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:51.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:51.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:51.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:51.640 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:35:52.108 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:35:52.576 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:35:53.040 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:35:53.506 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:35:53.972 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:35:54.441 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:35:54.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:54.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:54.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:54.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:54.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:54.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:54.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:54.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:54.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:54.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:35:54.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:54.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:54.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:35:54.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:35:54.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:35:54.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:35:54.906 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:35:54.906 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:35:54.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:54.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:54.912 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:35:55.383 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:35:55.853 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:35:56.317 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:35:56.782 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:35:57.249 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:35:57.721 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:35:58.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:35:58.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:35:58.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:35:58.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:35:58.068 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:35:58.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:35:58.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:35:58.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:35:58.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:35:58.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:35:58.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:35:58.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:35:58.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:35:58.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:35:58.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:35:58.082 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:36:03.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:03.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:36:03.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:03.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:03.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:03.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:03.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:03.098 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:03.098 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:03.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:03.099 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:36:03.102 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:36:03.102 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:36:03.102 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:03.103 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:03.103 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:03.103 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:36:03.103 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:03.103 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:36:03.107 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:36:03.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:36:03.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:03.108 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:03.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:03.108 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:36:03.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:03.108 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:36:03.112 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:36:03.112 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:36:03.112 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:03.112 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:03.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:03.112 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:36:03.113 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:03.113 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:36:03.118 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:36:03.118 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:36:03.118 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:36:03.118 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:36:03.118 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:36:03.119 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:36:03.119 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:36:03.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.119 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:03.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:03.124 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:36:03.597 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:36:03.659 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:36:03.661 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:36:03.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:03.663 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:36:03.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:03.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:03.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:03.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:03.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:03.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:03.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:03.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:03.708 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:03.708 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:03.708 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:03.708 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:03.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:03.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:03.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:03.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:04.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:04.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:04.069 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:36:04.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:04.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:04.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:04.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:04.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:04.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:04.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:04.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:04.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:04.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:04.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:04.114 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:36:04.114 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:36:04.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:04.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:04.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:04.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:04.540 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:36:04.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:04.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:04.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:04.600 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:36:04.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:04.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:04.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:04.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:04.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:04.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:04.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:04.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:04.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:04.625 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:04.625 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:04.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:04.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:04.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:04.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:05.010 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:36:05.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:05.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:05.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:05.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:05.477 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:36:05.950 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:36:06.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:06.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:06.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:06.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:06.415 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:36:06.888 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:36:07.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:07.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:07.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:07.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:07.360 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:36:07.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:07.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:07.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:07.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:07.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:07.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:07.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:07.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:07.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:07.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:07.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:07.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:07.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:07.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:07.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:07.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:07.595 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:36:07.595 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:36:07.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:07.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:07.827 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:36:08.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:08.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:08.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:08.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:08.293 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:36:08.757 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:36:09.224 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:36:09.693 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:36:10.157 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:36:10.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:10.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:10.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:10.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:10.478 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:36:10.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:10.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:10.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:10.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:10.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:10.493 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:10.493 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:36:10.494 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:36:10.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:10.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:10.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:10.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:10.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:10.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:10.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:10.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:10.494 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:15.501 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:15.501 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:36:15.501 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:15.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:15.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:15.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:15.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:15.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:15.516 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:15.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:15.516 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:36:15.517 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:36:15.517 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:36:15.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:15.518 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:15.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:15.518 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:36:15.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:15.518 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:36:15.520 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:36:15.520 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:36:15.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:15.520 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:15.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:15.520 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:36:15.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:15.520 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:36:15.522 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:36:15.522 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:36:15.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:15.522 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:15.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:15.522 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:36:15.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:15.522 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:36:15.525 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:36:15.525 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:15.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:36:16.000 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:36:16.054 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:36:16.056 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:36:16.057 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:36:16.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:16.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:16.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:16.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:16.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:16.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:16.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:16.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:16.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:16.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:16.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:16.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:16.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:16.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:16.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:16.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:16.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:16.468 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:36:16.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:16.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:16.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:16.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:16.934 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:36:17.405 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:36:17.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:17.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:17.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:17.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:17.449 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:17.449 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:17.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:17.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:17.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:17.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:17.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:17.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:17.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:17.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:17.457 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:17.457 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:17.497 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:36:17.497 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:36:17.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:17.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:17.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:17.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:17.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:17.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:17.871 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:36:18.344 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:36:18.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:18.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:18.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:18.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:18.811 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:36:19.278 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:36:19.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:19.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:19.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:19.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:19.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:19.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:19.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:19.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:19.605 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:36:19.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:19.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:19.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:19.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:19.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:19.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:19.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:19.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:19.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:19.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:19.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:19.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:19.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:19.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:19.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:19.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:19.745 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:36:20.216 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:36:20.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:20.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:20.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:20.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:20.687 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:36:21.152 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:36:21.623 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:36:22.094 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:36:22.565 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:36:23.036 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:36:23.507 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:36:23.977 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:36:24.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:24.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:24.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:24.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:24.446 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:36:24.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:24.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:24.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:24.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:24.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:24.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:24.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:24.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:24.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:24.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:24.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:24.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:24.486 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:36:24.486 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:36:24.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:24.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:24.917 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:36:25.389 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:36:25.862 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:36:26.333 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:36:26.807 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:36:27.280 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:36:27.753 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:36:28.225 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:36:28.698 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:36:29.171 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:36:29.643 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:36:30.111 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:36:30.581 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:36:31.047 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:36:31.519 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:36:31.992 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:36:32.465 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:36:32.936 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:36:33.408 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:36:33.879 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:36:34.349 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:36:34.819 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:36:35.283 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:36:35.749 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:36:36.222 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:36:36.695 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:36:37.168 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:36:37.635 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:36:38.100 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:36:38.564 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:36:39.031 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:36:39.500 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:36:39.965 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:36:40.432 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:36:40.897 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:36:41.362 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:36:41.831 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:36:42.298 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:36:42.771 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:36:43.235 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:36:43.701 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:36:44.172 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:36:44.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:44.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:44.466 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:36:44.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:44.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:44.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:44.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:44.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:44.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:44.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:44.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:44.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:44.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:36:44.473 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:36:44.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6289 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:44.473 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6289 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:44.474 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6289 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:44.474 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6289 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:44.474 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6289 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:36:49.476 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:36:49.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:36:49.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:49.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:49.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:49.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:49.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:36:49.491 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:49.491 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:49.491 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:36:49.491 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:36:49.495 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:36:49.495 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:36:49.496 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:49.496 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:49.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:36:49.496 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:36:49.496 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:36:49.496 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:36:49.501 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:36:49.501 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:36:49.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:49.501 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:49.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:36:49.501 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:36:49.502 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:36:49.502 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:36:49.505 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:36:49.506 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:36:49.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:49.506 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:36:49.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:36:49.506 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:36:49.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:36:49.506 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:36:49.510 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:36:49.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:36:49.511 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:36:49.511 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:36:49.511 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:36:49.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:36:49.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:36:49.516 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:36:49.982 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:36:50.037 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:36:50.039 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:36:50.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:50.041 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:36:50.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:50.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:50.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:50.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:50.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:50.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:50.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:50.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:50.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:50.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:50.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:50.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:50.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:50.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:50.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:50.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:50.447 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:36:50.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:50.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:50.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:50.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:50.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:50.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:50.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:50.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:50.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:50.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:50.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:50.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:50.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:50.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:50.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:50.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:50.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:50.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:50.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:50.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:50.768 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:36:50.768 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:36:50.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:50.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:50.917 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:36:51.383 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:36:51.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:51.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:51.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:51.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:51.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:51.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:51.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:51.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:51.688 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:36:51.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:51.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:51.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:51.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:51.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:51.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:51.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:51.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:51.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:51.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:51.713 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:51.713 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:51.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:51.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:51.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:51.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:51.848 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:36:52.319 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:36:52.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:52.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:52.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:52.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:52.790 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:36:53.263 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:36:53.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:53.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:53.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:53.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:53.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:53.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:53.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:53.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:53.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:53.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:53.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:53.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:36:53.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:36:53.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:36:53.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:36:53.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:53.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:36:53.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:36:53.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:36:53.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:36:53.729 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:36:53.730 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:36:53.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:53.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:36:53.735 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:36:54.207 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:36:54.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:36:54.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:36:54.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:36:54.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:36:54.678 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:36:55.147 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:36:55.612 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:36:56.079 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:36:56.545 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:36:57.009 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:36:57.475 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:36:57.941 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:36:58.406 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:36:58.875 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:36:59.348 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:36:59.820 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:37:00.292 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:37:00.765 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:37:01.237 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:37:01.709 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:37:02.176 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:37:02.642 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:37:03.111 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:37:03.581 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:37:04.053 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:37:04.526 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:37:04.999 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:37:05.470 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:37:05.942 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:37:06.415 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:37:06.888 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:37:07.362 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:37:07.834 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:37:08.306 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:37:08.776 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:37:09.246 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:37:09.718 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:37:10.189 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:37:10.661 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:37:11.135 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:37:11.606 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:37:12.078 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:37:12.542 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:37:13.011 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:37:13.476 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:37:13.674 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:13.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:13.674 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:37:13.678 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:13.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:13.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:13.678 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:13.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:13.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:13.679 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:13.679 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:37:13.679 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:37:13.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:13.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:13.679 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5248 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:13.679 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5248 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:13.679 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5248 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:13.679 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5248 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:13.679 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5248 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:13.679 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=5248 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:18.689 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:18.689 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:37:18.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:18.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:18.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:18.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:18.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:18.704 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:18.704 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:18.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:18.705 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:37:18.707 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:37:18.707 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:37:18.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:18.707 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:18.707 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:18.707 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:37:18.708 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:18.708 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:37:18.710 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:37:18.710 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:37:18.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:18.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:18.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:18.710 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:37:18.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:18.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:37:18.712 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:37:18.712 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:37:18.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:18.712 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:18.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:18.712 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:37:18.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:18.712 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.714 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:37:18.714 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:37:18.715 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:37:18.715 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:18.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:18.719 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:37:19.185 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:37:19.243 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:37:19.246 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:37:19.248 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:37:19.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:19.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:19.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:19.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:19.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:19.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:19.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:19.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:19.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:19.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:19.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:19.306 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:19.306 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:19.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:19.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:19.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:19.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:19.654 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:37:19.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:19.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:19.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:19.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:20.121 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:37:20.589 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:37:20.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:20.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:20.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:20.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:21.057 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:37:21.527 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:37:21.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:21.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:21.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:21.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:21.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:21.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:21.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:21.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:21.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:21.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:21.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:21.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:21.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:21.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:21.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:21.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:21.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:21.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:21.777 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:21.777 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:21.808 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:37:21.808 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:37:21.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:21.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:21.994 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:37:22.463 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:37:22.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:22.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:22.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:22.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:22.934 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:37:23.399 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:37:23.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:23.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:23.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:23.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:23.865 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:37:24.329 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:37:24.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:24.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:24.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:24.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:24.510 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:37:24.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:24.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:24.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:24.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:24.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:24.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:24.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:24.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:24.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:24.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:24.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:24.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:24.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:24.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:24.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:24.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:24.797 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:37:25.269 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:37:25.740 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:37:26.213 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:37:26.686 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:37:27.158 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:37:27.629 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:37:28.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:28.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:28.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:28.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:28.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:28.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:28.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:28.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:28.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:28.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:28.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:28.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:28.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:28.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:28.035 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:28.035 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:28.044 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:37:28.044 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:37:28.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:28.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:28.099 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:37:28.570 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:37:29.042 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:37:29.514 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:37:29.987 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:37:30.459 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:37:30.930 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:37:31.403 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:37:31.876 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:37:32.342 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:37:32.808 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:37:33.274 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:37:33.742 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:37:34.215 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:37:34.689 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:37:35.161 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:37:35.634 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:37:36.107 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:37:36.579 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:37:37.048 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:37:37.520 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:37:37.993 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:37:38.464 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:37:38.936 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:37:39.405 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:37:39.871 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:37:40.337 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:37:40.802 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:37:41.269 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:37:41.734 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:37:42.201 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:37:42.666 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:37:43.131 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:37:43.598 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:37:44.067 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:37:44.539 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:37:45.008 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:37:45.481 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:37:45.949 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:37:46.416 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:37:46.887 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:37:47.355 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:37:47.826 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:37:48.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:48.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:48.030 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:37:48.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:48.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:48.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:48.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:48.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:48.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:48.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:48.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:48.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:48.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:37:48.036 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:37:48.036 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6372 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:48.036 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6372 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:48.036 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6372 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:48.036 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6372 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:48.036 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6372 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:48.036 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=6372 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:53.039 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:53.039 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:37:53.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:53.039 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:53.039 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:53.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:53.046 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:53.047 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:53.047 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:53.048 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:37:53.048 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:37:53.052 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:37:53.052 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:37:53.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:53.053 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:53.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:53.053 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:37:53.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:37:53.053 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:37:53.057 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:37:53.057 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:37:53.057 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:53.057 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:53.058 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:53.058 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:37:53.058 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:37:53.058 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:37:53.062 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:37:53.062 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:37:53.062 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:53.062 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:37:53.062 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:37:53.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:53.062 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:37:53.062 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:37:53.068 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:37:53.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:37:53.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:37:53.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:37:53.068 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:37:53.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:37:53.069 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:37:53.069 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:37:53.069 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:37:53.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:37:53.074 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:37:53.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:37:53.611 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:37:53.613 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:37:53.615 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:37:53.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:53.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:53.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:53.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:53.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:53.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:53.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:53.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:53.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:53.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:53.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:53.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:53.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:53.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:53.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:53.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:53.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:53.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:53.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:53.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:53.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:53.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:53.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:53.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:53.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:53.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:53.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:53.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:53.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:53.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:53.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:53.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:53.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:53.960 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:37:53.960 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:37:53.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:53.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.007 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:37:54.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:54.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:54.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:54.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:54.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:54.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:54.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:54.294 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:37:54.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:54.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:54.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:54.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:54.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:54.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:54.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:54.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:54.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:54.319 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:54.319 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:54.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:54.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:54.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.475 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:37:54.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:54.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:54.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:54.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:54.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:54.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:54.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:54.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:54.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:37:54.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:54.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:37:54.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:37:54.893 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:37:54.893 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:37:54.941 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:37:54.942 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:37:54.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:54.947 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:37:55.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:55.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:55.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:55.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:55.418 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:37:55.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:37:55.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:37:55.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:37:55.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:37:55.505 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:37:55.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:37:55.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:37:55.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:37:55.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:37:55.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:37:55.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:37:55.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:37:55.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:37:55.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:37:55.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:37:55.520 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:37:55.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=534 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:55.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=534 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:55.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=534 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:55.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=534 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:55.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=534 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:55.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=534 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:37:55.520 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=534 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:38:00.523 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:38:00.523 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:38:00.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:38:00.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:38:00.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:38:00.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:38:00.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:38:00.531 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:38:00.531 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:38:00.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:38:00.532 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:38:00.536 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:38:00.536 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:38:00.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:38:00.536 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:38:00.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:38:00.536 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:38:00.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:38:00.537 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:38:00.541 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:38:00.541 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:38:00.541 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:38:00.541 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:38:00.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:38:00.541 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:38:00.542 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:38:00.542 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:38:00.545 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:38:00.545 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:38:00.545 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:38:00.545 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:38:00.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:38:00.545 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:38:00.546 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:38:00.546 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:38:00.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:38:00.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:38:00.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:38:00.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:38:00.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:38:00.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:38:00.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:38:00.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:38:00.551 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:38:00.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:38:00.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:38:00.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:38:00.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:38:01.021 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:38:01.086 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:38:01.089 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:38:01.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:01.091 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:38:01.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:01.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:38:01.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:38:01.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:01.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:38:01.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:38:01.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:01.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:01.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:38:01.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:38:01.109 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:38:01.109 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:38:01.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:38:01.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:38:01.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:01.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:01.489 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:38:01.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:38:01.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:38:01.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:38:01.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:38:01.963 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:38:02.435 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:38:02.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:38:02.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:38:02.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:38:02.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:38:02.908 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:38:03.379 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:38:03.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:38:03.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:38:03.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:38:03.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:38:03.852 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:38:04.325 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:38:04.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:38:04.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:38:04.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:38:04.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:38:04.797 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:38:05.268 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:38:05.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:38:05.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:38:05.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:38:05.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:38:05.738 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:38:06.206 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:38:06.675 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:38:07.146 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:38:07.617 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:38:08.088 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:38:08.558 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:38:09.029 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:38:09.500 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:38:09.971 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:38:10.442 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:38:10.912 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:38:11.383 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:38:11.850 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:38:12.320 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:38:12.793 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:38:13.265 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:38:13.737 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:38:14.207 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:38:14.674 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:38:15.144 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:38:15.610 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:38:16.076 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:38:16.547 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:38:17.017 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:38:17.490 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:38:17.962 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:38:18.429 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:38:18.899 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:38:19.373 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:38:19.846 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:38:20.318 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:38:20.784 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:38:21.255 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:38:21.726 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:38:22.196 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:38:22.667 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:38:23.140 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:38:23.613 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:38:24.085 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:38:24.556 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:38:25.027 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:38:25.497 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:38:25.965 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:38:26.432 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:38:26.899 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:38:27.366 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:38:27.834 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:38:28.301 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:38:28.769 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:38:29.235 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:38:29.706 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:38:30.172 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:38:30.644 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:38:31.117 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:38:31.588 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:38:32.058 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:38:32.526 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:38:32.993 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:38:33.460 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:38:33.929 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:38:34.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:34.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:34.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:34.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:38:34.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:34.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:38:34.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:38:34.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:38:34.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:38:34.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:38:34.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:38:34.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:34.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:38:34.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:38:34.138 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:38:34.138 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:38:34.162 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:38:34.163 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:38:34.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:34.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:38:34.396 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:38:34.861 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:38:35.328 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:38:35.793 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:38:36.261 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:38:36.734 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:38:37.205 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:38:37.674 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:38:38.147 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:38:38.618 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:38:39.091 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:38:39.561 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:38:40.030 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:38:40.502 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:38:40.972 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:38:41.444 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:38:41.916 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:38:42.387 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:38:42.854 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:38:43.323 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:38:43.788 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:38:44.261 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:38:44.732 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 03:38:45.201 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 03:38:45.667 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 03:38:46.132 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 03:38:46.598 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 03:38:47.064 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 03:38:47.537 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 03:38:48.010 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 03:38:48.482 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-01-29 03:38:48.955 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-01-29 03:38:49.421 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-01-29 03:38:49.886 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-01-29 03:38:50.351 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-01-29 03:38:50.822 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-01-29 03:38:51.291 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-01-29 03:38:51.759 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-01-29 03:38:52.233 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-01-29 03:38:52.705 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-01-29 03:38:53.175 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-01-29 03:38:53.645 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-01-29 03:38:54.112 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-01-29 03:38:54.585 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-01-29 03:38:55.057 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-01-29 03:38:55.529 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-01-29 03:38:56.002 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-01-29 03:38:56.472 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-01-29 03:38:56.945 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-01-29 03:38:57.413 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-01-29 03:38:57.885 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-01-29 03:38:58.357 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-01-29 03:38:58.830 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-01-29 03:38:59.301 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-01-29 03:38:59.771 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-01-29 03:39:00.244 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-01-29 03:39:00.716 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-01-29 03:39:01.181 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-01-29 03:39:01.652 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-01-29 03:39:02.123 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-01-29 03:39:02.596 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-01-29 03:39:03.070 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-01-29 03:39:03.542 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-01-29 03:39:04.014 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-01-29 03:39:04.480 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-01-29 03:39:04.950 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-01-29 03:39:05.421 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-01-29 03:39:05.891 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-01-29 03:39:06.362 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-01-29 03:39:06.830 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-01-29 03:39:07.297 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-01-29 03:39:07.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:07.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:39:07.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:07.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:39:07.690 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:39:07.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:07.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:39:07.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:39:07.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:07.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:39:07.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:39:07.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:39:07.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:07.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:39:07.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:39:07.716 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:39:07.716 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:39:07.762 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-01-29 03:39:07.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:39:07.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:39:07.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:07.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:08.228 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-01-29 03:39:08.693 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-01-29 03:39:09.159 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-01-29 03:39:09.627 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-01-29 03:39:10.092 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-01-29 03:39:10.559 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-01-29 03:39:11.024 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-01-29 03:39:11.492 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-01-29 03:39:11.958 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-01-29 03:39:12.424 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-01-29 03:39:12.889 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-01-29 03:39:13.360 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-01-29 03:39:13.831 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-01-29 03:39:14.301 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-01-29 03:39:14.772 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-01-29 03:39:15.240 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-01-29 03:39:15.713 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-01-29 03:39:16.185 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-01-29 03:39:16.658 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-01-29 03:39:17.131 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-01-29 03:39:17.603 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-01-29 03:39:18.074 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-01-29 03:39:18.543 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-01-29 03:39:19.015 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-01-29 03:39:19.488 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-01-29 03:39:19.961 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-01-29 03:39:20.432 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-01-29 03:39:20.904 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-01-29 03:39:21.369 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-01-29 03:39:21.834 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-01-29 03:39:22.303 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-01-29 03:39:22.775 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-01-29 03:39:23.247 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-01-29 03:39:23.718 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-01-29 03:39:24.185 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-01-29 03:39:24.650 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-01-29 03:39:25.119 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-01-29 03:39:25.585 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-01-29 03:39:26.056 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-01-29 03:39:26.524 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-01-29 03:39:26.992 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-01-29 03:39:27.459 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-01-29 03:39:27.929 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-01-29 03:39:28.400 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-01-29 03:39:28.871 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-01-29 03:39:29.340 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-01-29 03:39:29.809 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-01-29 03:39:30.283 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-01-29 03:39:30.755 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-01-29 03:39:31.226 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-01-29 03:39:31.697 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-01-29 03:39:32.170 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-01-29 03:39:32.642 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-01-29 03:39:33.112 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-01-29 03:39:33.585 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-01-29 03:39:34.057 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-01-29 03:39:34.528 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-01-29 03:39:34.999 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-01-29 03:39:35.470 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-01-29 03:39:35.940 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-01-29 03:39:36.410 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-01-29 03:39:36.882 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-01-29 03:39:37.353 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-01-29 03:39:37.825 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-01-29 03:39:38.296 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-01-29 03:39:38.762 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-01-29 03:39:39.230 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-01-29 03:39:39.700 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-01-29 03:39:40.168 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-01-29 03:39:40.635 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-01-29 03:39:41.105 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-01-29 03:39:41.579 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-01-29 03:39:42.051 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-01-29 03:39:42.523 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-01-29 03:39:42.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:42.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:39:42.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:42.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:39:42.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:42.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:39:42.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:39:42.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:42.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:39:42.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:39:42.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:39:42.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:42.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:39:42.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:39:42.946 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:39:42.946 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:39:42.991 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-01-29 03:39:42.994 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:39:42.994 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:39:42.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:42.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:39:43.456 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-01-29 03:39:43.921 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-01-29 03:39:44.386 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-01-29 03:39:44.853 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-01-29 03:39:45.325 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-01-29 03:39:45.797 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-01-29 03:39:46.267 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-01-29 03:39:46.731 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-01-29 03:39:47.201 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-01-29 03:39:47.668 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-01-29 03:39:48.134 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-01-29 03:39:48.606 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-01-29 03:39:49.079 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-01-29 03:39:49.552 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-01-29 03:39:50.024 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-01-29 03:39:50.497 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-01-29 03:39:50.970 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-01-29 03:39:51.440 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-01-29 03:39:51.912 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-01-29 03:39:52.383 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-01-29 03:39:52.855 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-01-29 03:39:53.328 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-01-29 03:39:53.800 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-01-29 03:39:54.273 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-01-29 03:39:54.741 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-01-29 03:39:55.210 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-01-29 03:39:55.683 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-01-29 03:39:56.155 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-01-29 03:39:56.628 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-01-29 03:39:57.100 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-01-29 03:39:57.568 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-01-29 03:39:58.035 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-01-29 03:39:58.500 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-01-29 03:39:58.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:39:58.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:39:58.821 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:39:58.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:39:58.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:39:58.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:39:58.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:39:58.826 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:39:58.826 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:39:58.826 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:39:58.826 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:39:58.826 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:39:58.826 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:39:58.826 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:03.833 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:03.833 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:40:03.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:03.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:03.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:03.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:03.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:03.837 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:03.837 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:03.837 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:03.837 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:40:03.838 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:40:03.838 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:40:03.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:03.838 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:03.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:03.838 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:40:03.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:03.838 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:40:03.839 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:40:03.839 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:40:03.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:03.839 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:03.839 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:03.839 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:40:03.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:03.839 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:40:03.840 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:40:03.840 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:40:03.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:03.841 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:03.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:03.841 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:40:03.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:03.841 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:40:03.843 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:40:03.843 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:40:03.843 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:03.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:03.844 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:03.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:03.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:03.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:03.844 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:03.844 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:40:03.845 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:40:08.856 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:08.857 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:40:08.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:08.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:08.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:08.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:08.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:08.868 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:08.868 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:08.868 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:08.868 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:40:08.871 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:40:08.871 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:40:08.872 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:08.872 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:08.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:08.872 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:40:08.872 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:08.872 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:40:08.875 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:40:08.875 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:40:08.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:08.875 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:08.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:08.875 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:40:08.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:08.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:40:08.878 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:40:08.878 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:40:08.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:08.878 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:08.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:08.878 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:40:08.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:08.878 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:40:08.882 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:40:08.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:40:08.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:40:08.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:40:08.882 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:40:08.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:40:08.883 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:40:08.883 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:40:08.883 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:08.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:08.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:08.888 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:40:09.358 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:40:09.418 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:40:09.420 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:40:09.421 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:40:09.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:09.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:09.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:09.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:09.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:09.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:09.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:09.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:09.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:09.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:09.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:09.454 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:40:09.454 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:40:09.495 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:09.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:09.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:09.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:09.823 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:40:09.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:09.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:09.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:09.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:10.292 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:40:10.764 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:40:10.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:10.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:10.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:10.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:10.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:10.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:10.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:10.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:10.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:10.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:10.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:10.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:10.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:10.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:10.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:10.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:10.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:10.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:10.937 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:40:10.937 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:40:10.943 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:40:10.943 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:40:10.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:10.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:11.233 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:40:11.700 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:40:11.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:11.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:11.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:11.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:12.174 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:40:12.647 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:40:12.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:12.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:12.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:12.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:13.120 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:40:13.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:13.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:13.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:13.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:13.234 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:40:13.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:13.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:13.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:13.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:13.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:13.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:13.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:13.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:13.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:13.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:13.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:40:13.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:40:13.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:13.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:13.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:13.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:13.590 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:40:13.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:13.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:13.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:13.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:14.061 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:40:14.534 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:40:15.005 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:40:15.478 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:40:15.950 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:40:16.421 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:40:16.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:16.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:16.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:16.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:16.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:16.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:16.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:16.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:16.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:16.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:16.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:16.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:16.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:16.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:16.598 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:40:16.598 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:40:16.601 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:40:16.601 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:40:16.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:16.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:16.892 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:40:17.361 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:40:17.828 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:40:17.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:17.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:17.912 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:40:17.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:17.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:17.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:17.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:17.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:17.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:17.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:17.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:17.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:17.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:40:17.916 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:40:17.916 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1959 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:17.916 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:17.916 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:17.916 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:40:22.920 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:40:22.920 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:40:22.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:22.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:22.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:22.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:22.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:40:22.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:22.932 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:22.933 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:40:22.933 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:40:22.935 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:40:22.936 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:40:22.936 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:22.936 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:22.936 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:40:22.936 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:40:22.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:40:22.937 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:40:22.939 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:40:22.939 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:40:22.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:22.939 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:22.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:40:22.939 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:40:22.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:40:22.939 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:40:22.941 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:40:22.941 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:40:22.941 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:22.941 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:40:22.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:40:22.941 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:40:22.942 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:40:22.942 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:40:22.944 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:40:22.944 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:40:22.944 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:40:22.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:40:22.949 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:40:23.426 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:40:23.468 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:40:23.469 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:40:23.470 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:40:23.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:23.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:23.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:23.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:23.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:23.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:23.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:23.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:23.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:23.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:23.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:23.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:40:23.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:40:23.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:23.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:23.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:23.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:23.898 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:40:23.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:23.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:23.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:23.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:24.369 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:40:24.841 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:40:24.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:24.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:24.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:24.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:25.314 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:40:25.787 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:40:25.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:25.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:25.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:25.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:26.259 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:40:26.732 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:40:26.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:26.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:26.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:26.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:27.205 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:40:27.677 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:40:27.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:40:27.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:40:27.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:40:27.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:40:28.148 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:40:28.621 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:40:29.094 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:40:29.566 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:40:30.037 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:40:30.503 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:40:30.974 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:40:31.440 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:40:31.906 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:40:32.377 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:40:32.851 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:40:33.324 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:40:33.796 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:40:34.267 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:40:34.740 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:40:35.205 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:40:35.674 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:40:36.148 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:40:36.621 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:40:37.093 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:40:37.564 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:40:38.037 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:40:38.510 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:40:38.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:38.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:38.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:38.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:38.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:38.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:38.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:38.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:38.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:38.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:38.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:38.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:38.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:38.853 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:40:38.853 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:40:38.903 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:40:38.903 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:40:38.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:38.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:38.998 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:40:39.471 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:40:39.943 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:40:40.415 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:40:40.884 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:40:41.355 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:40:41.827 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:40:42.299 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:40:42.771 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:40:43.243 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:40:43.711 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:40:44.184 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:40:44.656 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:40:45.128 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:40:45.599 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:40:46.071 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:40:46.545 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:40:47.017 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:40:47.490 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:40:47.963 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:40:48.436 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:40:48.908 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:40:49.379 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:40:49.850 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:40:50.323 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:40:50.795 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:40:51.266 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:40:51.739 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:40:52.212 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:40:52.684 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:40:53.155 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:40:53.628 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:40:53.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:53.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:53.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:53.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:53.981 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:40:54.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:54.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:54.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:54.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:40:54.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:40:54.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:40:54.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:40:54.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:54.009 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:54.009 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:54.009 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:40:54.009 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:40:54.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:40:54.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:40:54.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:54.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:40:54.101 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:40:54.573 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:40:55.044 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:40:55.515 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:40:55.985 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:40:56.456 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:40:56.927 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:40:57.398 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:40:57.868 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:40:58.340 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:40:58.805 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:40:59.271 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:40:59.736 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:41:00.203 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:41:00.674 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:41:01.145 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:41:01.616 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:41:02.086 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:41:02.553 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:41:03.021 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-01-29 03:41:03.492 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-01-29 03:41:03.960 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-01-29 03:41:04.428 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-01-29 03:41:04.897 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-01-29 03:41:05.368 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-01-29 03:41:05.838 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-01-29 03:41:06.304 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-01-29 03:41:06.769 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-01-29 03:41:07.236 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-01-29 03:41:07.704 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-01-29 03:41:08.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:08.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:08.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:08.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:08.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:08.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:08.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:08.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:08.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:08.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:08.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:08.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:08.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:08.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:08.169 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:41:08.169 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:41:08.174 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-01-29 03:41:08.220 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:41:08.220 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:41:08.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:08.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:08.645 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-01-29 03:41:09.117 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-01-29 03:41:09.591 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-01-29 03:41:10.060 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-01-29 03:41:10.529 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-01-29 03:41:10.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:10.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:10.924 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:41:10.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:10.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:10.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:10.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:10.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:10.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:10.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:10.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:10.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:10.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:41:10.932 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10390 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10390 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10390 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10390 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:10.932 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=10391 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:41:15.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:15.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:41:15.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:15.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:15.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:15.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:15.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:15.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:41:15.943 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:15.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:41:15.943 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:41:15.944 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:41:15.944 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:41:15.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:41:15.944 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:15.945 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:15.945 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:41:15.945 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:41:15.945 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:41:15.946 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:41:15.947 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:41:15.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:41:15.947 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:15.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:15.947 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:41:15.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:41:15.947 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:41:15.948 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:41:15.948 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:41:15.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:41:15.948 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:41:15.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:41:15.948 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:41:15.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:41:15.948 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:41:15.950 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:41:15.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:41:15.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:41:15.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:41:15.950 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:41:15.951 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:41:15.951 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:41:15.951 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:41:15.955 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:41:16.429 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:41:16.478 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:41:16.481 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:41:16.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:16.483 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:41:16.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:16.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:16.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:16.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:16.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:16.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:16.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:16.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:16.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:16.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:16.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:41:16.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:41:16.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:16.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:16.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:16.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:16.898 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:41:16.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:16.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:16.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:16.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:17.364 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:41:17.833 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:41:17.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:17.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:17.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:17.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:18.305 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:41:18.776 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:41:18.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:18.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:18.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:18.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:19.246 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:41:19.720 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:41:19.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:19.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:19.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:19.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:20.193 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:41:20.665 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:41:20.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:20.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:20.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:20.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:21.137 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:41:21.609 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:41:22.082 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:41:22.554 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:41:23.025 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:41:23.496 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:41:23.966 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:41:24.433 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:41:24.903 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:41:25.371 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:41:25.844 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:41:26.316 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:41:26.784 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:41:26.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:26.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:26.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:26.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:27.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:27.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:27.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:27.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:27.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:27.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:27.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:27.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:27.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:27.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:27.012 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:41:27.012 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:41:27.062 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:41:27.062 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:41:27.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:27.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:27.253 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:41:27.723 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:41:28.191 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:41:28.657 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:41:29.130 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:41:29.602 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:41:30.071 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:41:30.539 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:41:31.007 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:41:31.479 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:41:31.953 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:41:32.426 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:41:32.899 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:41:33.372 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:41:33.845 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:41:34.317 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:41:34.786 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:41:35.256 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:41:35.728 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:41:36.201 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:41:36.671 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:41:37.144 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:41:37.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:37.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:37.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:37.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:37.318 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:41:37.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:37.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:37.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:37.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:37.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:37.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:37.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:37.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:37.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:37.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:37.345 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:41:37.345 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:41:37.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:37.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:37.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:37.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:37.616 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:41:38.087 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:41:38.557 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:41:39.024 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-01-29 03:41:39.495 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-01-29 03:41:39.966 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-01-29 03:41:40.439 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-01-29 03:41:40.912 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-01-29 03:41:41.382 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-01-29 03:41:41.854 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-01-29 03:41:42.326 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-01-29 03:41:42.794 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-01-29 03:41:43.263 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-01-29 03:41:43.734 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-01-29 03:41:44.205 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-01-29 03:41:44.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:44.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:44.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:44.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:44.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:44.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:44.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:44.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:44.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:44.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:41:44.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:44.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:44.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:41:44.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:41:44.270 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:41:44.270 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:41:44.295 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:41:44.296 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:41:44.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:44.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:44.675 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-01-29 03:41:45.140 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-01-29 03:41:45.606 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-01-29 03:41:46.073 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-01-29 03:41:46.545 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-01-29 03:41:47.013 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-01-29 03:41:47.483 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-01-29 03:41:47.948 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-01-29 03:41:48.413 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-01-29 03:41:48.878 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-01-29 03:41:49.346 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-01-29 03:41:49.815 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-01-29 03:41:50.283 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-01-29 03:41:50.754 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-01-29 03:41:51.226 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-01-29 03:41:51.694 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-01-29 03:41:52.161 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-01-29 03:41:52.630 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-01-29 03:41:53.095 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-01-29 03:41:53.565 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-01-29 03:41:54.036 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-01-29 03:41:54.509 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-01-29 03:41:54.977 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-01-29 03:41:55.449 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-01-29 03:41:55.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:41:55.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:41:55.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:41:55.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:41:55.558 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:41:55.564 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:41:55.564 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:41:55.564 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:41:55.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:00.571 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:00.571 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:42:00.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:00.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:00.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:00.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:00.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:00.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:00.584 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:00.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:00.584 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:42:00.586 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:42:00.586 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:42:00.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:00.586 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:00.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:00.586 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:42:00.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:00.586 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:42:00.588 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:42:00.588 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:42:00.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:00.588 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:00.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:00.588 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:42:00.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:00.588 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:42:00.589 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:42:00.589 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:42:00.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:00.589 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:00.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:00.590 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:42:00.590 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:00.590 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:42:00.592 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:42:00.592 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:42:00.592 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:00.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:00.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:00.597 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:42:01.068 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:42:01.113 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:42:01.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:01.116 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:42:01.118 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:42:01.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:01.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:01.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:01.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:01.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:01.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:01.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:01.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:01.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:01.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:01.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:01.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:01.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:01.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:01.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:01.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:01.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:01.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:01.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:01.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:01.536 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:42:01.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:01.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:01.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:01.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:01.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:01.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:01.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:01.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:01.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:01.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:01.552 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:01.552 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:01.581 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:42:01.581 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:42:01.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:01.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:01.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:01.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:01.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:01.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:02.006 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:42:02.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:02.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:02.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:02.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:02.107 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:42:02.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:02.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:02.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:02.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:02.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:02.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:02.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:02.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:02.131 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:02.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:02.131 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:02.131 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:02.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:02.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:02.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:02.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:02.472 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:42:02.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:02.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:02.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:02.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:02.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:02.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:02.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:02.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:02.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:02.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:02.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:02.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:02.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:02.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:02.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:02.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:02.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:02.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:02.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:02.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:02.939 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:42:02.943 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:42:02.943 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:42:02.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:02.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:03.409 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:42:03.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:03.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:03.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:03.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:03.880 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:42:04.353 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:42:04.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:04.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:04.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:04.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:04.817 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:42:05.289 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:42:05.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:05.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:05.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:05.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:05.759 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:42:06.225 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:42:06.690 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:42:06.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:06.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:06.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:06.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:06.967 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:42:06.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:06.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:06.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:06.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:06.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:06.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:06.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:42:06.985 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:42:06.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:06.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:06.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:06.986 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1392 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.986 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1392 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.986 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1392 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.986 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1392 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.986 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1392 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1392 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1392 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:06.987 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=1393 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:11.987 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:11.987 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:42:11.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:11.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:11.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:11.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:12.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:12.002 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:12.002 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:12.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:12.003 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:42:12.008 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:42:12.008 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:42:12.008 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:12.008 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:12.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:12.009 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:42:12.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:12.009 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:42:12.012 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:42:12.013 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:42:12.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:12.013 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:12.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:12.013 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:42:12.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:12.013 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:42:12.016 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:42:12.016 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:42:12.016 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:12.016 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:12.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:12.017 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:42:12.017 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:12.017 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:42:12.021 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:42:12.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:42:12.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:42:12.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:42:12.021 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:42:12.022 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:42:12.022 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:42:12.022 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.022 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:12.027 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:42:12.498 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:42:12.555 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:42:12.559 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:42:12.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:12.562 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:42:12.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:12.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:12.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:12.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:12.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:12.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:12.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:12.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:12.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:12.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:12.597 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:12.597 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:12.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:12.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:12.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:12.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:12.968 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:42:13.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:13.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:13.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:13.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:13.441 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:42:13.913 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:42:14.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:14.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:14.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:14.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:14.385 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:42:14.857 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:42:15.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:15.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:15.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:15.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:15.330 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:42:15.802 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:42:15.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:15.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:15.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:15.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:15.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:15.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:15.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:15.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:15.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:15.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:15.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:15.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:15.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:15.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:15.883 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:15.883 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:15.890 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:42:15.890 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:42:15.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:15.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:16.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:16.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:16.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:16.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:16.275 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:42:16.748 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:42:17.031 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:17.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:17.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:17.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:17.220 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:42:17.693 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:42:18.165 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:42:18.633 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:42:19.105 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:42:19.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:19.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:19.230 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:19.230 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:19.230 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:42:19.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:19.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:19.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:19.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:19.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:19.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:19.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:19.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:19.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:19.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:19.259 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:19.259 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:19.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:19.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:19.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:19.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:19.576 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:42:20.048 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:42:20.519 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:42:20.991 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:42:21.458 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:42:21.929 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:42:22.400 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:42:22.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:22.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:22.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:22.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:22.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:22.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:22.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:22.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:22.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:22.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:22.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:22.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:22.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:22.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:22.820 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:22.820 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:22.869 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:42:22.869 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:42:22.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:22.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:22.872 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:42:23.344 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:42:23.808 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:42:24.275 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:42:24.748 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:42:25.220 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:42:25.692 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:42:26.164 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:42:26.636 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:42:27.108 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:42:27.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:27.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:27.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:27.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:27.193 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:42:27.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:27.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:27.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:27.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:27.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:27.207 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:27.207 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:27.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:27.207 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:27.207 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:42:27.207 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:42:32.215 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:32.215 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:42:32.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:32.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:32.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:32.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:32.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:32.223 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:32.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:32.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:42:32.224 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:42:32.227 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:42:32.227 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:42:32.227 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:32.227 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:32.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:32.228 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:42:32.228 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:42:32.229 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:42:32.230 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:42:32.231 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:42:32.231 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:32.231 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:32.231 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:32.232 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:42:32.232 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:42:32.232 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:42:32.235 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:42:32.235 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:42:32.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:32.235 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:42:32.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:32.236 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:42:32.236 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:42:32.236 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:42:32.240 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:42:32.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:42:32.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:42:32.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:42:32.240 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:42:32.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:42:32.241 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:42:32.241 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:42:32.241 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:42:32.246 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:42:32.718 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:42:32.781 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:42:32.782 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:42:32.783 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:42:32.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:32.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:32.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:32.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:32.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:32.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:32.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:32.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:32.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:32.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:32.826 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:32.826 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:32.826 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:32.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:32.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:32.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:32.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.190 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:42:33.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:33.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:33.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:33.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:33.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:33.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:33.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:33.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:33.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:33.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:33.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:33.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:33.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:33.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:33.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:33.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:33.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:33.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:33.280 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:42:33.280 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:42:33.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.662 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:42:33.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:33.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:33.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:33.882 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:42:33.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:33.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:33.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:33.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:33.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:33.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:33.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:33.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:33.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:33.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:33.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:33.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:33.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:33.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:33.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:34.132 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:42:34.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:34.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:34.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:34.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:34.602 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:42:34.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:34.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:35.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:35.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:35.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:35.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:35.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:35.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:35.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:35.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:42:35.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:42:35.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:35.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:42:35.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:42:35.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:42:35.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:42:35.068 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:42:35.073 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:42:35.073 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:42:35.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:35.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:42:35.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:35.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:35.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:35.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:35.537 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:42:36.010 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:42:36.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:36.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:36.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:36.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:36.482 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:42:36.953 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:42:37.250 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:37.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:37.251 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:37.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:37.427 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:42:37.898 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:42:38.371 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:42:38.844 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:42:39.317 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:42:39.789 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:42:40.257 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:42:40.730 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:42:41.202 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:42:41.674 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:42:42.145 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:42:42.610 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:42:43.079 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:42:43.552 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:42:44.025 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:42:44.497 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:42:44.969 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:42:45.442 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:42:45.915 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:42:46.386 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:42:46.858 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:42:47.332 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:42:47.804 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:42:48.275 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:42:48.746 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-01-29 03:42:49.211 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-01-29 03:42:49.682 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-01-29 03:42:50.151 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-01-29 03:42:50.618 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-01-29 03:42:51.091 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-01-29 03:42:51.563 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-01-29 03:42:52.027 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-01-29 03:42:52.494 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-01-29 03:42:52.964 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-01-29 03:42:53.428 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-01-29 03:42:53.893 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-01-29 03:42:54.360 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-01-29 03:42:54.829 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-01-29 03:42:55.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:42:55.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:42:55.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:42:55.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:42:55.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:42:55.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:42:55.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:42:55.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:42:55.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:42:55.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:42:55.029 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4942 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:55.029 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4942 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:55.030 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4942 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:55.030 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4942 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:55.030 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4942 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:55.030 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=4942 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:42:55.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:42:55.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:42:55.035 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:42:55.035 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:00.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:00.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:00.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:00.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:00.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:00.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:00.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:00.039 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:00.039 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:00.039 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:00.039 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:00.042 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:00.042 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:00.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:00.042 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:00.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:00.042 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:00.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:00.042 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:00.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:00.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:00.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:00.045 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:00.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:00.045 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:00.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:00.045 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:00.047 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:00.047 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:00.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:00.047 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:00.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:00.047 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:00.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:00.047 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:00.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:00.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:00.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:00.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:00.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:00.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:43:00.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:43:00.050 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:00.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:00.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:00.054 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:00.518 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:00.580 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:00.582 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:00.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:00.583 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:00.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:00.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:00.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:00.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:00.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:00.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:00.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:00.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:00.624 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:00.624 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:00.624 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:00.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:00.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:00.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:00.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:00.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:00.985 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:01.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:01.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:01.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:01.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:01.456 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:01.927 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:43:02.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:02.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:02.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:02.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:02.400 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:43:02.873 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:43:03.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:03.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:03.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:03.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:03.341 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:43:03.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:03.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:03.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:03.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:03.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:03.513 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:03.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:03.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:03.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:03.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:03.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:03.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:03.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:03.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:03.522 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:03.522 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:03.574 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:43:03.574 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:43:03.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:03.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:03.811 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:43:04.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:04.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:04.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:04.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:04.276 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:43:04.741 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:43:05.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:05.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:05.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:05.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:05.214 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:43:05.687 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:43:06.160 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:43:06.632 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:43:07.105 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:43:07.579 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:43:08.050 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:43:08.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:08.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:08.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:08.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:08.071 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:43:08.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:08.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:08.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:08.083 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:08.083 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:08.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:08.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:08.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:08.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:08.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:08.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:08.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:08.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:08.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:08.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:08.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:08.518 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:43:08.989 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:43:09.462 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:43:09.933 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:43:10.404 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:43:10.872 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:43:11.345 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:43:11.818 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:43:12.290 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:43:12.761 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:43:13.234 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:43:13.707 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:43:14.174 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:43:14.641 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:43:14.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:14.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:14.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:14.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:14.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:14.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:14.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:14.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:14.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:14.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:14.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:14.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:14.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:14.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:14.824 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:14.824 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:14.874 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:43:14.874 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:43:14.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:14.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:15.108 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:43:15.577 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:43:15.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:15.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:15.660 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:43:15.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:15.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:15.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:15.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:15.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:15.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:15.664 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:15.664 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:15.664 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:15.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:15.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:15.665 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3387 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:15.665 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:15.665 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:15.665 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:15.665 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:15.665 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:20.670 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:20.670 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:20.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:20.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:20.670 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:20.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:20.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:20.685 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:20.685 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:20.686 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:20.686 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:20.691 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:20.691 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:20.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:20.692 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:20.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:20.692 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:20.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:20.692 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:20.699 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:20.699 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:20.699 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:20.699 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:20.700 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:20.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:20.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:20.700 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:20.705 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:20.705 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:20.705 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:20.705 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:20.705 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:20.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:20.706 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:20.706 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:43:20.711 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:43:20.711 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:20.711 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.711 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:20.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:20.715 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:21.179 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:21.241 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:21.242 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:21.244 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:21.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:21.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:21.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:21.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:21.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:21.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:21.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:21.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:21.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:21.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:21.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:21.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:21.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:21.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:21.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:21.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:21.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:21.646 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:21.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:21.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:21.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:21.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:22.113 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:22.579 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:43:22.715 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:22.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:22.716 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:22.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:23.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:23.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:23.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:23.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:23.049 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:43:23.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:23.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:23.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:23.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:23.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:23.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:23.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:23.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:23.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:23.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:23.072 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:23.072 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:23.092 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:43:23.092 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-01-29 03:43:23.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:23.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:23.514 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:43:23.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:23.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:23.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:23.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:23.984 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:43:24.452 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:43:24.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:24.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:24.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:24.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:24.919 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:43:25.391 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:43:25.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:25.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:25.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:25.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:25.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:25.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:25.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:25.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:25.830 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:43:25.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:25.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:25.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:25.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:25.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:25.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:25.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:25.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:25.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:25.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:25.856 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:25.856 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:25.863 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:43:25.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:25.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:25.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:25.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:26.331 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:43:26.802 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:43:27.273 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:43:27.746 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:43:28.219 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:43:28.691 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:43:29.162 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:43:29.633 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:43:30.106 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:43:30.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:30.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:30.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:30.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:30.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:30.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:30.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:30.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:30.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:43:30.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:30.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:30.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:43:30.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:43:30.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:43:30.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:43:30.338 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.128.22:6700) Recv SETFH cmd
2026-01-29 03:43:30.338 [INFO] transceiver.py:201 (MS@172.18.128.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-01-29 03:43:30.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:30.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:43:30.575 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:43:31.047 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:43:31.520 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:43:31.991 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:43:32.464 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:43:32.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:43:32.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:43:32.546 [INFO] transceiver.py:205 (MS@172.18.128.22:6700) Frequency hopping disabled
2026-01-29 03:43:32.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:32.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:32.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:32.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:32.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:32.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:32.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:32.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:32.549 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:32.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:32.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:32.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2571 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:32.549 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2571 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:32.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2571 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:32.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2571 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:32.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2571 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:32.550 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=2571 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:37.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:37.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:37.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:37.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:37.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:37.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:37.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:37.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:37.566 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:37.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:37.566 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:37.569 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:37.569 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:37.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:37.570 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:37.570 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:37.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:37.570 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:37.570 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:37.573 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:37.574 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:37.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:37.574 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:37.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:37.574 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:37.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:37.574 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:37.577 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:37.577 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:37.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:37.577 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:37.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:37.577 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:37.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:37.577 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:37.580 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:37.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:43:37.581 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:43:37.581 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:37.581 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:37.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:37.586 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:38.058 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:38.113 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:38.116 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:38.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.118 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:38.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.523 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:38.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:38.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:38.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:38.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:38.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:38.992 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:39.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:39.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:39.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:39.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:39.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:39.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:39.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:39.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:39.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:39.457 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:43:39.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:39.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:39.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:39.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:39.462 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:39.462 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:39.462 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:39.462 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:39.462 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=409 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.462 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=409 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=409 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=409 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=409 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=409 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.463 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=410 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=411 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.464 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.465 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.465 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.465 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.465 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.465 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:39.465 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:44.462 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:44.462 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:44.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:44.462 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:44.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:44.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:44.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:44.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:44.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:44.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:44.472 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:44.475 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:44.475 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:44.475 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:44.475 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:44.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:44.475 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:44.475 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:44.475 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:44.477 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:44.477 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:44.477 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:44.477 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:44.477 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:44.477 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:44.477 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:44.477 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:44.479 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:44.479 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:44.479 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:44.479 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:44.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:44.479 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:44.479 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:44.479 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.481 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:43:44.481 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:43:44.481 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:44.481 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:44.486 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:44.963 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:45.009 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:45.011 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:45.013 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:45.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.428 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:45.486 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:45.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:45.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:45.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:45.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:45.899 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:46.366 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:43:46.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:46.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:46.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:46.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:46.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:46.383 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:46.383 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:46.383 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:46.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:46.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:46.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=413 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=413 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=413 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.384 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.385 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.385 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:46.385 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=414 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:43:51.384 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:51.384 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:51.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:51.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:51.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:51.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:51.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:51.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:51.393 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:51.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:51.393 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:51.397 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:51.398 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:51.398 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:51.398 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:51.398 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:51.398 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:51.398 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:51.398 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:51.402 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:51.402 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:51.402 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:51.403 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:51.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:51.403 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:51.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:51.403 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:51.406 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:51.407 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:51.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:51.407 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:51.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:51.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:51.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:51.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:51.412 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:51.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:51.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:51.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:51.412 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.413 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:43:51.413 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:43:51.413 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:51.413 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:51.418 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:51.888 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:51.944 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:51.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.946 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:51.946 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:51.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:51.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.357 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:52.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:52.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:52.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:52.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:52.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.829 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:52.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:52.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:53.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:53.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:53.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:53.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:53.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:53.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:53.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:53.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:53.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:53.267 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:53.267 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:53.267 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:43:53.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:53.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:58.271 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:43:58.271 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:43:58.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:58.272 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:58.272 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:58.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:58.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:43:58.284 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:58.284 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:58.285 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:43:58.285 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:43:58.287 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:43:58.287 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:43:58.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:58.288 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:58.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:43:58.288 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:43:58.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:43:58.288 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:43:58.289 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:43:58.290 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:43:58.290 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:58.290 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:58.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:43:58.290 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:43:58.290 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:43:58.290 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:43:58.292 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:43:58.292 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:43:58.292 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:58.292 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:43:58.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:43:58.293 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:43:58.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:43:58.293 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:43:58.296 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:43:58.296 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:43:58.296 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:43:58.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:43:58.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:43:58.301 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:43:58.773 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:43:58.829 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:43:58.831 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:43:58.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.833 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:43:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:58.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.240 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:43:59.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:43:59.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:43:59.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:43:59.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:43:59.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.708 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:43:59.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:43:59.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:00.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:00.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:00.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:00.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:00.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:00.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:00.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:00.157 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:00.157 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:00.158 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:00.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:00.158 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:00.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:00.158 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:00.158 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:00.158 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:00.159 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:00.159 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:00.159 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:00.159 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:05.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:05.159 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:05.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:05.159 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:05.159 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:05.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:05.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:05.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:05.167 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:05.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:05.167 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:05.168 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:05.168 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:05.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:05.168 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:05.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:05.169 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:05.169 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:05.169 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:05.170 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:05.170 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:05.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:05.170 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:05.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:05.170 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:05.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:05.170 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:05.172 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:05.172 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:05.172 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:05.172 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:05.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:05.172 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:05.172 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:05.172 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:05.176 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:05.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:05.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:05.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:05.176 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.177 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:05.177 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:05.177 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:05.177 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:05.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.182 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:05.647 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:05.717 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:05.718 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:05.720 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:05.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:05.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:05.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.111 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:44:06.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:06.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:06.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:06.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:06.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.583 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:44:06.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:06.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:07.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:07.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:07.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:07.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:07.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:07.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:07.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:07.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:07.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:07.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:07.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:07.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:07.049 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:12.055 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:12.055 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:12.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:12.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:12.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:12.055 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:12.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:12.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:12.066 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:12.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:12.066 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:12.069 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:12.069 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:12.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:12.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:12.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:12.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:12.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:12.070 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:12.073 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:12.074 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:12.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:12.074 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:12.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:12.074 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:12.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:12.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:12.078 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:12.078 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:12.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:12.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:12.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:12.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:12.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:12.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:12.084 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:12.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.085 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:12.085 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:12.085 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:12.085 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:12.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:12.090 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:12.561 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:12.623 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:12.626 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:12.628 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:12.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:12.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:12.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.029 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:44:13.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:13.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:13.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:13.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:13.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.497 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:44:13.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.965 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:44:13.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:13.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:13.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:13.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:13.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:13.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:13.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:13.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:13.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:13.993 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:13.993 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:13.993 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:13.993 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=415 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.993 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=415 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.993 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=415 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.993 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=415 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=415 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=415 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:13.994 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=416 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:18.997 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:18.997 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:18.997 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:18.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:18.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:18.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:19.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:19.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:19.005 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:19.005 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:19.005 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:19.008 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:19.008 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:19.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:19.009 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:19.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:19.009 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:19.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:19.009 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:19.012 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:19.012 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:19.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:19.012 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:19.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:19.012 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:19.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:19.012 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:19.015 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:19.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:19.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:19.015 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:19.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:19.015 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:19.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:19.015 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.019 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:19.019 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:19.019 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:19.019 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:19.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:19.024 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:19.493 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:19.543 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:19.544 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:19.545 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:19.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:19.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:19.961 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:44:20.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:20.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:20.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:20.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:20.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.433 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:44:20.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:20.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:20.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:20.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:20.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:20.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:20.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:20.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:20.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:20.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:20.877 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:20.877 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:20.877 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:20.877 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=405 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:25.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:25.886 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:25.886 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:25.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:25.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:25.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:25.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:25.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:25.896 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:25.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:25.896 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:25.898 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:25.899 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:25.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:25.899 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:25.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:25.899 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:25.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:25.899 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:25.901 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:25.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:25.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:25.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:25.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:25.901 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:25.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:25.902 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:25.903 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:25.903 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:25.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:25.904 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:25.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:25.904 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:25.904 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:25.904 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:25.907 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:25.907 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:25.907 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:25.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:25.912 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:26.375 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:26.441 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:26.443 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:26.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.446 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:26.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:26.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:26.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:26.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:26.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:26.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:26.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:26.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:26.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:26.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:26.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:26.528 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:26.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=137 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:26.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=137 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:26.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=137 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:26.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=137 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:26.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=137 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:26.528 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=137 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:31.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:31.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:31.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:31.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:31.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:31.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:31.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:31.545 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:31.545 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:31.545 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:31.545 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:31.548 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:31.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:31.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:31.549 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:31.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:31.549 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:31.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:31.549 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:31.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:31.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:31.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:31.552 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:31.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:31.552 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:31.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:31.552 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:31.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:31.554 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:31.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:31.555 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:31.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:31.555 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:31.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:31.555 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:31.558 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:31.558 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:31.558 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:31.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:31.563 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:32.034 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:32.082 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:32.086 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:32.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.088 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:32.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:32.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:32.205 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:32.205 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:32.205 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:32.205 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:32.206 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:32.206 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:32.206 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:32.206 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:32.206 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:32.206 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:32.206 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:37.216 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:37.216 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:37.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:37.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:37.217 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:37.217 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:37.231 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:37.232 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:37.232 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:37.232 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:37.232 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:37.235 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:37.235 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:37.236 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:37.236 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:37.236 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:37.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:37.236 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:37.236 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:37.241 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:37.241 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:37.241 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:37.241 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:37.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:37.242 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:37.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:37.242 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:37.247 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:37.247 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:37.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:37.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:37.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:37.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:37.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:37.248 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:37.257 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:37.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:37.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:37.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:37.257 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:37.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:37.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:37.258 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:37.258 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:37.258 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:37.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:37.263 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:37.735 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:37.798 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:37.800 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:37.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.802 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:37.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:37.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:37.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:37.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:37.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:37.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:37.902 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:37.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:37.902 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:37.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:37.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:37.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:37.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=140 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:37.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=140 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:37.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=140 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:37.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=140 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:37.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=140 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:37.902 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=140 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:44:42.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:42.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:42.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:42.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:42.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:42.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:42.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:42.917 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:42.917 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:42.917 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:42.917 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:42.921 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:42.922 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:42.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:42.922 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:42.922 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:42.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:42.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:42.922 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:42.930 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:42.930 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:42.930 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:42.930 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:42.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:42.931 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:42.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:42.931 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:42.939 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:42.939 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:42.939 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:42.939 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:42.940 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:42.940 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:42.940 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:42.940 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:42.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:42.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:42.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:42.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:42.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:42.949 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:42.950 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:42.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:42.954 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:43.425 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:43.488 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:43.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.492 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:43.495 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:43.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:43.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:43.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:43.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:43.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:43.585 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:43.585 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:43.585 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:43.585 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:43.585 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:43.586 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:43.586 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:48.593 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:48.593 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:48.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:48.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:48.593 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:48.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:48.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:48.603 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:48.603 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:48.604 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:48.604 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:48.609 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:48.609 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:48.609 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:48.609 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:48.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:48.610 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:48.610 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:48.610 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:48.614 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:48.615 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:48.615 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:48.615 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:48.615 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:48.615 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:48.615 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:48.615 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:48.619 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:48.619 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:48.619 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:48.619 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:48.619 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:48.619 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:48.620 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:48.620 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:48.624 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:48.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:48.624 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:48.624 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:48.624 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:48.624 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:48.625 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:48.625 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:48.625 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:48.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:48.630 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:49.102 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:49.160 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:49.162 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:49.163 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:49.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:49.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:49.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:49.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:49.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:49.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:49.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:49.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:49.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:49.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:49.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:49.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:49.233 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:54.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:54.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:54.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:54.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:54.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:54.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:54.248 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:54.249 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:54.249 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:54.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:54.250 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:54.255 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:54.255 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:54.256 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:54.256 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:54.256 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:54.256 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:54.257 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:54.257 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:54.260 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:54.260 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:54.260 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:54.260 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:54.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:54.261 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:54.261 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:54.261 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:54.263 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:54.264 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:54.264 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:54.264 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:54.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:54.264 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:54.264 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:54.264 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.267 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:54.267 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:54.267 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:54.267 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:54.272 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:44:54.750 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:44:54.792 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:44:54.794 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:44:54.796 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:44:54.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:54.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:44:54.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:44:54.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:44:54.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:44:54.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:44:54.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:54.933 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:54.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:54.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:54.934 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:44:59.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:44:59.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:44:59.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:59.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:59.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:59.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:59.956 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:44:59.957 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:59.957 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:59.958 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:44:59.958 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:44:59.961 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:44:59.962 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:44:59.962 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:59.962 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:59.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:44:59.963 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:44:59.963 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:44:59.963 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:44:59.965 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:44:59.966 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:44:59.966 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:59.966 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:59.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:44:59.966 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:44:59.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:44:59.967 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:44:59.969 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:44:59.969 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:44:59.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:59.969 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:44:59.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:44:59.969 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:44:59.970 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:44:59.970 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.974 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:44:59.974 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:44:59.974 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:44:59.975 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:44:59.979 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:00.451 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:00.511 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:00.513 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:00.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.515 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:00.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:00.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:00.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:00.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:00.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:00.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:00.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:00.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:00.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:00.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:00.599 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:00.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:00.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:05.607 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:05.607 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:05.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:05.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:05.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:05.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:05.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:05.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:05.620 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:05.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:05.620 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:05.621 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:05.621 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:05.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:05.621 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:05.622 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:05.622 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:05.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:05.622 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:05.623 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:05.623 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:05.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:05.623 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:05.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:05.623 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:05.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:05.623 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:05.624 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:05.624 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:05.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:05.625 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:05.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:05.625 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:05.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:05.625 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:45:05.627 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:45:05.627 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:05.627 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:05.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:05.632 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:06.095 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:06.158 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:06.160 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:06.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:06.162 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:06.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:06.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:06.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:06.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:06.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:06.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:06.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:06.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:06.561 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:06.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:06.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:06.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:06.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:07.033 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:45:07.506 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:45:07.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:07.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:07.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:07.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:07.975 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:45:08.442 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:45:08.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:08.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:08.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:08.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:08.913 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:45:09.384 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:45:09.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:09.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:09.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:09.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:09.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:09.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:09.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:09.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:09.607 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:09.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:09.607 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:09.607 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:09.607 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:09.608 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:09.608 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:09.608 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:09.608 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:09.608 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:09.608 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:14.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:14.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:14.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:14.611 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:14.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:14.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:14.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:14.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:14.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:14.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:14.614 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:14.615 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:14.615 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:14.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:14.615 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:14.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:14.616 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:14.616 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:14.616 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:14.616 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:14.616 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:14.616 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:14.616 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:14.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:14.617 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:14.617 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:14.617 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:14.618 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:14.618 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:14.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:14.618 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:14.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:14.618 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:14.618 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:14.618 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:45:14.620 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:45:14.620 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:14.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:14.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:14.625 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:15.103 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:15.147 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:15.149 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:15.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:15.152 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:15.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:15.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:15.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:15.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:15.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:15.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:15.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:15.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:15.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:15.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:15.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:15.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:15.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:15.575 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:15.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:15.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:15.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:15.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:15.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:15.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:15.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:15.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:15.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:15.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:15.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:15.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:15.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:15.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:15.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:15.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:15.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:15.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:15.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:15.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:15.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:15.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:15.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:15.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:15.723 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:15.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:15.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:15.723 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:15.723 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:15.723 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:15.723 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:15.723 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:15.723 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:20.730 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:20.730 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:20.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:20.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:20.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:20.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:20.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:20.740 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:20.740 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:20.741 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:20.741 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:20.745 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:20.745 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:20.746 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:20.746 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:20.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:20.746 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:20.746 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:20.746 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:20.750 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:20.750 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:20.750 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:20.750 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:20.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:20.751 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:20.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:20.751 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:20.754 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:20.754 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:20.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:20.755 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:20.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:20.755 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:20.755 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:20.755 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:20.760 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.761 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:45:20.761 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:45:20.761 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:20.762 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:20.766 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:21.238 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:21.299 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:21.301 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:21.303 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:21.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:21.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:21.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:21.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:21.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:21.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:21.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:21.330 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:21.330 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:21.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:21.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:21.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:21.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:21.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:21.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:21.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:21.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:21.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:21.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:21.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:21.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:21.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:21.515 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:21.515 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:21.706 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:21.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:21.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:21.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:21.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:22.177 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:45:22.650 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:45:22.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:22.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:22.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:22.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:23.123 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:45:23.596 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-01-29 03:45:23.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:23.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:23.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:23.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:24.066 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-01-29 03:45:24.540 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-01-29 03:45:24.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:25.008 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-01-29 03:45:25.478 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-01-29 03:45:25.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:25.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:25.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:25.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:25.949 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-01-29 03:45:26.415 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-01-29 03:45:26.881 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-01-29 03:45:27.352 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-01-29 03:45:27.823 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-01-29 03:45:28.293 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-01-29 03:45:28.765 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-01-29 03:45:29.238 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-01-29 03:45:29.711 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-01-29 03:45:30.183 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-01-29 03:45:30.653 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-01-29 03:45:31.124 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-01-29 03:45:31.595 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-01-29 03:45:32.069 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-01-29 03:45:32.541 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-01-29 03:45:33.013 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-01-29 03:45:33.484 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-01-29 03:45:33.955 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-01-29 03:45:34.426 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-01-29 03:45:34.896 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-01-29 03:45:35.367 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-01-29 03:45:35.838 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-01-29 03:45:36.308 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-01-29 03:45:36.776 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-01-29 03:45:37.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:37.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:37.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:37.080 [WARNING] transceiver.py:257 (MS@172.18.128.22:6700) RX TRXD message (fn=3536 tn=7 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:37.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:37.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:37.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:37.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:37.097 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:37.097 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:37.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:37.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:37.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:37.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:37.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:37.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:37.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:37.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:37.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:37.165 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:37.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:37.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:37.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:37.165 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:37.166 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3554 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:37.166 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3554 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:37.166 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3554 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:37.166 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3554 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:37.166 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3554 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:37.166 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=3554 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:42.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:42.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:42.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:42.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:42.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:42.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:42.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:42.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:42.175 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:42.176 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:42.176 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:42.178 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:42.178 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:42.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:42.179 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:42.179 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:42.179 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:42.179 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:42.179 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:42.181 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:42.181 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:42.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:42.181 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:42.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:42.181 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:42.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:42.181 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:42.183 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:42.183 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:42.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:42.183 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:42.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:42.183 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:42.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:42.183 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:42.185 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:45:42.186 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:45:42.186 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:42.186 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:42.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:42.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:42.668 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:42.712 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:42.714 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:42.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:42.716 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:42.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:42.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:42.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:42.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:42.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:42.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:42.746 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:42.746 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:42.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:42.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:42.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:42.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:42.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:42.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:42.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:43.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:43.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:43.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:43.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:43.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:43.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:43.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:43.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:43.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:43.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:43.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:43.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:43.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:43.100 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:43.100 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:43.100 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:48.106 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:48.106 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:48.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:48.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:48.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:48.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:48.115 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:48.117 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:48.117 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:48.118 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:48.118 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:48.123 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:48.123 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:48.124 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:48.124 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:48.124 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:48.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:48.124 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:48.124 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:48.129 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:48.129 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:48.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:48.129 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:48.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:48.129 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:48.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:48.129 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:48.132 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:48.132 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:48.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:48.132 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:48.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:48.132 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:48.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:48.132 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:48.135 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:45:48.136 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:45:48.136 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:48.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:48.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:48.141 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-01-29 03:45:48.619 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-01-29 03:45:48.660 [DEBUG] fake_trx.py:278 (BTS@172.18.128.20:5700) Recv FAKE_TOA cmd
2026-01-29 03:45:48.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:48.663 [DEBUG] fake_trx.py:297 (BTS@172.18.128.20:5700) Recv FAKE_RSSI cmd
2026-01-29 03:45:48.664 [DEBUG] fake_trx.py:322 (BTS@172.18.128.20:5700) Recv FAKE_CI cmd
2026-01-29 03:45:48.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:48.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:48.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:48.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:48.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:48.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:48.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:48.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:48.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD HANDOVER
2026-01-29 03:45:48.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:48.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:48.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:48.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:49.090 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-01-29 03:45:49.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:49.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:49.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:49.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:49.562 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-01-29 03:45:50.034 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-01-29 03:45:50.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:50.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:50.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:50.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:50.505 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-01-29 03:45:50.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:50.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:50.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:50.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD ECHO
2026-01-29 03:45:50.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.128.22:6700) Ignore CMD SETSLOT
2026-01-29 03:45:50.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.128.22:6700) Recv RXTUNE cmd
2026-01-29 03:45:50.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.128.22:6700) Recv TXTUNE cmd
2026-01-29 03:45:50.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.128.22:6700) Recv POWERON CMD
2026-01-29 03:45:50.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.128.22:6700) Starting transceiver...
2026-01-29 03:45:50.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD NOHANDOVER
2026-01-29 03:45:50.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.128.22:6700) Recv POWEROFF cmd
2026-01-29 03:45:50.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.128.22:6700) Stopping transceiver...
2026-01-29 03:45:50.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.128.20:5700) Recv SETPOWER cmd
2026-01-29 03:45:50.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.128.20:5700/1) Recv SETPOWER cmd
2026-01-29 03:45:50.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.128.20:5700/2) Recv SETPOWER cmd
2026-01-29 03:45:50.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.128.20:5700/3) Recv SETPOWER cmd
2026-01-29 03:45:50.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:50.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:50.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:50.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:50.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:50.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:50.797 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:50.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=575 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:50.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=575 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:50.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=575 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:50.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=575 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:50.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=575 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:50.797 [WARNING] transceiver.py:257 (BTS@172.18.128.20:5700) RX TRXD message (ver=1 fn=575 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-01-29 03:45:55.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:55.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:55.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:55.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:55.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:55.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:55.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:55.799 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:55.799 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:55.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:45:55.800 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:45:55.801 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:45:55.801 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:45:55.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:55.801 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:55.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:55.801 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:45:55.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:45:55.801 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:45:55.803 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:45:55.803 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:45:55.803 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:55.803 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:55.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:45:55.803 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:45:55.803 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:45:55.803 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:45:55.805 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:45:55.805 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:45:55.805 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:55.805 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:45:55.805 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:45:55.805 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:45:55.805 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:45:55.805 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:45:55.808 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:45:55.809 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:45:55.809 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:45:55.809 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:55.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:45:55.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:45:55.812 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:45:55.812 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:45:55.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:46:00.816 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:46:00.816 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:46:00.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:46:00.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:46:00.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:46:00.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:46:00.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:46:00.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:46:00.820 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.128.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:46:00.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.128.20:5700) Recv SETFORMAT cmd
2026-01-29 03:46:00.820 [INFO] ctrl_if_trx.py:201 (BTS@172.18.128.20:5700) TRXD header version 1 -> 1
2026-01-29 03:46:00.821 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.128.20:5700/1) Recv RXTUNE cmd
2026-01-29 03:46:00.821 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.128.20:5700/1) Recv TXTUNE cmd
2026-01-29 03:46:00.821 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:46:00.821 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.128.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:46:00.821 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.128.20:5700/1) Recv NOMTXPOWER cmd
2026-01-29 03:46:00.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:46:00.821 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.128.20:5700/1) Recv SETFORMAT cmd
2026-01-29 03:46:00.821 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.128.20:5700/1) TRXD header version 1 -> 1
2026-01-29 03:46:00.822 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.128.20:5700/2) Recv RXTUNE cmd
2026-01-29 03:46:00.822 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.128.20:5700/2) Recv TXTUNE cmd
2026-01-29 03:46:00.822 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:46:00.822 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.128.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:46:00.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd
2026-01-29 03:46:00.822 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.128.20:5700/2) Recv NOMTXPOWER cmd
2026-01-29 03:46:00.822 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.128.20:5700/2) Recv SETFORMAT cmd
2026-01-29 03:46:00.822 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.128.20:5700/2) TRXD header version 1 -> 1
2026-01-29 03:46:00.824 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.128.20:5700/3) Recv RXTUNE cmd
2026-01-29 03:46:00.824 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.128.20:5700/3) Recv TXTUNE cmd
2026-01-29 03:46:00.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:46:00.824 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.128.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-01-29 03:46:00.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.128.20:5700/3) Recv RFMUTE cmd
2026-01-29 03:46:00.824 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.128.20:5700/3) Recv NOMTXPOWER cmd
2026-01-29 03:46:00.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.128.20:5700/3) Recv SETFORMAT cmd
2026-01-29 03:46:00.824 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.128.20:5700/3) TRXD header version 1 -> 1
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.128.20:5700) Recv RXTUNE cmd
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETTSC
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETTSC
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETTSC
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.128.20:5700) Recv TXTUNE cmd
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETRXGAIN
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETRXGAIN
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETTSC
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETRXGAIN
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.128.20:5700) Recv NOMTXPOWER cmd
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.827 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.128.20:5700) Recv POWERON CMD
2026-01-29 03:46:00.827 [INFO] ctrl_if_trx.py:109 (BTS@172.18.128.20:5700) Starting transceiver...
2026-01-29 03:46:00.827 [INFO] transceiver.py:243 Starting clock generator
2026-01-29 03:46:00.827 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETRXGAIN
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.128.20:5700/1) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.128.20:5700/1) Recv RFMUTE cmd
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.128.20:5700) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.128.20:5700) Recv RFMUTE cmd
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.128.20:5700/2) Ignore CMD SETSLOT
2026-01-29 03:46:00.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.128.20:5700) Recv POWEROFF cmd
2026-01-29 03:46:00.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.128.20:5700) Stopping transceiver...
2026-01-29 03:46:00.830 [INFO] transceiver.py:246 Stopping clock generator
2026-01-29 03:46:00.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.128.20:5700/3) Ignore CMD SETSLOT
2026-01-29 03:46:00.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.128.20:5700/2) Recv RFMUTE cmd